CN115576766A - Flash memory management algorithm debugging method, system, device and readable storage medium - Google Patents
Flash memory management algorithm debugging method, system, device and readable storage medium Download PDFInfo
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Abstract
The application discloses a method, a system, equipment and a readable storage medium for debugging a flash memory management algorithm, wherein the method comprises the following steps: generating a test excitation based on a preset excitation generation mode when a test instruction is received; starting a virtual micro control unit and sending the test excitation to the virtual micro control unit, wherein after the virtual micro control unit is started, a flash memory management algorithm to be debugged is operated, so that the virtual micro control unit can process the test excitation; and acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module so as to control the storage module to finish a storage action. Therefore, the technical problem that the time cost for debugging the master control and the FTL of the solid state disk in the related technology is high is effectively solved, and the fast completion of the master control and the FTL debugging of the solid state disk is further realized.
Description
Technical Field
The present application relates to the field of fast storage technologies, and in particular, to a flash memory management algorithm debugging method, a flash memory management algorithm debugging system, a flash memory management algorithm debugging device, and a computer-readable storage medium.
Background
Solid State Drives (SSDs) employ semiconductors as storage media. The method does not need to depend on any mechanical device and seek, thereby reducing the access delay of the I/O request, and gradually replacing a mechanical hard disk with the advantages of low power consumption, shock resistance, falling resistance, small size and the like.
Flash memory (NAND Flash) is mostly used as a storage medium in SSD, and the storage mode of NAND Flash depends on its physical characteristics, so that the existing file system cannot directly access or operate SSD, and in order for the file system to access SSD like accessing a mechanical hard disk, it is necessary to add a software Layer FTL (Flash Translation Layer) between NAND Flash and the file system.
In the related art, the FTL runs in a micro control unit of the solid state disk, and a processor of the micro control unit has a low frequency, which takes a long time to debug the FTL.
Disclosure of Invention
The embodiment of the application provides a flash memory management algorithm debugging method, a flash memory management algorithm debugging system, a flash memory management algorithm debugging device and a computer readable storage medium, solves the technical problem that the time cost for debugging the master control and the FTL of the solid state disk in the related technology is high, and achieves the technical effect of rapidly completing the master control and the FTL debugging of the solid state disk.
The embodiment of the application provides a flash memory management algorithm debugging method, which comprises the following steps:
generating a test excitation based on a preset excitation generation mode when a test instruction is received;
starting a virtual micro control unit and sending the test excitation to the virtual micro control unit, wherein after the virtual micro control unit is started, a flash memory management algorithm to be debugged is operated, so that the virtual micro control unit can process the test excitation;
and acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module so as to control the storage module to finish a storage action.
Optionally, the generating a test stimulus based on a preset stimulus generating manner when the test instruction is received includes:
when the test instruction is received, the virtual host determines a service flow corresponding to the test instruction;
and operating the virtual drive corresponding to the test instruction, and generating the test excitation according to the business process.
Optionally, the starting a virtual microcontrol unit and sending the test stimulus to the virtual microcontrol unit, where after the virtual microcontrol unit is started, the running of a flash management algorithm to be debugged is performed, so that the virtual microcontrol unit can process the test stimulus, including:
after receiving the test stimulus, the virtual micro-control unit determines a processor associated with the virtual micro-control unit and sends the test stimulus to the processor;
and after the processor receives the test excitation, operating the flash memory management algorithm to process the test excitation.
Optionally, after the processor receives the test stimulus, the flash management algorithm is run, and processing the test stimulus includes:
after the processor receives the test stimulus, determining a logic address corresponding to the test stimulus;
and based on a preset mapping relation, storing the logic address and the physical address of the storage module in a logic mapping table in an associated manner.
Optionally, the associating and storing the logical address and the physical address of the storage module before the logical mapping table based on the preset mapping relationship further includes:
determining a flash memory block to be executed in the storage module based on a preset wear leveling function;
determining the physical address of the to-be-executed flash block.
Optionally, the obtaining a processing result of the test stimulus by the virtual micro control unit, and sending the processing result to a storage module to control the storage module to complete a storage action includes:
after receiving the processing result, the storage module determines data to be stored corresponding to the processing result;
and determining the logic address of the data to be stored, and storing the logic address.
Optionally, the starting a virtual microcontrol unit and sending the test excitation to the virtual microcontrol unit, where after the virtual microcontrol unit is started, the virtual microcontrol unit runs a flash memory management algorithm to be debugged, so that after the virtual microcontrol unit can process the test excitation, the method further includes:
acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module;
after the storage module receives the processing result, determining a physical address of the data to be read corresponding to the processing result;
and reading the physical address based on a logic mapping table included in the processing result.
In addition, the application also provides a flash memory management algorithm debugging system, which comprises a virtual host, wherein the virtual host generates test excitation corresponding to a test instruction after receiving the test instruction, and sends the test excitation to a virtual micro control unit;
the virtual micro-control unit sends the test excitation to the processor after receiving the test excitation, so that the processor is called to run a flash memory management algorithm to process the test excitation;
the storage module executes a storage action corresponding to the processing result after receiving the processing result sent by the virtual micro control unit;
and the processor runs a flash memory management algorithm to process the test excitation after receiving the test excitation sent by the virtual micro control unit.
In addition, the present application further provides a flash memory management algorithm debugging device, where the flash memory management algorithm debugging device includes a memory, a processor, and a flash memory management algorithm debugging program stored on the memory and capable of running on the processor, and the processor implements the steps of the flash memory management algorithm debugging method when executing the flash memory management algorithm debugging program.
In addition, the present application also provides a computer readable storage medium, where a flash memory management algorithm debugging program is stored, and when the flash memory management algorithm debugging program is executed by a processor, the steps of the flash memory management algorithm debugging method as described above are implemented.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
1. because the test excitation is generated based on the preset excitation generation mode when the test instruction is received; starting a virtual micro control unit and sending the test excitation to the virtual micro control unit, wherein after the virtual micro control unit is started, a flash memory management algorithm to be debugged is operated, so that the virtual micro control unit can process the test excitation; and acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module to control the storage module to finish a storage action, so that the technical problem of high time cost for debugging the master control and the FTL of the solid state disk in the related art is effectively solved, and the master control and the FTL debugging of the solid state disk are quickly finished.
2. After the virtual micro control unit is started, the test excitation is sent to the processor associated with the virtual micro control unit, and the computing power of the processor is called to run the flash memory management algorithm, so that the test excitation is processed by the processor, the technical problem of high time cost for debugging the master control and the FTL of the solid state disk in the related technology is effectively solved, and the master control and the FTL debugging of the solid state disk are quickly completed.
3. After the processor receives the test excitation, determining a logical address corresponding to the test excitation, and storing the logical address and a physical address of a flash memory particle in a storage module in a logic mapping table in an associated manner based on a preset mapping relation; and meanwhile, determining a flash memory block to be executed in the storage module based on a preset wear leveling function, and taking a physical address of the flash memory block to be executed as the physical address associated with the logical address. Therefore, the technical problem that the time cost for debugging the master control and the FTL of the solid state disk in the related technology is high is effectively solved, and the fast completion of the master control and the FTL debugging of the solid state disk is further realized.
4. After a storage module receives a processing result of test excitation, determining data to be stored corresponding to the processing result, determining a logical address of the data to be stored, and storing the logical address into a physical address associated with the logical address; and determining a physical address of the data to be read corresponding to the processing result, and reading a logical address associated with the physical address, so that the technical problem of high time cost for debugging the master control and the FTL of the solid state disk in the related technology is effectively solved, and the master control and the FTL debugging of the solid state disk are quickly completed.
Drawings
FIG. 1 is a schematic flowchart of a first embodiment of a flash memory management algorithm debugging method according to the present application;
FIG. 2 is a flowchart illustrating a step S20 of the flash memory management algorithm debugging method according to the present application;
FIG. 3 is a flowchart illustrating a second embodiment of a debugging method of a flash memory management algorithm according to the present application;
FIG. 4 is a schematic flowchart of a third embodiment of a flash memory management algorithm debugging method according to the present application;
fig. 5 is a schematic diagram of a hardware structure related to an embodiment of a flash memory management algorithm debugging device according to the present application.
Detailed Description
In the related art, after a flash memory granule manufacturer issues a new flash memory granule, a solid state disk manufacturer needs to develop a new master control and flash memory management algorithm for the new flash memory granule; however, a solid state disk manufacturer cannot take new flash memory particles at the first time, and the processing frequency of the solid state disk master control is low, so that the time cost of the solid state disk master control development process and the flash memory management algorithm debugging process is too high. The embodiment of the application adopts the following main technical scheme: the method comprises the steps that when a virtual host receives a test instruction, a test excitation is generated based on a preset mode; sending the test excitation to a virtual micro control unit to control the virtual micro control unit to call the computing power of a processor and run a flash memory management algorithm; and sending the processing result of the test excitation to a storage module so as to control the storage module to complete corresponding storage action. Therefore, the main control and FTL debugging of the solid state disk are completed quickly.
In order to better understand the above technical solutions, exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example one
The embodiment of the application discloses a flash memory management algorithm debugging method, and with reference to fig. 1, the flash memory management algorithm debugging method includes:
step S10, when a test instruction is received, generating a test excitation based on a preset excitation generation mode;
in this embodiment, the test instruction may be regarded as an instruction for starting a test, and the test instruction may also include data to be read or written, and may also include a terminal model to be simulated by the test stimulus. And when the virtual host receives the test instruction, generating corresponding test excitation based on a preset excitation generation mode.
Optionally, step S10 includes:
step S11, when the test instruction is received, the virtual host machine determines a service process corresponding to the test instruction;
and S12, operating the virtual drive corresponding to the test instruction, and generating the test excitation according to the business process.
As an optional implementation manner, when receiving a test instruction, a virtual host determines a service flow corresponding to the test instruction and a terminal model to be simulated; calling a corresponding script in a pre-stored script library according to the terminal model, and determining a virtual drive associated with the script; and operating the virtual drive to generate the test excitation corresponding to the business process.
Step S20, starting a virtual micro control unit and sending the test excitation to the virtual micro control unit, wherein the virtual micro control unit runs a flash memory management algorithm to be debugged after being started, so that the virtual micro control unit can process the test excitation;
in this embodiment, the virtual micro-control unit processes the received test stimulus by operating the flash memory management algorithm, and sends the processing result to the storage module to control the storage module to execute the corresponding read-write operation. The virtual micro control unit is associated with the processor, so that the computing power of the processor can be called to execute the operation. The processor may be a processor of a terminal where the virtual micro control unit is located, or may be a processor that establishes a wired or wireless connection with the terminal, so that the terminal can invoke other terminals connected thereto. Multiple processors may also be invoked simultaneously, and are not specifically limited herein.
Alternatively, referring to fig. 2, step S20 includes:
step S21, after receiving the test excitation, the virtual micro-control unit determines a processor associated with the virtual micro-control unit and sends the test excitation to the processor;
and S22, after the processor receives the test excitation, operating the flash memory management algorithm to process the test excitation.
As an optional implementation manner, after receiving the test stimulus, the virtual micro control unit determines a processor associated with the virtual micro control unit, and sends the test stimulus to the processor, and after receiving the test stimulus, the processor runs the flash memory management algorithm to be debugged, so that the processor can process the test stimulus and generate a processing result of the test stimulus.
Illustratively, the processor associated with the virtual microcontrol unit is the processor of the terminal on which the virtual microcontrol unit operates.
The processor associated with the virtual microcontrol unit is illustratively the processor of the terminal connected to the terminal on which the virtual microcontrol unit operates.
And S30, acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module so as to control the storage module to finish a storage action.
In this embodiment, after the virtual micro control unit processes the test stimulus, the corresponding processing result is sent to the storage module, so as to control the storage module to execute a read operation or a write operation corresponding to the test stimulus.
Optionally, the storage module may be a virtual flash memory granule or a physical flash memory granule.
As an optional implementation manner, after the virtual micro control unit finishes processing the test stimulus, an interface between the virtual micro control unit and the storage module is called, a corresponding processing result is sent to the storage module through the interface, after the storage module receives the processing result, the corresponding read operation or write operation is executed according to the processing result, and after the execution of the operation is finished, execution completion information is sent to the virtual micro control unit.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
because the test excitation is generated based on the preset excitation generation mode when the test instruction is received; starting a virtual micro control unit and sending the test excitation to the virtual micro control unit, wherein after the virtual micro control unit is started, a flash memory management algorithm to be debugged is operated, so that the virtual micro control unit can process the test excitation; and acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module to control the storage module to finish a storage action, so that the technical problem of high time cost for debugging the master control and the FTL of the solid state disk in the related technology is effectively solved, and the master control and the FTL debugging of the solid state disk are quickly finished.
After the virtual micro control unit is started, the test excitation is sent to the processor associated with the virtual micro control unit, and the computing power of the processor is called to run the flash memory management algorithm, so that the test excitation is processed by the processor, the technical problem of high time cost for debugging the master control and the FTL of the solid state disk in the related technology is effectively solved, and the master control and the FTL debugging of the solid state disk are quickly completed.
Example two
Based on the first embodiment, the second embodiment of the present application discloses a method for debugging a flash memory management algorithm, and referring to fig. 3, step S22 includes:
step S210, after the processor receives the test excitation, determining a logic address corresponding to the test excitation;
step S220, based on a preset mapping relationship, storing the logical address and the physical address of the storage module in a logical mapping table in an associated manner.
In this embodiment, the functions that can be realized by operating the flash memory management algorithm include storing a logical address corresponding to the test stimulus in association with a physical address of the storage module, and establishing a logical mapping table, where the logical mapping table includes an association relationship between the logical address and the physical address, and when the storage module performs a read-write operation, corresponding data can be read or written according to the logical mapping table.
As an optional implementation manner, after receiving a test stimulus, the processor determines a logical address corresponding to the test stimulus when the test stimulus is a read test; determining a physical address of data to be read in a memory module; and storing the association between the logical address and the physical address in a logical mapping table.
As another optional implementation manner, after receiving a test stimulus, the processor determines a logical address corresponding to the test stimulus when the test stimulus is a write test; and determining the physical address of the flash memory block to be executed in the storage module, and storing the association between the logical address and the physical address in a logical mapping table.
Optionally, before step S220, the method further includes:
step S230, determining a flash memory block to be executed in the storage module based on a preset wear leveling function;
step S240, determining the physical address of the to-be-executed flash memory block.
In this embodiment, the functions that can be realized by running the flash memory management algorithm include the balance management of the service life of the flash memory granules in the storage module, and the wear leveling function can be obtained from a parameter manual of the flash memory granules.
As an optional implementation manner, the processor runs a flash memory management algorithm, determines a part of flash memory granules in the storage module based on a preset wear leveling function, marks the flash memory granules as to-be-executed flash memory blocks, and determines physical addresses of the to-be-executed flash memory blocks, so that the service lives of the flash memory granules in the storage module are balanced as a whole.
Optionally, step S20 further includes:
step S250, after the processor receives the test excitation, determining a service process corresponding to the test excitation;
step S260, when the service process is storage data, determining to-be-stored data corresponding to the test excitation, and determining redundant data of the to-be-stored data based on a preset error correction algorithm;
updating the data to be stored based on the data to be stored and the redundant data;
step S270, when the service process is data reading, determining data to be read corresponding to the test excitation, checking the data to be read based on a preset error correction algorithm, and determining redundant data corresponding to the data to be read;
updating the data to be read according to the redundant data;
as an optional implementation manner, when the virtual micro control unit controls the storage module to store data, a flash memory management algorithm is operated, redundant data is calculated based on the data to be stored, and the data to be stored and the redundant data are simultaneously stored in the storage module.
As another optional implementation manner, when the virtual micro control unit controls the memory module to read data, the virtual micro control unit operates a flash memory management algorithm, checks data to be read, and updates the data to be read based on redundant data corresponding to the data to be read.
Illustratively, when the data to be read has an error relative to the original data, a flash memory management algorithm is run, and the error is corrected based on the redundant data corresponding to the data to be read, so as to obtain the original data.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
after the processor receives the test excitation, determining a logical address corresponding to the test excitation, and storing the logical address and a physical address of a flash memory particle in a storage module in a logical mapping table in an associated manner based on a preset mapping relation; and meanwhile, determining a flash memory block to be executed in the storage module based on a preset wear leveling function, and taking a physical address of the flash memory block to be executed as the physical address associated with the logical address. Therefore, the technical problem that time cost for debugging the master control and the FTL of the solid state disk is high in the related technology is effectively solved, and the master control and the FTL debugging of the solid state disk are rapidly completed.
EXAMPLE III
Based on the first embodiment, the third embodiment of the present application discloses a flash memory management algorithm debugging method, and referring to fig. 4, step S30 includes:
step S310, after receiving the processing result, the storage module determines data to be stored corresponding to the processing result;
step S320, determining a logical address of the data to be stored, and storing the logical address.
In this embodiment, the processing result includes a logic mapping table, so that the virtual microcontrol unit determines a corresponding physical address in the storage module according to a logic address corresponding to the test stimulus.
As an optional implementation manner, after receiving a processing result sent by a virtual micro control unit, a storage module determines data to be stored corresponding to the processing result, and determines a logic address corresponding to the data to be stored; and determining flash memory particles to be stored in a storage module based on a logic mapping table included in the processing result, and storing the logic address into the storage module based on the physical address of the flash memory particles.
As another optional implementation manner, when the storage module is a virtual flash granule, determining a first logical address of data to be stored, determining a second logical address of the virtual flash granule based on a logical mapping table included in a processing result, and storing the first logical address into the virtual flash granule; and determining the physical address of the entity memory corresponding to the second logical address based on a preset mapping relation, and storing the first logical address into the entity memory.
Illustratively, when the storage module is a virtual flash memory granule, the logic mapping table stores an association relationship between a first logic address corresponding to the test stimulus and a second logic address corresponding to the virtual flash memory granule.
Optionally, after step S20, the method further includes:
step S330, acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module;
step S340, after the storage module receives the processing result, determining a physical address of the data to be read corresponding to the processing result;
step S350, reading the physical address based on the logical mapping table included in the processing result.
In the embodiment, no matter whether the read operation or the storage operation is executed, only the logical address of the data to be executed is read or stored, so that the debugging progress is accelerated, and the time cost is saved.
As an optional implementation manner, after the virtual micro control unit completes the test excitation, the virtual micro control unit sends a corresponding processing result to a storage module, and after the storage module receives the processing result, determines to-be-read data corresponding to the processing result, and determines a physical address of the to-be-read data in the storage module; and reading the physical address based on a logic mapping table included in the processing result. Namely, the physical address is taken as data to be read when reading.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
after a storage module receives a processing result of test excitation, determining data to be stored corresponding to the processing result, determining a logical address of the data to be stored, and storing the logical address into a physical address associated with the logical address; and determining a physical address of the data to be read corresponding to the processing result, and reading a logical address associated with the physical address, so that the technical problem of high time cost for debugging the master control and the FTL of the solid state disk in the related technology is effectively solved, and the master control and the FTL debugging of the solid state disk are quickly completed.
The present application further provides a flash memory management algorithm debugging device, and referring to fig. 5, fig. 5 is a schematic structural diagram of a flash memory management algorithm debugging device in a hardware operating environment according to the embodiment of the present application.
As shown in fig. 5, the flash management algorithm debugging device may include: a processor 1001, such as a Central Processing Unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a WIreless interface (e.g., a WIreless-FIdelity (WI-FI) interface). The Memory 1005 may be a Random Access Memory (RAM) Memory, or may be a Non-Volatile Memory (NVM), such as a disk Memory. The memory 1005 may alternatively be a storage device separate from the processor 1001 described previously.
Those skilled in the art will appreciate that the architecture shown in FIG. 5 does not constitute a limitation of the flash management algorithm debug apparatus, and may include more or fewer components than those shown, or some components in combination, or a different arrangement of components.
Optionally, the memory 1005 is electrically connected to the processor 1001, and the processor 1001 may be configured to control the operation of the memory 1005 and may further read data in the memory 1005 to implement the flash memory management algorithm debugging.
Alternatively, as shown in fig. 5, the memory 1005, which is a storage medium, may include therein an operating system, a data storage module, a network communication module, a user interface module, and a flash memory management algorithm debugging program.
Optionally, in the flash memory management algorithm debugging device shown in fig. 5, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 of the flash memory management algorithm debugging device of the present application may be disposed in the flash memory management algorithm debugging device.
As shown in fig. 5, the flash management algorithm debugging device calls a flash management algorithm debugging program stored in a memory 1005 through a processor 1001, and performs the operations of the related steps of the flash management algorithm debugging method provided in the embodiment of the present application:
generating a test excitation based on a preset excitation generation mode when a test instruction is received;
starting a virtual micro control unit and sending the test excitation to the virtual micro control unit, wherein after the virtual micro control unit is started, a flash memory management algorithm to be debugged is operated, so that the virtual micro control unit can process the test excitation;
and acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module so as to control the storage module to finish a storage action.
Alternatively, the processor 1001 may call a flash management algorithm debugger stored in the memory 1005, and further perform the following operations:
when the test instruction is received, the virtual host determines a service flow corresponding to the test instruction;
and running the virtual drive corresponding to the test instruction, and generating the test excitation according to the service flow.
Alternatively, the processor 1001 may call a flash management algorithm debugger stored in the memory 1005, and further perform the following operations:
after receiving the test stimulus, the virtual micro-control unit determines a processor associated with the virtual micro-control unit and sends the test stimulus to the processor;
and after the processor receives the test excitation, operating the flash memory management algorithm to process the test excitation.
Alternatively, the processor 1001 may call a flash management algorithm debugger stored in the memory 1005, and further perform the following operations:
after the processor receives the test stimulus, determining a logic address corresponding to the test stimulus;
and based on a preset mapping relation, storing the logic address and the physical address of the storage module in a logic mapping table in an associated manner.
Alternatively, the processor 1001 may call a flash management algorithm debugger stored in the memory 1005, and further perform the following operations:
determining a flash memory block to be executed in the storage module based on a preset wear leveling function;
determining the physical address of the to-be-executed flash block.
Alternatively, the processor 1001 may call a flash management algorithm debugger stored in the memory 1005, and further perform the following operations:
after receiving the processing result, the storage module determines data to be stored corresponding to the processing result;
and determining the logical address of the data to be stored, and storing the logical address.
Alternatively, the processor 1001 may call a flash management algorithm debugger stored in the memory 1005, and further perform the following operations:
acquiring a processing result of the virtual micro control unit on the test excitation, and sending the processing result to a storage module;
after the storage module receives the processing result, determining a physical address of the data to be read corresponding to the processing result;
and reading the physical address based on a logic mapping table included in the processing result.
In addition, the present application further provides a flash memory management algorithm debugging system, which includes:
the virtual host generates a test excitation corresponding to the test instruction after receiving the test instruction, and sends the test excitation to the virtual micro-control unit;
the virtual micro-control unit sends the test excitation to the processor after receiving the test excitation, so that the processor is called to run a flash memory management algorithm to process the test excitation;
the storage module executes a storage action corresponding to the processing result after receiving the processing result sent by the virtual micro control unit;
and the processor runs a flash memory management algorithm to process the test excitation after receiving the test excitation sent by the virtual micro control unit.
In addition, an embodiment of the present application further provides a computer-readable storage medium, where a flash memory management algorithm debugging program is stored on the computer-readable storage medium, and when being executed by a processor, the flash memory management algorithm debugging program implements relevant steps of any embodiment of the flash memory management algorithm debugging method described above.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means can be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A flash memory management algorithm debugging method is characterized by comprising the following steps:
generating a test excitation based on a preset excitation generation mode when a test instruction is received;
starting a virtual micro control unit and sending the test excitation to the virtual micro control unit, wherein after the virtual micro control unit is started, a flash memory management algorithm to be debugged is operated, so that the virtual micro control unit can process the test excitation;
and acquiring a processing result of the virtual micro control unit on the test excitation, and sending the processing result to a storage module to control the storage module to finish a storage action.
2. The flash memory management algorithm debugging method of claim 1, wherein generating the test stimulus based on a preset stimulus generation manner upon receiving the test instruction comprises:
when the test instruction is received, the virtual host machine determines a service flow corresponding to the test instruction;
and operating the virtual drive corresponding to the test instruction, and generating the test excitation according to the business process.
3. The method of claim 1, wherein the booting a virtual mcu and sending the test stimulus to the virtual mcu, wherein the running of the mcu after booting the flash management algorithm to be debugged so that the mcu can process the test stimulus comprises:
after receiving the test stimulus, the virtual micro-control unit determines a processor associated with the virtual micro-control unit and sends the test stimulus to the processor;
and after the processor receives the test excitation, operating the flash memory management algorithm to process the test excitation.
4. The flash management algorithm debugging method of claim 3, wherein said executing the flash management algorithm after the processor receives the test stimulus, the processing of the test stimulus comprising:
after the processor receives the test stimulus, determining a logic address corresponding to the test stimulus;
and storing the logic address and the physical address of the storage module in a logic mapping table in an associated manner based on a preset mapping relation.
5. The flash memory management algorithm debugging method of claim 4, wherein the associating the logical address with the physical address of the storage module based on the preset mapping relationship is stored before a logical mapping table, further comprising:
determining a flash memory block to be executed in the storage module based on a preset wear leveling function;
determining the physical address of the to-be-executed flash block.
6. The method for debugging flash memory management algorithm according to claim 1, wherein the obtaining the processing result of the virtual microcontrol unit on the test stimulus and sending the processing result to a storage module to control the storage module to complete a storage action comprises:
after receiving the processing result, the storage module determines data to be stored corresponding to the processing result;
and determining the logical address of the data to be stored, and storing the logical address.
7. The method of claim 1, wherein the booting a virtual mcu and sending the test stimulus to the virtual mcu, wherein the virtual mcu after booting runs a flash management algorithm to be debugged so that the virtual mcu can process the test stimulus, further comprises:
acquiring a processing result of the test excitation by the virtual micro control unit, and sending the processing result to a storage module;
after the storage module receives the processing result, determining a physical address of the data to be read corresponding to the processing result;
and reading the physical address based on a logic mapping table included in the processing result.
8. A flash memory management algorithm debugging system, comprising:
the virtual host generates a test excitation corresponding to the test instruction after receiving the test instruction, and sends the test excitation to the virtual micro-control unit;
the virtual micro-control unit sends the test excitation to the processor after receiving the test excitation, so that the processor is called to run a flash memory management algorithm to process the test excitation;
the storage module executes a storage action corresponding to the processing result after receiving the processing result sent by the virtual micro control unit;
and the processor runs a flash memory management algorithm to process the test excitation after receiving the test excitation sent by the virtual micro control unit.
9. A flash memory management algorithm debugging device comprising a memory, a processor and a flash memory management algorithm debugging program stored on the memory and executable on the processor, wherein the processor implements the steps of the flash memory management algorithm debugging method according to any one of claims 1 to 7 when executing the flash memory management algorithm debugging program.
10. A computer-readable storage medium, having stored thereon a flash management algorithm debugging program, which when executed by a processor, performs the steps of the flash management algorithm debugging method of any one of claims 1 to 7.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211312389.4A CN115576766A (en) | 2022-10-25 | 2022-10-25 | Flash memory management algorithm debugging method, system, device and readable storage medium |
| PCT/CN2023/096119 WO2024087607A1 (en) | 2022-10-25 | 2023-05-24 | Flash memory management algorithm debugging method, system and device, and readable storage medium |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211312389.4A CN115576766A (en) | 2022-10-25 | 2022-10-25 | Flash memory management algorithm debugging method, system, device and readable storage medium |
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| WO2024087607A1 (en) * | 2022-10-25 | 2024-05-02 | 深圳市硅格半导体有限公司 | Flash memory management algorithm debugging method, system and device, and readable storage medium |
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| US10200271B2 (en) * | 2016-04-12 | 2019-02-05 | International Business Machines Corporation | Building and testing composite virtual services using debug automation |
| CN110287076A (en) * | 2018-03-19 | 2019-09-27 | 北京兆易创新科技股份有限公司 | A kind of method for testing memory and device |
| CN113342697B (en) * | 2021-07-19 | 2022-08-26 | 英韧科技(上海)有限公司 | Simulation test system and method for flash translation layer |
| CN115576766A (en) * | 2022-10-25 | 2023-01-06 | 深圳市硅格半导体有限公司 | Flash memory management algorithm debugging method, system, device and readable storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024087607A1 (en) * | 2022-10-25 | 2024-05-02 | 深圳市硅格半导体有限公司 | Flash memory management algorithm debugging method, system and device, and readable storage medium |
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