CN115549676A - Reference sampling phase-locked loop suitable for low-voltage application - Google Patents

Reference sampling phase-locked loop suitable for low-voltage application Download PDF

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CN115549676A
CN115549676A CN202211029887.8A CN202211029887A CN115549676A CN 115549676 A CN115549676 A CN 115549676A CN 202211029887 A CN202211029887 A CN 202211029887A CN 115549676 A CN115549676 A CN 115549676A
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sampling
phase
signal
voltage
frequency divider
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丁瑞雪
黄林国
孙德鹏
步枫
刘术彬
朱樟明
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention relates to a reference sampling phase-locked loop suitable for low-voltage application, which comprises: the device comprises a reference sampling phase discriminator module, a low-pass filter module, a voltage-controlled oscillator, a frequency divider module and a clock signal generating module. The invention reduces the on-resistance of the sampling switch by adopting the high-level boost inverter, and reduces the sampling time constant under low voltage, thereby realizing the normal sampling and holding function. And meanwhile, the noise is improved by using a larger sampling capacitor, and the normal sampling operation and the excellent clock jitter performance of the phase-locked loop under low voltage are realized. And a low-pass filter is added at the output end of the reference sampling phase discriminator, and a high-frequency pole is introduced, so that the reference stray is improved on the premise of not influencing the phase margin. And the combination of the current mode logic frequency divider and the multi-mode programmable frequency divider is adopted to realize the normal operation of the reference sampling phase-locked loop under low voltage and the excellent stray and clock jitter performance.

Description

Reference sampling phase-locked loop suitable for low-voltage application
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a reference sampling phase-locked loop suitable for low-voltage application.
Background
For a phase-locked loop system, performance indexes such as clock jitter, spurs, phase noise, power consumption and area are all important. The traditional charge pump phase-locked loop is limited due to the problem that the phase noise and the clock jitter performance need to be improved by sacrificing large power consumption and filter area, so that the requirement of people on a better phase-locked loop architecture is promoted. The sub-sampling phase-locked loop and the injection locking phase-locked loop proposed in the past also have the problems that the phase discrimination range is too small and the spurious is affected by harmonic waves respectively.
In contrast, in recent years, a reference sampling phase-locked loop (rppll) architecture has been proposed to optimize phase noise and clock jitter by converting a phase difference between an input reference signal and a feedback signal of the rppll into a voltage using a Reference Sampling Phase Detector (RSPD) for comparison to increase in-band gain. In order to further reduce the power consumption of the phase-locked loop, reducing the power supply voltage is the most direct method, however, the on-resistance RON of the sampler during low-voltage operation is increased, and the sampling time constant τ is increased, so that the sampler cannot realize a normal sampling and holding function, and the reference sampling phase-locked loop cannot realize a normal phase-locked function. At the same time, only a smaller sampling capacitor can be used to maintain the sampling time constant to be much smaller than the reference period tau = RC < < TREF, which causes the deterioration of the sampling thermal noise. Under the low-voltage work, the power consumption of a digital circuit is reduced, the cost is the reduction of the working speed, the frequency divider cannot realize the normal frequency division function when working at high frequency, and the working frequency of the phase-locked loop is limited.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a reference sampling phase-locked loop adapted to low voltage applications. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a reference sampling phase-locked loop suitable for low-voltage application, which comprises: a reference sampling phase discriminator module, a low pass filter module, a voltage controlled oscillator, a frequency divider module, and a clock signal generation module, wherein,
a differential reference signal is input into a reference signal input end of the reference sampling phase discriminator module, and an output end of the reference sampling phase discriminator module is connected with an input end of the low-pass filter module; the output end of the low-pass filter module is connected with the input end of the voltage-controlled oscillator, and the output signal of the voltage-controlled oscillator is used as the clock signal output by the phase-locked loop; the input end of the frequency divider module is connected with the output end of the voltage-controlled oscillator, and the output end of the frequency divider module is connected with the input end of the clock signal generation module; the output end of the clock signal generation module is connected with the feedback signal input end of the reference sampling phase discriminator module;
the reference sampling phase discriminator module carries out sampling, holding and tracking on the input differential reference signal to obtain a differential sampling output signal; the low-pass filter module performs low-pass filtering processing on the differential sampling output signal to obtain a differential voltage signal with reduced ripple waves; the differential voltage signal is used as the control voltage of the voltage-controlled oscillator to control the output frequency of the voltage-controlled oscillator; the frequency divider module divides the frequency of the output signal of the voltage-controlled oscillator to obtain a frequency-divided output signal; the clock signal generation module generates a feedback clock signal according to the frequency division output signal, and the reference sampling phase discriminator module samples the differential reference signal according to the feedback clock signal.
In an embodiment of the present invention, the reference sampling phase detector module includes two reference sampling phase detectors, reference signal input ends of the two reference sampling phase detectors correspondingly input a first differential reference signal and a second differential reference signal, and output ends correspondingly output a first differential sampling output signal and a second differential sampling output signal.
In an embodiment of the present invention, the low-pass filter module includes two low-pass filters, where the two low-pass filters are correspondingly connected to the two reference sampling phase detectors, and respectively perform low-pass filtering processing on the first differential sampling output signal and the second differential sampling output signal to obtain a first differential voltage signal and a second differential voltage signal correspondingly.
In one embodiment of the invention, the low pass filter is a passive filter, a switched capacitor filter or an active filter.
In one embodiment of the present invention, the frequency divider module includes a first frequency divider and a second frequency divider connected in sequence, an input terminal of the first frequency divider is connected to an output terminal of the voltage-controlled oscillator, and an output terminal of the second frequency divider is connected to an input terminal of the clock signal generation module;
wherein the first frequency divider is an injection locking frequency divider, a current mode logic frequency divider, a true single-phase clock trigger frequency divider or a Miller frequency divider; the second frequency divider is a multi-mode programmable frequency divider.
In one embodiment of the invention, the clock signal generation module comprises a two-phase non-overlapping clock generator and two high-level boost inverters, wherein,
the input end of the two-phase non-overlapping clock generator is connected with the output end of the frequency divider module, and the output end of the two-phase non-overlapping clock generator is correspondingly connected with the two high-level boost inverters;
the two-phase non-overlapping clock generator carries out time sequence processing on the frequency division output signal to obtain a first two-phase non-overlapping narrow pulse signal and a second two-phase non-overlapping narrow pulse signal;
the first two-phase non-overlapped narrow pulse signal is subjected to boosting processing by a corresponding high-level boosting inverter to obtain a first feedback clock signal;
the second two-phase non-overlapped narrow pulse signal is subjected to boosting processing by a corresponding high-level boosting inverter to obtain a second feedback clock signal;
the first feedback clock signal and the second feedback clock signal are respectively input into feedback signal input ends of the two reference sampling phase detectors.
In one embodiment of the present invention, the high-level boost inverter includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a first capacitor, wherein,
the source electrode of the first MOS tube and the source electrode of the third MOS tube are both connected with a power supply end;
the grid electrode of the first MOS tube is respectively connected with the grid electrode of the second MOS tube, the grid electrode of the fourth MOS tube and the grid electrode of the fifth MOS tube, and the drain electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube and the first polar plate of the first capacitor;
the source electrode of the second MOS tube and the source electrode of the fifth MOS tube are both connected with a grounding end;
the drain electrode of the third MOS tube is respectively connected with the second pole plate of the first capacitor and the source electrode of the fourth MOS tube, and the grid electrode of the third MOS tube is respectively connected with the drain electrode of the fourth MOS tube and the drain electrode of the fifth MOS tube;
and the grid electrode of the first MOS tube is used as the input end of the high-level boost phase inverter, and the grid electrode of the third MOS tube is used as the output end of the high-level boost phase inverter.
In one embodiment of the present invention, the reference sampling phase detector comprises a first sampling switch, a second sampling switch, a first sampling capacitor, and a second sampling capacitor, wherein,
the first sampling switch and the second sampling switch are connected in series, a first end of the first sampling switch is used as a reference signal input end of the reference sampling phase discriminator, and a second end of the second sampling switch is used as an output end of the reference sampling phase discriminator;
the first sampling capacitor is connected between the second end of the first sampling switch and the ground terminal, and the second sampling capacitor is connected between the second end of the second sampling switch and the ground terminal;
the first sampling switch is turned on or turned off according to the first feedback clock signal, and the second sampling switch is turned on or turned off according to the second feedback clock signal.
Compared with the prior art, the invention has the beneficial effects that:
1. the reference sampling phase-locked loop suitable for low-voltage application of the invention improves the reference stray on the premise of not influencing the phase margin by adding the low-pass filter at the output end of the reference sampling phase discriminator and introducing the high-frequency pole.
2. The reference sampling phase-locked loop suitable for low-voltage application utilizes the high-level boost inverter to reduce the on-resistance of the sampling switch, and realizes the normal sampling and holding functions of the sampler under low voltage.
3. The reference sampling phase-locked loop suitable for low-voltage application adopts two frequency dividers, utilizes the high-speed frequency divider to reduce the working frequency required by the multi-mode programmable frequency divider, solves the problem of reduction of the working speed of the frequency divider caused by low-voltage work, and thus improves the working frequency which can be realized by the phase-locked loop.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a block diagram of a reference sampling phase-locked loop adapted for low voltage applications according to an embodiment of the present invention;
fig. 2 is a block diagram of a reference sampling phase-locked loop adapted to low-voltage applications according to an embodiment of the present invention;
fig. 3 is a circuit diagram of a reference sampling phase detector according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an operating principle of a reference sampling phase detector according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a high level boost inverter according to an embodiment of the present invention;
FIG. 6 is a waveform diagram of the input and output of a high-level boost inverter according to an embodiment of the present invention;
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, a reference sampling pll suitable for low voltage applications according to the present invention is described in detail below with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
Example one
Referring to fig. 1 and fig. 2 in combination, fig. 1 is a block diagram of a reference sampling phase-locked loop adapted to low-voltage applications according to an embodiment of the present invention; fig. 2 is a block diagram of a reference sampling phase-locked loop adapted to low-voltage applications according to an embodiment of the present invention. As shown in the figure, the reference sampling phase-locked loop adapted to low voltage application of this embodiment includes: the circuit comprises a reference sampling phase discriminator module, a low-pass filter module, a Voltage Controlled Oscillator (VCO), a frequency divider module and a clock signal generation module. The reference sampling phase discriminator module comprises a reference signal input end, an output end and a low-pass filter module, wherein a differential reference signal is input into a reference signal input end of the reference sampling phase discriminator module, and the output end is connected with the input end of the low-pass filter module; the output end of the low-pass filter module is connected with the input end of the voltage-controlled oscillator, and an output signal FOUT of the voltage-controlled oscillator is used as a clock signal output by the phase-locked loop; the input end of the frequency divider module is connected with the output end of the voltage-controlled oscillator, and the output end of the frequency divider module is connected with the input end of the clock signal generation module; the output end of the clock signal generation module is connected with the feedback signal input end of the reference sampling phase discriminator module.
Specifically, the reference sampling phase discriminator module performs sampling, holding and tracking on an input differential reference signal to obtain a differential sampling output signal; the low-pass filter module performs low-pass filtering processing on the differential sampling output signal to obtain a differential voltage signal with reduced ripples; the differential voltage signal is used as the control voltage of the voltage-controlled oscillator to control the output frequency of the voltage-controlled oscillator; the frequency divider module divides the frequency of an output signal FOUT of the voltage-controlled oscillator to obtain a frequency division output signal; the clock signal generation module generates a feedback clock signal according to the frequency division output signal, and the reference sampling phase discriminator module samples the differential reference signal according to the feedback clock signal.
In this embodiment, the reference sampling phase detector module includes two Reference Sampling Phase Detectors (RSPDs), the reference signal input ends of the two reference sampling phase detectors correspondingly input the first differential reference signal FREFP and the second differential reference signal FREFN, and the output ends correspondingly output the first differential sampling output signal VSP and the second differential sampling output signal VSN.
The low-pass filter module comprises two low-pass filters (LPFs), the two low-pass filters are correspondingly connected with the two reference sampling phase detectors, and are used for respectively performing low-pass filtering processing on the first differential sampling output signal VSP and the second differential sampling output signal VSN to correspondingly obtain a first differential voltage signal VCP and a second differential voltage signal VCN.
Optionally, the two low-pass filters of the present embodiment may be passive filters, switched capacitor filters, or active filters, which is not limited herein. Optionally, the low-pass filter is a first-order low-pass filter, and may also be a low-pass filter of another order, and the specific order is not limited herein.
In this embodiment, a low-pass filter is added to the output end of the reference sampling phase detector, and a high-frequency pole is introduced, so that the reference spur is improved on the premise of not affecting the phase margin. The specific principle is as follows: the low pass filter LPF is a first order filter with a transfer function of 1/(1 + s R C), and a high frequency pole wp = -1/R C is introduced, wherein s is a complex frequency, R is a filter resistor, and C is a filter capacitor, so that the function of low pass filtering is realized. Then, at the high frequency pole wp frequency, the slope of the magnitude curve is additionally changed by-20 dB/dec, so that the suppression capability of the high frequency noise can be enhanced. Assuming a loop comprising one zero wz and two poles wp1, wp2, the phase margin PM =180 ° + arctan (wc/wz) -arctan (wc/wp 1) -arctan (wc/wp 2). It can be seen from the phase margin PM formula that when the high-frequency pole wp is far greater than the loop bandwidth wc of the pll, the high-frequency pole wp does not affect the phase margin of the pll.
Furthermore, the frequency divider module comprises a first frequency divider and a second frequency divider which are connected in sequence, wherein the input end of the first frequency divider is connected with the output end of the voltage-controlled oscillator, and the output end of the second frequency divider is connected with the input end of the clock signal generation module.
Optionally, the first frequency divider is an Injection Locked Frequency Divider (ILFD), a current mode logic frequency divider (CML), a true single phase clock trigger divider (ETSPC), or a Miller frequency divider (Miller).
In this embodiment, the first frequency divider is a current-mode logic four-way frequency divider (CML _ DIV 4), and the second frequency divider is a multi-mode programmable frequency divider (MMDIV).
Specifically, an output signal FOUT of the voltage-controlled oscillator is subjected to four-frequency division through a current mode logic four-frequency divider (CML _ DIV 4) to obtain a four-frequency division output signal F1, the current mode logic four-frequency divider is used for reducing the frequency of the output signal FOUT to the working frequency of a multi-mode programmable frequency divider (MMDIV), and the four-frequency division output signal F1 is subjected to frequency division through the multi-mode programmable frequency divider to obtain a frequency division output signal FDIV serving as a feedback signal of the phase-locked loop.
In this embodiment, the current mode logic quad divider is used to reduce the operating frequency required by the multi-mode programmable frequency divider, so as to solve the problem of reduced operating speed of the frequency divider due to low-voltage operation, thereby improving the operating frequency that can be realized by the phase-locked loop.
Further, the Clock signal generating module includes a two-phase non-overlapping Clock generator (Nonoverlap Clock Generation) and two high-level boost inverters (HBINV), wherein an input end of the two-phase non-overlapping Clock generator is connected to an output end of the frequency divider module, and an output end of the two-phase non-overlapping Clock generator is correspondingly connected to the two high-level boost inverters.
Specifically, the two-phase non-overlapping clock generator performs time sequence processing on the frequency-divided output signal to obtain a first two-phase non-overlapping narrow pulse signal V1 and a second two-phase non-overlapping narrow pulse signal V2; the first two-phase non-overlapped narrow pulse signal V1 is subjected to boosting processing by a corresponding high-level boosting inverter to obtain a first feedback clock signal CK1; the second two-phase non-overlapped narrow pulse signal V2 is subjected to boosting processing by a corresponding high-level boosting inverter to obtain a second feedback clock signal CK2; the first feedback clock signal CK1 and the second feedback clock signal CK2 are respectively input to feedback signal input ends of the two reference sampling phase detectors.
In this embodiment, the first two-phase non-overlapping narrow pulse signal V1 and the second two-phase non-overlapping narrow pulse signal V2 operate at a frequency division frequency, and the first feedback clock signal CK1 and the second feedback clock signal CK2 are two-phase non-overlapping narrow pulse signals that obtain a high swing at a low voltage.
The working principle of the reference sampling phase-locked loop adapted to low-voltage application of the embodiment is as follows: firstly, feedback clock signals CK1 and CK2 boosted by a high-level boosting inverter are sampled, kept and tracked by a reference sampling phase discriminator for input differential reference signals FREFP and FREFN, and differential sampling output signals VSP and VSN are obtained. The low-pass filter performs low-pass filtering on the differential sampling output signals VSP and VSN to obtain differential voltage signals VCP and VCN with reduced ripples. The differential output voltage signals VCP and VCN of the low-pass filter are used as the control voltage of the voltage-controlled oscillator to control the output frequency of the voltage-controlled oscillator, and an output signal FOUT is obtained. The output signal FOUT of the voltage-controlled oscillator is subjected to four-frequency division through the current mode logic four-frequency divider to obtain a four-frequency division output signal F1. The frequency division output signal F1 is subjected to frequency division by the multi-mode programmable frequency divider to obtain a frequency division output signal FDIV serving as a feedback signal of the phase-locked loop. The frequency-divided output signal FDIV is subjected to timing processing by a two-phase non-overlapping clock generator to generate two-phase non-overlapping narrow pulse signals V1 and V2 working at a frequency-divided frequency. The two-phase non-overlapping narrow pulse signals V1 and V2 pass through the boosting function of the high-level boost inverter, and obtain the two-phase non-overlapping narrow pulse signals CK1 and CK2 (i.e., feedback clock signals) with high swing at low voltage. The phase-locked loop circularly works according to the processes through negative feedback until the phase of the output signal FOUT of the voltage-controlled oscillator is equal to the phase of the input differential reference signals FREFP and FREFN, and the phase-locked function of the phase-locked loop is achieved.
Further, referring to fig. 3 and fig. 5 in combination, a circuit of the reference sampling phase detector and the high-level boost inverter of the present embodiment is specifically described.
As shown in fig. 3, the reference sampling phase detector of this embodiment includes a first sampling switch S 1 A second sampling switch S 2 A first sampling capacitor Cs and a second sampling capacitor C H . Wherein the first sampling switch S 1 And a second sampling switch S 2 In series, a first sampling switch S 1 As a reference signal input terminal of a reference sampling phase detector, a second sampling switch S 2 The second end of the reference sampling phase discriminator is used as the output end of the reference sampling phase discriminator; the first sampling capacitor Cs is connected with the first sampling switch S 1 Between the second terminal and the ground terminal, and a second sampling capacitor C H Connected to a second sampling switch S 2 Between the second terminal of (a) and ground; first sampling switch S 1 The second sampling switch S is turned on or off according to the first feedback clock signal CK1 2 And the switching on or the switching off is realized according to the second feedback clock signal CK 2.
The working principle of the reference sampling phase discriminator of the embodiment is as follows:
the first feedback clock signal CK1 and the second feedback clock signal CK2 working at the output frequency of the multi-mode programmable frequency divider are used as sampling signals, FREF is an input reference signal (i.e. a first differential reference signal FREFP or a second differential reference signal FREFN), and the first sampling switch S 1 And a second sampling switch S 2 A sampling switch, a first sampling capacitor Cs and a second sampling capacitor C which are respectively used for master-slave two-stage sampling H The sampling capacitors are respectively a sampling capacitor for master-slave two-stage sampling, and the sampling output signal VS and the sampling output signal VH are respectively sampling output signals for master-slave two-stage sampling, (in this embodiment, the sampling output signal VH is the first differential sampling output signal VSP or the second differential sampling output signal VSN). The phase difference between the feedback clock signals CK1 and CK2 and the reference signal FREF represents the phase difference between the feedback signal and the reference signal of the reference sampling phase-locked loop, and the phase difference is converted into a voltage signal through the track-hold sampler, wherein the reference sampling means that the sampling frequency is the reference frequency.
Referring to the schematic diagram of the working principle of the reference sampling phase discriminator shown in fig. 4, when the zero crossing point of the rising edge of the first feedback clock signal CK1 is aligned with the rising edge of the reference signal FREF, the phase difference at this time is 0, and the second feedback clock signal CK2 further samples the sampling output signal VS of the main sampler to obtain the sampling output signal VH. At this time, the voltage value of the sampling output signal VH is equal to the control voltage VDC required after the voltage-controlled oscillator locks.
When the first feedback clock signal CK1 and the second feedback clock signal CK2 lag behind the reference signal FREF, the phase difference is not 0, and the voltage value of the obtained sampling output signal VH is smaller than the control voltage VDC required after the voltage-controlled oscillator is locked.
When the first feedback clock signal CK1 and the second feedback clock signal CK2 lead the reference signal FREF, the phase difference is not 0, and the voltage value of the obtained sampling output signal VH is greater than the control voltage VDC required after the voltage-controlled oscillator is locked.
As shown in the circuit diagram of the high-level boost inverter shown in fig. 5, the high-level boost inverter of this embodiment includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a first capacitor C HB . The source electrode of the first MOS transistor M1 and the source electrode of the third MOS transistor M3 are both connected with a power supply end VDD; the grid electrode of the first MOS tube M1 is respectively connected with the grid electrode of the second MOS tube M2, the grid electrode of the fourth MOS tube M4 and the grid electrode of the fifth MOS tube M5, and the drain electrode is respectively connected with the drain electrode of the second MOS tube M2 and the first capacitor C HB A first electrode plate of (a); the source electrode of the second MOS transistor M2 and the source electrode of the fifth MOS transistor M5 are both connected with a grounding terminal VSS; the drain electrodes of the third MOS transistors M3 are respectively connected with a first capacitor C HB The grid electrode of the second polar plate and the source electrode of the fourth MOS tube M4 are respectively connected with the drain electrode of the fourth MOS tube M4 and the drain electrode of the fifth MOS tube M5; the grid electrode of the first MOS tube M1 is used as the input end of the high-level boost phase inverter, and the grid electrode of the third MOS tube M3 is used as the output end of the high-level boost phase inverter.
The working principle of the high-level boost inverter of the present embodiment is as follows:
having a first capacitor C HB Increased and increased parameter h, where 0<h<1. The high-level boost inverter boosts the high level of the feedback clock signal under the condition of lower power supply voltage, thereby remarkably reducing reference sampling identificationSampling switch S in phase device 1 And S 2 On-resistance R of ON So that the time constant of the sampling switch and the sampling capacitor is τ = R ON *C S Much less than the reference clock period TREF, thereby achieving the normal sampling function. The same sampling switch size realizes smaller R ON The sampling capacitor allows the sampling noise brought by the sampling capacitor to be reduced by using a larger capacitor, and the in-band noise performance which is more excellent under low voltage is realized.
As shown IN the input/output waveform diagram of the high-level boost inverter IN fig. 6, when the input IN of the high-level boost inverter is the power voltage VDD, the first MOS transistor M1 and the fourth MOS transistor M4 are turned off, the second MOS transistor M2 and the fifth MOS transistor M5 are turned on, the node voltage VA and the output OUT are discharged to 0, and the third MOS transistor M3 is turned on, and the node voltage VB is precharged to the power voltage VDD. When the input IN of the high-level boost inverter is turned over from the power supply voltage VDD to the low level 0, the first MOS transistor M1 and the fourth MOS transistor M4 are switched on, the second MOS transistor M2 and the fifth MOS transistor M5 are switched off, the node voltage VA is charged to the power supply voltage VDD, and the node voltage VB passes through the first capacitor C HB The voltage bootstrap effect of (3) reaches (1+h) × VDD high level voltage, and the output OUT is charged to (1+h) × VDD high level voltage, thereby realizing the high level boost function of the high level boost inverter.
In this embodiment, the on-resistance of the sampling switch is reduced by using a high-level boost inverter, so as to realize the normal sample-and-hold function of the sampler under low voltage. The specific principle is as follows:
on-resistance R of sampling switch ON The sampling switch comprises a sampling switch and a sampling switch, wherein the sampling switch comprises a transistor, a capacitor, a voltage source and a voltage drain, the sampling switch comprises a sampling switch, a sampling switch and a voltage source, the sampling switch is used for sampling the voltage source and the voltage drain, the voltage source and the voltage drain are connected with the sampling switch, the sampling switch is used for sampling the voltage source and the voltage drain, and the voltage source and the voltage drain are connected with the sampling switch. The high-level boost inverter increases VGS in the formula by boosting the sampling voltage, thereby reducing the on-resistance R ON 。
When the sampling switch is turned on, the time required for the output voltage to rise from zero to the maximum input level is a speed measurement standard, and a time constant tau =canbe usedR ON * CS is described as the size of the sampling capacitor. If the sampling speed is not fast enough, i.e. the time constant τ is not much smaller than the sampling time, the input signal cannot be completely sampled within the sampling time, resulting in distortion of the sampled output. According to the formula of the time constant tau, the on-resistance R is reduced when the sampling capacitor CS is not changed ON The sampling speed can be increased, and the normal sampling function is realized. In a reference sampling phase-locked loop, the sampling time is typically the reference period or high level pulse width of the sampled signal.
On-resistance R of sampling switch ON Resistance thermal noise K T/CS is introduced, where K is the boltzmann constant, T is the temperature, and CS is the size of the sampling capacitance. To reduce noise, the sampling capacitance must be large enough, but will result in a time constant τ = R ON * The increase in CS decreases the sampling speed. To reduce the resistance R ON The noise can be reduced by increasing the sampling capacitance without increasing the time constant tau.
In the specific embodiment, a reference sampling phase-locked loop with the working frequency of 3.8GHz-4.7GHz, the working voltage of 1V-1.8V, the clock jitter of 109fs and the reference stray of-82 dBc is manufactured by using a 0.18-micron CMOS process, so that the superior performance of low voltage, low stray and low jitter is realized.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of additional like elements in an article or apparatus that comprises the element. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (8)

1. A reference sampling phase-locked loop adapted for low voltage applications, comprising: a reference sampling phase discriminator module, a low pass filter module, a voltage controlled oscillator, a frequency divider module, and a clock signal generation module, wherein,
a differential reference signal is input at the reference signal input end of the reference sampling phase discriminator module, and the output end of the reference sampling phase discriminator module is connected with the input end of the low-pass filter module; the output end of the low-pass filter module is connected with the input end of the voltage-controlled oscillator, and the output signal of the voltage-controlled oscillator is used as the clock signal output by the phase-locked loop; the input end of the frequency divider module is connected with the output end of the voltage-controlled oscillator, and the output end of the frequency divider module is connected with the input end of the clock signal generation module; the output end of the clock signal generation module is connected with the feedback signal input end of the reference sampling phase discriminator module;
the reference sampling phase discriminator module carries out sampling, holding and tracking on the input differential reference signal to obtain a differential sampling output signal; the low-pass filter module performs low-pass filtering processing on the differential sampling output signal to obtain a differential voltage signal with reduced ripple waves; the differential voltage signal is used as a control voltage of the voltage-controlled oscillator to control the output frequency of the voltage-controlled oscillator; the frequency divider module divides the frequency of the output signal of the voltage-controlled oscillator to obtain a frequency-divided output signal; the clock signal generation module generates a feedback clock signal according to the frequency division output signal, and the reference sampling phase discriminator module samples the differential reference signal according to the feedback clock signal.
2. The phase locked loop of claim 1, wherein the reference sampling phase detector module comprises two reference sampling phase detectors, and the reference signal input ends of the two reference sampling phase detectors are respectively input with a first differential reference signal (FREFP) and a second differential reference signal (FREFN), and the output ends of the two reference sampling phase detectors are respectively output with a first differential sampling output signal (VSP) and a second differential sampling output signal (VSN).
3. The phase locked loop of claim 2, wherein the low pass filter module comprises two low pass filters, and the two low pass filters are connected to the two phase detectors for low pass filtering the first differential sampled output signal (VSP) and the second differential sampled output signal (VSN) to obtain a first differential voltage signal (VCP) and a second differential voltage signal (VCN), respectively.
4. The reference sampling phase-locked loop adapted for low voltage applications of claim 3, wherein said low pass filter is a passive filter, a switched capacitor filter or an active filter.
5. The reference sampling phase-locked loop adapted to low voltage application of claim 1, wherein the frequency divider module comprises a first frequency divider and a second frequency divider connected in sequence, an input terminal of the first frequency divider is connected to an output terminal of the voltage-controlled oscillator, and an output terminal of the second frequency divider is connected to an input terminal of the clock signal generation module;
wherein the first frequency divider is an injection locking frequency divider, a current mode logic frequency divider, a true single-phase clock trigger frequency divider or a Miller frequency divider; the second frequency divider is a multi-mode programmable frequency divider.
6. The reference sampling phase-locked loop for low voltage applications of claim 2, wherein the clock signal generation block comprises a two-phase non-overlapping clock generator and two high-level boost inverters, wherein,
the input end of the two-phase non-overlapping clock generator is connected with the output end of the frequency divider module, and the output end of the two-phase non-overlapping clock generator is correspondingly connected with the two high-level boost inverters;
the two-phase non-overlapping clock generator carries out time sequence processing on the frequency division output signal to obtain a first two-phase non-overlapping narrow pulse signal (V1) and a second two-phase non-overlapping narrow pulse signal (V2);
the first two-phase non-overlapped narrow pulse signal (V1) is subjected to boosting processing by a corresponding high-level boosting inverter to obtain a first feedback clock signal (CK 1);
the second two-phase non-overlapped narrow pulse signal (V2) is subjected to boosting processing by a corresponding high-level boosting inverter to obtain a second feedback clock signal (CK 2);
the first feedback clock signal (CK 1) and the second feedback clock signal (CK 2) are respectively input to feedback signal input ends of the two reference sampling phase detectors.
7. The reference sampling phase-locked loop adapted to low voltage application according to claim 6, wherein the high level boost phase inverter comprises a first MOS transistor (M1), a second MOS transistor (M2), a third MOS transistor (M3), a fourth MOS transistor (M4), a fifth MOS transistor (M5) and a first capacitor (C) HB ) Wherein, in the step (A),
the source electrode of the first MOS transistor (M1) and the source electrode of the third MOS transistor (M3) are both connected with a power supply end (VDD);
the grid electrode of the first MOS tube (M1) is respectively connected with the grid electrode of the second MOS tube (M2), the grid electrode of the fourth MOS tube (M4) and the grid electrode of the fifth MOS tube (M5), and the drain electrode is respectively connected with the drain electrode of the second MOS tube (M2) and the first capacitor (C) HB ) A first electrode plate of (a);
the source electrode of the second MOS transistor (M2) and the source electrode of the fifth MOS transistor (M5) are both connected with a ground terminal (VSS);
the drain electrodes of the third MOS tubes (M3) are respectively connected with the first capacitors (C) HB ) And a source of said fourth MOS transistor (M4),the grid electrode is respectively connected with the drain electrode of the fourth MOS tube (M4) and the drain electrode of the fifth MOS tube (M5);
the grid electrode of the first MOS tube (M1) is used as the input end of the high-level boost phase inverter, and the grid electrode of the third MOS tube (M3) is used as the output end of the high-level boost phase inverter.
8. The reference sampling phase-locked loop adapted for low voltage applications of claim 6, wherein the reference sampling phase detector comprises a first sampling switch (S) 1 ) A second sampling switch (S) 2 ) A first sampling capacitor (Cs) and a second sampling capacitor (C) H ) Wherein, in the step (A),
the first sampling switch (S) 1 ) And said second sampling switch (S) 2 ) In series, the first sampling switch (S) 1 ) As a reference signal input of said reference sampling phase detector, said second sampling switch (S) 2 ) The second end of the reference sampling phase discriminator is used as the output end of the reference sampling phase discriminator;
the first sampling capacitor (Cs) is connected to the first sampling switch (S) 1 ) Between the second terminal and ground, the second sampling capacitor (C) H ) Is connected to the second sampling switch (S) 2 ) Between the second terminal of (a) and ground;
the first sampling switch (S) 1 ) -said second sampling switch (S) is switched on or off in dependence on said first feedback clock signal (CK 1) 2 ) -switching on or off in dependence of the second feedback clock signal (CK 2).
CN202211029887.8A 2022-08-25 2022-08-25 Reference sampling phase-locked loop suitable for low-voltage application Pending CN115549676A (en)

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