CN115549587B - Low-temperature voltage-controlled oscillator circuit with low flicker noise, chip and quantum measurement and control system - Google Patents
Low-temperature voltage-controlled oscillator circuit with low flicker noise, chip and quantum measurement and control system Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
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- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
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Abstract
The embodiment of the invention provides a low-temperature voltage-controlled oscillator circuit with low flicker noise, a chip and a quantum measurement and control system, wherein in the low-temperature voltage-controlled oscillator circuit with low flicker noise, a double-layer inductive coupling structure and a transformer structure are adopted, so that a double-second harmonic resonance point and a triple harmonic resonance point can be constructed simultaneously, and a harmonic tuning technology is maintained to be effective at low temperature, so that harmonic waves can be aligned accurately, and further low-temperature flicker noise is restrained successfully; meanwhile, the first differential-mode capacitance regulating circuit and the second differential-mode capacitance regulating circuit are used for respectively realizing fine adjustment and coarse adjustment of the frequency of the oscillator, and the suppression of broadband low-temperature flicker noise is realized.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a low-temperature voltage-controlled oscillator circuit with low flicker noise, a chip and a quantum measurement and control system.
Background
The voltage-controlled oscillator (Voltage Controlled Oscillator, VCO) is an oscillating circuit with output frequency corresponding to input control voltage, and has the following technical requirements: the frequency stability is good, the control sensitivity is high, the frequency modulation range is wide, the frequency offset and the control voltage form a linear relation, the integration is easy, and the like; the stability of the output frequency of the voltage-controlled oscillator mainly depends on phase noise, and the smaller the phase noise is, the more stable the output frequency of the voltage-controlled oscillator is, and the higher the precision is; the phase noise is divided into a flicker noise region and a thermal noise region, which represent a region dominated by flicker noise and a region dominated by thermal noise, respectively.
B. Patra et al, in IEEE Journal of Solid-State Circuits, vol.53, no.1, pp.309-321, cryo-CMOS Circuits and Systems for Quantum Computing Applications, published in Jan.2018, states: in an extremely low temperature environment, the flicker noise of the CMOS process is severely deteriorated, and the low temperature flicker noise angle (Flicker Noise Corner) of the VCO is deteriorated by more than 40 times than the normal temperature, so that it is known that the low temperature flicker noise angle of the voltage-controlled oscillator commonly manufactured by the CMOS process is also deteriorated by many times than the normal temperature.
However, harmonic tuning techniques are often used in VCOs to suppress flicker noise, and the conventional harmonic tuning techniques of VCOs are further described by the schematic diagram of the LC-VCO shown in fig. 1 (a), which specifically refers to: two NMOS active transistors cross-coupledThe form of the combination forms a negative resistance oscillator, and coil inductance and capacitance above the cross-coupled pair form two or more LC resonant cavities for selecting the frequency output by the VCO circuit. As shown in fig. 1 (b), a differential mode capacitance C D And common mode capacitance C C And L form a resonant circuit, resonating at the fundamental frequency F0, and the common-mode capacitor C C And L form another common-mode resonant circuit, resonating at frequency F CM Where it is located. By adjusting the common-mode capacitance C C And differential mode capacitance C D When C is a ratio of C /C D When=1/3, let F CM =2f0, the common mode resonance frequency is just at the second harmonic of the fundamental frequency, at which time the smallest Phase Noise (PN) can be obtained, as shown in fig. 1 (c).
However, the parameter change of passive devices (capacitance and inductance) can be caused in a low-temperature environment, so that the oscillation frequency of the LC resonant cavity has larger difference at normal temperature and low temperature; the oscillation frequency shifts to a high frequency at a low temperature, so that the additional resonant cavity cannot just resonate at the harmonic frequency of the fundamental frequency, and optimal phase noise cannot be obtained, namely, a harmonic tuning technology is invalid at the low temperature, and the harmonic pair Ji Shizhun cannot successfully inhibit low-temperature flicker noise.
Therefore, there is a need to design a voltage controlled oscillator scheme with excellent phase noise performance for low temperature application scenarios.
Disclosure of Invention
In a first aspect of the present invention, a low-flicker-noise low-temperature voltage controlled oscillator circuit is provided, which uses a double-layer inductive coupling structure and a transformer structure to implement construction of a double-second harmonic resonance point, so that a harmonic tuning technology can be maintained effectively at a low temperature, and harmonics can be aligned accurately, thereby successfully suppressing low-temperature flicker noise.
In a first aspect of the present invention, there is provided a low flicker noise low temperature voltage controlled oscillator circuit comprising: the device comprises a double-layer inductive coupling structure, a transformer structure, a first oscillation frequency adjusting circuit, a second oscillation frequency adjusting circuit, a first MOS tube and a second MOS tube;
one end of an upper inductor of the double-layer inductance coupling structure is coupled to the working voltage input end, one end of a lower inductor is coupled to the working voltage input end through the first capacitor, and the other ends of the upper inductor and the lower inductor are coupled to a center tap of the transformer structure together;
one end of a primary winding of the transformer structure is coupled to the grid electrode of the first MOS tube, the other end of the primary winding is coupled to the grid electrode of the second MOS tube, one end of a secondary winding is coupled to the drain electrode of the first MOS tube, and the other end of the secondary winding is coupled to the drain electrode of the second MOS tube; furthermore, a center of the primary winding of the transformer structure is coupled to the second voltage input;
the sources of the first MOS tube and the second MOS tube are respectively coupled to the grounding end, the drain electrode of the first MOS tube is coupled to one end of the second capacitor, and the drain electrode of the second MOS tube is coupled to the other end of the second capacitor;
the first differential-mode capacitance adjusting circuit is connected with the second differential-mode capacitance adjusting circuit in parallel and is arranged between two ends of the primary winding of the transformer structure, and is used for respectively adjusting differential-mode capacitance of the primary winding connected into the transformer structure, so as to adjust oscillation frequency of the voltage-controlled oscillator circuit.
In some possible embodiments, the double-layer inductive coupling structure is formed by two metal wires arranged in a laminated manner, an upper metal wire forms the upper layer inductor, a lower metal wire forms the lower layer inductor, and the two metal wires arranged in a laminated manner are formed into two symmetrical annular structures in the same plane.
In some possible embodiments, the low flicker noise low temperature voltage controlled oscillator circuit of the present invention further comprises a decoupling capacitor; the working voltage input end is coupled to the positive plate of the decoupling capacitor, one end of the upper inductor of the double-layer inductive coupling structure is coupled to the positive plate of the decoupling capacitor, one end of the lower inductor is coupled to the positive plate of the decoupling capacitor through the first capacitor, and the negative plate of the decoupling capacitor is coupled to the ground end.
In some possible embodiments, the first differential-mode capacitance adjustment circuit comprises: a first fixed capacitance, a first variable capacitance, and a second variable capacitance; the first variable capacitor is connected in series with the second variable capacitor, then connected in parallel with the first fixed capacitor, and arranged between two ends of a primary winding of the transformer structure; the connection node of the first variable capacitor and the second variable capacitor is coupled to the capacitance adjusting voltage input end.
In some possible embodiments, the second differential-mode capacitance adjustment circuit includes: a plurality of switched capacitor units; wherein each of the switched capacitor units comprises: a pair of fixed capacitors and a MOS tube; and the source electrode of the MOS tube is coupled to one end of the primary winding of the transformer structure through a fixed capacitor, the drain electrode of the MOS tube is coupled to the other end of the primary winding of the transformer structure through another fixed capacitor, and the grid electrode of the MOS tube is coupled to the switch signal input end corresponding to the switch capacitor unit.
In some possible embodiments, the switched capacitor unit further comprises: a first inverter, a second inverter, and a pair of resistors; the input end of the first inverter is coupled to the switch signal input end corresponding to the switch capacitance unit, the output end of the first inverter is coupled to the input end of the second inverter, and the output end of the second inverter is coupled to the grid electrode of the MOS tube; one end of the resistor is coupled to the source electrode of the MOS tube, the other end of the resistor is coupled to the output end of the first inverter, one end of the resistor is coupled to the drain electrode of the MOS tube, and the other end of the resistor is coupled to the output end of the first inverter.
In some possible embodiments, the ratio of the capacitance value variation range of the second differential-mode capacitance adjusting circuit to the capacitance value of the first capacitance is between 10:1 and 20:1.
In some possible embodiments, the low flicker noise low temperature voltage controlled oscillator circuit of the present invention further comprises: a plurality of switching resistance units; wherein each of the switching resistance units includes: the MOS transistor comprises a grounding resistor and a MOS transistor, wherein sources of the first MOS transistor and the second MOS transistor are commonly coupled to one end of the grounding resistor, the other end of the grounding resistor is coupled to a drain electrode of the MOS transistor, the source electrode of the MOS transistor is coupled to the grounding terminal, and a grid electrode of the MOS transistor is coupled to a switch signal input end corresponding to the switch resistor unit.
In some possible embodiments, the low flicker noise low temperature voltage controlled oscillator circuit of the present invention further comprises: a first buffer and a second buffer; wherein the input end of the first buffer is coupled to one end of the primary winding of the transformer structure, the other end of the first buffer is coupled to the first frequency output end, and the input end of the second buffer is coupled to the other end of the primary winding of the transformer structure, and the other end of the second buffer is coupled to the second frequency output end.
In a second aspect of the present invention, there is provided a chip comprising:
a silicon substrate; and the low-flicker-noise low-temperature voltage-controlled oscillator circuit of the first aspect of the invention formed on the silicon substrate, wherein the low-flicker-noise low-temperature voltage-controlled oscillator circuit is manufactured by adopting a COMS process.
In a third aspect of the invention, a quantum measurement and control system is provided, which comprises the chip according to the second aspect of the invention.
In the low-temperature voltage-controlled oscillator circuit with low flicker noise, a double-layer inductive coupling structure and a transformer structure are adopted in the circuit, so that a double-second harmonic resonance point and a triple harmonic resonance point can be simultaneously constructed, and a harmonic tuning technology is maintained effectively at low temperature, so that harmonic waves can be accurately aligned, and further low-temperature flicker noise is successfully restrained; meanwhile, the first differential-mode capacitance regulating circuit and the second differential-mode capacitance regulating circuit are used for respectively realizing fine adjustment and coarse adjustment of the frequency of the oscillator, and the suppression of broadband low-temperature flicker noise is realized.
Description of the drawings:
fig. 1 is a schematic diagram of an LC-VCO;
FIG. 2 is a block diagram of a low flicker noise low temperature voltage controlled oscillator circuit provided in an embodiment of the present invention;
FIG. 3 is a block diagram of a low flicker noise low temperature voltage controlled oscillator circuit provided in an embodiment of the present invention;
fig. 4 is a schematic connection diagram of a decoupling capacitor and a dual-layer inductive coupling structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a dual-layer inductive coupling structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram showing the magnetic field distribution of a dual-layer inductive coupling structure according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating the harmonic impedance simulation of the low flicker noise low temperature voltage controlled oscillator circuit of FIG. 3;
FIG. 8 is a schematic diagram of a simulation of flicker noise angle within the full frequency band of the low flicker noise low temperature voltage controlled oscillator circuit of FIG. 3;
FIG. 9 is a schematic diagram of a simulation of phase noise in a flicker noise dominant region of the low flicker noise low temperature voltage controlled oscillator circuit of FIG. 3;
fig. 10 is a schematic diagram of a structure of a reading system in quantum measurement and control reading according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings and specific examples. It should not be construed that the scope of the above subject matter of the present invention is limited to the following embodiments, and all techniques realized based on the present invention are within the scope of the present invention.
In one embodiment of the present invention, a low flicker noise low temperature voltage controlled oscillator circuit 10 is provided, as shown in fig. 2, comprising: the device comprises a double-layer inductive coupling structure 101, a transformer structure 102, a first oscillation frequency adjusting circuit 103, a second oscillation frequency adjusting circuit 104, a first MOS tube M1 and a second MOS tube M2;
one end of an upper layer inductor of the double-layer inductor coupling structure 101 is coupled to the working voltage input end VDD, one end of a lower layer inductor is coupled to the working voltage input end VDD through the first capacitor Chead, and the other ends of the upper layer inductor and the lower layer inductor are commonly coupled to a center tap of the transformer structure 102;
one end of the primary winding of the transformer structure is coupled to the gate of the first MOS tube M1, the other end thereof is coupled to the gate of the second MOS tube M2, one end of the secondary winding is coupled to the drain of the first MOS tube M1, and the other end thereof is coupled to the first MOS tube M2A drain electrode of the two MOS transistors M2; also, the center of the primary winding of the transformer structure 102 is coupled to the second voltage input terminal V GB ；
The sources of the first MOS tube M1 and the second MOS tube M2 are respectively coupled to the grounding end, the drain electrode of the first MOS tube M1 is coupled to one end of the second capacitor Cdd, and the drain electrode of the second MOS tube M2 is coupled to the other end of the second capacitor Cdd;
the first differential-mode capacitance adjusting circuit 103 is connected in parallel with the second differential-mode capacitance adjusting circuit 104, and is disposed between two ends of the primary winding of the transformer structure 102, so as to respectively adjust differential-mode capacitance of the primary winding connected to the transformer structure 102, thereby adjusting the oscillation frequency of the voltage-controlled oscillator circuit.
In the present embodiment, the first differential-mode capacitance adjusting circuit 103 includes: a first fixed capacitor Cgg, two variable capacitors Cv; the two variable capacitors Cv are connected in series and then connected in parallel with the first fixed capacitor Cgg, and are arranged between two ends of the primary winding of the transformer structure 102; wherein the connection nodes of the two variable capacitors Cv are coupled to the capacitance-regulating voltage input.
In this embodiment, the second differential-mode capacitance adjusting circuit 104 includes: a plurality of switched capacitor units; wherein each of the switched capacitor units comprises: a pair of fixed capacitors CB and a MOS tube; furthermore, the source of the MOS transistor is coupled to one end of the primary winding of the transformer structure 102 through a fixed capacitor CB, the drain of the MOS transistor is coupled to the other end of the primary winding of the transformer structure 102 through another fixed capacitor CB, and the gate of the MOS transistor is coupled to the switch signal input terminal SW corresponding to the switch capacitor unit.
Specifically, the switched capacitor unit further includes: a first inverter, a second inverter, and a pair of resistors; the input end of the first inverter is coupled to the switch signal input end corresponding to the switch capacitance unit, the output end of the first inverter is coupled to the input end of the second inverter, and the output end of the second inverter is coupled to the grid electrode of the MOS tube; one end of the resistor is coupled to the source electrode of the MOS tube, the other end of the resistor is coupled to the output end of the first inverter, one end of the resistor is coupled to the drain electrode of the MOS tube, and the other end of the resistor is coupled to the output end of the first inverter. Through the mode, the MOS switch can be ensured to be normally turned on and turned off.
In order to widen the operating bandwidth of the VCO, the ratio of the capacitance value variation range of the second differential-mode capacitance adjustment circuit 104 to the capacitance value of the first capacitance is between 10:1 and 20:1; thus, the overall capacitance variation range of the second differential-mode capacitance adjusting circuit 104 can be increased by reducing the specific gravity of Chead, so that the operating bandwidth of the VCO can be increased.
In the low-temperature voltage-controlled oscillator circuit with low flicker noise, a double-layer inductive coupling structure and a transformer structure are adopted, so that a double-second harmonic resonance point and a triple harmonic resonance point can be simultaneously constructed, and a harmonic tuning technology is maintained to be effective at low temperature, so that harmonic waves can be accurately aligned, and further low-temperature flicker noise can be successfully restrained; meanwhile, the first differential-mode capacitance regulating circuit and the second differential-mode capacitance regulating circuit are used for respectively realizing fine adjustment and coarse adjustment of the frequency of the oscillator, and the suppression of broadband low-temperature flicker noise is realized.
In this embodiment, since the voltage-controlled oscillator core circuit and the later stage circuit (frequency divider) are directly connected, in order to isolate the influence of the later stage circuit on the voltage-controlled oscillator core circuit, a first buffer and a second buffer are arranged at the gate outputs of the first MOS transistor M1 and the second MOS transistor M2; specifically, the input end of the first buffer is coupled to one end of the primary winding of the transformer structure, and the other end thereof is coupled to the first frequency output end V GN The input end of the second buffer is coupled to the other end of the primary winding of the transformer structure, and the other end thereof is coupled to the second frequency output end V GP 。
In one embodiment of the present invention, a resistor array 105 is added on the basis of the embodiment shown in fig. 2, and as shown in fig. 3, the resistor array 105 includes: a plurality of switching resistance units; wherein each of the switching resistance units includes: the MOS transistor comprises a grounding resistor and a MOS transistor, wherein sources of the first MOS transistor and the second MOS transistor are commonly coupled to one end of the grounding resistor, the other end of the grounding resistor is coupled to a drain electrode of the MOS transistor, the source electrode of the MOS transistor is coupled to the grounding terminal, and a grid electrode of the MOS transistor is coupled to a switch signal input end SW corresponding to the switch resistor unit. Through the mode, the whole resistance value of the resistor array can be changed in a digital control mode, so that the whole current of the oscillator can be controlled, and the power consumption can be regulated at a low temperature to obtain better FOM.
In one embodiment, as shown in fig. 4, the low flicker noise low temperature voltage controlled oscillator circuit of the present invention further comprises a decoupling capacitor 106; the working voltage input end VDD is coupled to the positive plate of the decoupling capacitor 106, one end of the upper inductor of the double-layer inductive coupling structure is coupled to the positive plate of the decoupling capacitor 106, one end of the lower inductor is coupled to the positive plate of the decoupling capacitor 106 through the first capacitor, and the negative plate of the decoupling capacitor 106 is coupled to the ground.
In one embodiment of the present invention, as shown in fig. 5, in this embodiment, the dual-layer inductive coupling structure 101 is formed by two metal wires that are stacked, the upper metal wire 101a forms the upper layer inductor, the lower metal wire 101b forms the lower layer inductor, and the two metal wires that are stacked are formed into two ring structures that are symmetrical in the same plane. When the low-temperature voltage-controlled oscillator circuit with low flicker noise works, the magnetic field distribution of the double-layer inductive coupling structure 101 is shown in fig. 6, so that the internal integral magnetic field is balanced, the influence of magnetic force is avoided, and the common-mode voltage amplitude at the drain electrodes of the first MOS tube M1 and the second MOS tube M2 is equal.
In the embodiments shown in fig. 2 or fig. 3 provided by the present invention, the specific structure of the transformer structure 102 is consistent with the structure adopted by a design transformer to implement VCO harmonic tuning technology disclosed in a.beckers et al, 2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, pp.62-65, cryogenic characterization of 28nm bulk CMOS technology for quantum computing, and not described in detail herein.
Referring to fig. 3 and 4, gates of the first MOS transistor M1 and the second MOS transistor M2 connected to the primary winding Lp of the transformer structure 102, and drains of the first MOS transistor M1 and the second MOS transistor M2 connected to the secondary winding Ls; when the secondary winding Ls is excited in a differential mode, the induced current in the primary winding Lp is strengthened in the same direction, and the strong coupling coefficient is realized; and when the secondary winding Ls is excited in a common mode, the induced current in the primary winding Lp is reversely cancelled, and has a weak coupling coefficient. Therefore, the primary winding Lp does not participate in common mode resonance.
When the MOS transistor works, differential mode resonance of fundamental frequency (f 0) is generated on the grid electrodes of the first MOS transistor M1 and the second MOS transistor M2 together by the secondary winding Ls, the primary winding Lp, the differential mode capacitor CV, the capacitor arrays CB and Cgg; the resonant cavity formed by the double-layer inductive coupling structure 101, the secondary winding Ls and the first capacitor Chead generate common mode resonance and are output at the drains of the first MOS tube M1 and the second MOS tube M2; meanwhile, as the upper layer and the lower layer of the resonant cavity formed by the double-layer inductive coupling structure 101 are mutually coupled, the common mode resonance at two frequencies can be realized at the same time, and the coupling coefficient of the structure is higher, so that the two resonant frequencies are close enough at high frequency, and broadband Common Mode (CM) resonance with double resonant peaks is formed near the second harmonic (2 f 0); meanwhile, the secondary winding Ls, the primary winding Lp and the differential mode capacitor Cdd realize differential mode resonance at the third harmonic (3 f 0) at the drain electrodes of the first MOS tube M1 and the second MOS tube M2.
Finally, a harmonic impedance simulation diagram as shown in fig. 7, i.e., a Differential Mode (DM) resonance is formed near the fundamental frequency (f 0), a wideband Common Mode (CM) resonance with a double resonance peak is formed near the second harmonic (2 f 0), and a Differential Mode (DM) resonance is formed near the third harmonic (3 f 0).
Further, as shown in fig. 8, by testing the flicker noise angle in the full frequency band, the red broken line is 293K normal temperature test result, and the blue broken line is 4K low temperature test result, respectively, are obtained. Wherein, 293K flicker noise angle: 150-600 kHz;4K flicker noise angle: 450-800 kHz. The 4K low temperature is only 1.3-3 times worse than the 293K normal temperature, and the flicker noise angle is suppressed in the whole frequency band and kept within 800kHz.
As shown in fig. 9, by testing the phase noise (flicker noise dominant region) at the frequency offset of 100kHz, according to the simulation result, it is known that if the flicker noise is not suppressed in the region where the flicker noise is dominant, the flicker noise will be degraded 10 times at the low temperature of 4K, but the broadband double resonance peak of the design is still effective at the low temperature, and the flicker noise is suppressed in the whole frequency band.
In one embodiment of the present invention, there is also provided a chip including: a silicon substrate; and the low-flicker-noise low-temperature voltage-controlled oscillator circuit shown in fig. 2 or 3 is formed on the silicon substrate, wherein the low-flicker-noise low-temperature voltage-controlled oscillator circuit is manufactured by adopting a COMS process.
The invention also provides a quantum measurement and control system, which comprises the chip provided by the embodiment of the invention. Specifically, the quantum computation is divided into a quantum Chip (Qubit Chip) and a quantum measurement and control system (Controller), wherein the Qubit Chip needs to work in an extremely low temperature region of 10mK (0.01 kelvin above absolute zero) in a low temperature refrigeration box; the Controller is used for reading and controlling the quantum chip; furthermore, the quantum measurement and control system comprises a reading system and a control system, and as shown in fig. 10, the reading system (Readout Chip) is composed of a frequency synthesis system, namely a phase-locked loop (Phase Locked Loop, PLL) and an IQ receiver. The PLL generates a radio frequency signal that is attenuated by an Attenuator (Attenuator) and passed through a circulator into the qubit. The gate reflected signal of the quantum bit Q1 enters a first stage of an IQ receiver through a circulator, is amplified by a Low noise amplifier (Low Noise Amplifier, LNA), is down-converted into a quadrature component (I/Q), and is read after being filtered (Low Pass Filter, LPF) and amplified by a later stage.
Wherein the PLL functions in the read system to generate a stable radio frequency signal. The PLL works as follows: firstly, a voltage-controlled oscillator (Voltage Controlled Oscillator, VCO), which is the control object of a phase-locked loop, freely oscillates at a certain frequency through an LC resonant cavity to generate a radio frequency signal, and the voltage signal output by the LPF controls the magnitude of the capacitance value in the VCO, so that the VCO can output the radio frequency signal in a certain frequency range; the VCO has two paths of outputs, one path of output provides a frequency signal for a large system, and the other path participates in feedback of a PLL loop, as shown in the figure, after the VCO output is divided by a frequency division chain, namely two-stage/2 frequency division, and a program-controlled frequency divider, a high-frequency signal component is divided into a lower-frequency signal, and then the lower-frequency signal is fed back to a Phase Detector (PD); the phase discriminator has two inputs, one input is a feedback signal of the output of the VCO in the PLL loop through a frequency dividing chain, the other input is a Reference clock (Reference) provided by the external environment, the Reference clock is usually low in frequency, therefore, the frequency dividing chain is required to divide the high-frequency signal of the oscillator to a lower frequency by a designated frequency dividing multiple so as to be compared with the Reference clock, the phase discriminator has the function of extracting the phase difference between the feedback signal and the Reference clock and converting the error signal into a form which can be processed by a subsequent module, wherein the form comprises a voltage signal, a current signal or a digital signal; a Charge Pump (CP) and a phase detector are typically used in combination, the main function of which is to convert the phase difference into a charge and to transmit the charge to a filter (LPF) in the loop for filtering, generating a control voltage for controlling the frequency and phase of the oscillator (VCO). This forms a very versatile phase locked loop system.
At present, a quantum measurement and control system is being integrated from normal temperature (290K) to low temperature (4K) environment, so that the problems that a large number of signal cables are needed and the quantum measurement and control system can be connected to a quantum chip only when crossing a temperature zone are avoided, and a large amount of noise is introduced, the complexity of interconnection is brought, the cost is high, the reliability is unreliable and the like are solved. Therefore, the Chip provided by the embodiment of the invention is used as a voltage-controlled oscillator to be applied to a reading system (Readout Chip), can successfully inhibit low-temperature flicker noise, and is particularly suitable for an application scene of integrating a quantum measurement and control system into a low-temperature (4K) environment.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A low flicker noise low temperature voltage controlled oscillator circuit comprising: the device comprises a double-layer inductive coupling structure, a transformer structure, a first differential mode capacitance adjusting circuit, a second differential mode capacitance adjusting circuit, a first MOS tube and a second MOS tube;
one end of an upper inductor of the double-layer inductance coupling structure is coupled to the working voltage input end, one end of a lower inductor is coupled to the working voltage input end through a first capacitor, and the other ends of the upper inductor and the lower inductor are coupled to a center tap of the transformer structure together;
one end of a primary winding of the transformer structure is coupled to the grid electrode of the first MOS tube, the other end of the primary winding is coupled to the grid electrode of the second MOS tube, one end of a secondary winding is coupled to the drain electrode of the first MOS tube, and the other end of the secondary winding is coupled to the drain electrode of the second MOS tube; furthermore, a center of the primary winding of the transformer structure is coupled to the second voltage input;
the sources of the first MOS tube and the second MOS tube are respectively coupled to the grounding end, the drain electrode of the first MOS tube is coupled to one end of the second capacitor, and the drain electrode of the second MOS tube is coupled to the other end of the second capacitor;
the first differential-mode capacitance adjusting circuit is connected with the second differential-mode capacitance adjusting circuit in parallel and is arranged between two ends of the primary winding of the transformer structure, so as to respectively adjust differential-mode capacitance of the primary winding connected into the transformer structure and further adjust oscillation frequency of the voltage-controlled oscillator circuit;
the double-layer inductance coupling structure is composed of two metal wires which are arranged in a laminated mode, the upper layer metal wires form the upper layer inductance, the lower layer metal wires form the lower layer inductance, and the two metal wires which are arranged in the laminated mode are formed into two annular structures which are symmetrical in the same plane.
2. The low flicker noise low temperature voltage controlled oscillator circuit of claim 1, further comprising a decoupling capacitor; the working voltage input end is coupled to the positive plate of the decoupling capacitor, one end of the upper inductor of the double-layer inductive coupling structure is coupled to the positive plate of the decoupling capacitor, one end of the lower inductor is coupled to the positive plate of the decoupling capacitor through the first capacitor, and the negative plate of the decoupling capacitor is coupled to the ground end.
3. The low flicker noise low temperature voltage controlled oscillator circuit of claim 1, wherein said first differential mode capacitance adjustment circuit comprises: a first fixed capacitance, a first variable capacitance, and a second variable capacitance; the first variable capacitor is connected in series with the second variable capacitor, then connected in parallel with the first fixed capacitor, and arranged between two ends of a primary winding of the transformer structure; the connection node of the first variable capacitor and the second variable capacitor is coupled to the capacitance adjusting voltage input end.
4. The low flicker noise low temperature voltage controlled oscillator circuit of claim 1, wherein said second differential mode capacitance adjustment circuit comprises: a plurality of switched capacitor units; wherein each of the switched capacitor units comprises: a pair of fixed capacitors and a MOS tube; and the source electrode of the MOS tube is coupled to one end of the primary winding of the transformer structure through a fixed capacitor, the drain electrode of the MOS tube is coupled to the other end of the primary winding of the transformer structure through another fixed capacitor, and the grid electrode of the MOS tube is coupled to the switch signal input end corresponding to the switch capacitor unit.
5. The low flicker noise low temperature voltage controlled oscillator circuit of claim 4, wherein said switched capacitor unit further comprises: a first inverter, a second inverter, and a pair of resistors; the input end of the first inverter is coupled to the switch signal input end corresponding to the switch capacitance unit, the output end of the first inverter is coupled to the input end of the second inverter, and the output end of the second inverter is coupled to the grid electrode of the MOS tube; one end of the resistor is coupled to the source electrode of the MOS tube, the other end of the resistor is coupled to the output end of the first inverter, one end of the resistor is coupled to the drain electrode of the MOS tube, and the other end of the resistor is coupled to the output end of the first inverter.
6. The low flicker noise low temperature voltage controlled oscillator circuit of claim 5, wherein the ratio of the capacitance value variation range of the second differential mode capacitance adjusting circuit to the capacitance value of the first capacitor is between 10:1 and 20:1.
7. The low flicker noise low temperature voltage controlled oscillator circuit of any of claims 1-6, further comprising: a plurality of switching resistance units; wherein each of the switching resistance units includes: the MOS transistor comprises a grounding resistor and a MOS transistor, wherein sources of the first MOS transistor and the second MOS transistor are commonly coupled to one end of the grounding resistor, the other end of the grounding resistor is coupled to a drain electrode of the MOS transistor, the source electrode of the MOS transistor is coupled to the grounding terminal, and a grid electrode of the MOS transistor is coupled to a switch signal input end corresponding to the switch resistor unit.
8. The low flicker noise low temperature voltage controlled oscillator circuit of claim 7, further comprising: a first buffer and a second buffer; wherein the input end of the first buffer is coupled to one end of the primary winding of the transformer structure, the other end of the first buffer is coupled to the first frequency output end, and the input end of the second buffer is coupled to the other end of the primary winding of the transformer structure, and the other end of the second buffer is coupled to the second frequency output end.
9. A chip, comprising:
a silicon substrate; and the low-flicker-noise low-temperature voltage controlled oscillator circuit according to any one of claims 1 to 8, which is formed on the silicon substrate, wherein the low-flicker-noise low-temperature voltage controlled oscillator circuit is manufactured by adopting a COMS process.
10. A quantum measurement and control system, comprising: the chip of claim 9.
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