CN115548106A - Enhancement mode GaN device with P type grid - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 70
- 230000004888 barrier function Effects 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 238000002161 passivation Methods 0.000 claims description 36
- 229910002704 AlGaN Inorganic materials 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 26
- 230000005684 electric field Effects 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 7
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 7
- 238000010030 laminating Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- -1 fluorine ions Chemical class 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
The invention belongs to the technical field of power semiconductors, and provides an enhanced GaN device with a P-type gate, which is used for solving the problems of narrow gate voltage swing, large gate leakage, high process requirement, high specific on resistance, high cost, poor electrothermal stability and the like of the conventional device. The novel MIS grid part is formed by sequentially laminating an insulated gate dielectric layer, a P-type wide bandgap semiconductor layer and a metal grid from bottom to top, high-concentration two-dimensional electron gas below the MIS grid part is exhausted by utilizing a high work function difference, and an enhanced device is obtained under the design of a thick barrier layer; in addition, a gate dielectric layer is arranged between the P-type wide bandgap semiconductor layer and the barrier layer to prevent the P-type wide bandgap semiconductor layer from injecting holes into the barrier layer, so that extremely low gate leakage is obtained; finally, the enhanced GaN device has the advantages of large grid voltage swing, low grid leakage, small channel specific on-resistance, high threshold voltage consistency, simple process, low cost, high stability and the like.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, relates to a high-voltage semiconductor device, and particularly provides an enhanced GaN device with a P-type gate.
Background
The GaN device is used as a third-generation semiconductor device, and the inherent physical properties of the GaN device enable the GaN device to be very suitable for high-frequency, high-power and other applications; the enhancement GaN device is a key point of research because it can omit the protection circuit and improve the system reliability in power electronic application.
The traditional enhancement type transverse GaN device mainly comprises a p-GaN gate or p-AlGaN gate enhancement type HEMT device, a process-gate HEMT and an HEMT adopting fluorine ion injection; wherein the p-GaN Gate or p-AlGaN Gate enhanced HEMT device utilizes p-GaN or p-AlGaN to deplete the two-dimensional electron gas at the channel, as described in the documents "Y.Uemoto et al", "Gate Injection Transistor (GIT) -A normal-off AlGaN/GaN power transistor using modulation," IEEETrans. Electron Devices, vol.54, no.12, pp.3393-3399, dec.2007 ", and has the structure shown in FIG. 1; however, a PN diode formed by the p-GaN or the p-AlGaN and the barrier layer is conducted when the grid voltage is 3V, so that a large grid current is introduced, the driving loss is increased, the grid voltage swing is limited by the characteristics and generally does not exceed 5V, and the difficulty of the design of a driving circuit is increased; and the p-GaN gate and the metal gate electrode generally form reverse bias Schottky contact to reduce gate current, but the Schottky contact has lower reliability and stability, so that the reliability and stability of gate leakage are lower. Recycled-gate HEMTs are obtained by etching a portion of the barrier layer (residual thickness d) under the gate dielectric as described in the documents "y.zhao, et al," Effects of depth on performance of AlGaN/GaN power MIS-HEMTs on the Si substrates and threshold voltage model of diffusion depth for the using HfO2 gate insulator, "Solid-State Electronics,2020, 107649" which has the structure shown in fig. 2, which reduces the two-dimensional electron gas concentration at the channel to achieve enhancement mode but reduces the channel polarization strength to increase the specific on-resistance; in addition, the threshold voltage of the device is increased along with the reduction of the thickness of a barrier layer reserved under a channel gate dielectric, generally about 1V-2V, and when the reserved barrier layer is thinned to a few nanometers, the electron mobility in the channel is greatly reduced along with the damage of the channel, so that the specific on-resistance is multiplied; furthermore, the precision of the thickness d reserved by etching is very difficult to control, and the threshold voltage uniformity of devices on the wafer is obviously influenced. An enhancement type device can also be realized by injecting fluorine ions into the MIS-HEMT structure below the grid channel, but the electron mobility is reduced by the scattering introduced by the F ions, the resistance of the device is increased, and meanwhile, the problems of thermal stability and the like exist.
To overcome the above problems, the applicant has filed the following applications: 202210146339.7, a patent document entitled enhanced MIS-GaN device, discloses a structure with a MIS gate portion; however, the P-type wide bandgap semiconductor layer of the structure is in a floating state, which may affect the stability and reliability of the threshold voltage; in addition, the diffusion form of doping the P-type wide bandgap semiconductor layer into the barrier layer and the channel layer seriously affects the threshold voltage and the specific on-resistance of the device.
Disclosure of Invention
The invention aims to provide an enhanced GaN device with a P-type gate aiming at the problems of poor threshold voltage consistency, poor stability and reliability, channel damage, low two-dimensional electron gas concentration, high channel resistance, narrow gate voltage swing, large gate leakage, high process difficulty, complex drive design and the like of the existing enhanced GaN device; the invention has the advantages of large grid voltage swing, low grid leakage, small channel resistance, high consistency of threshold voltage, high electrothermal stability, high reliability, simple process and the like.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
1. an enhancement mode GaN device with a P-type gate, comprising: the structure comprises an insulated gate dielectric layer 1-1, a metal gate 1-2, a P type wide bandgap semiconductor layer 1-3, a barrier layer 1-4, a channel layer 1-5, a metal source 1-6, a metal drain 1-7, a buffer layer 1-8, a substrate 1-9 and a dielectric passivation layer 1-10, wherein the buffer layer 1-8 is arranged on the substrate, the channel layer 1-5 is arranged on the buffer layer, the barrier layer 1-4 is arranged on the channel layer, and the metal source 1-6 and the metal drain 1-7 are arranged on the channel layer 1-5 and are respectively positioned at two ends of the barrier layer 1-4;
the metal gate structure is characterized in that an insulated gate dielectric layer 1-1, a P-type wide bandgap semiconductor layer 1-3 and a metal gate 1-2 are sequentially laminated from bottom to top to form an MIS gate part, and the MIS gate part is arranged on the upper surface of a barrier layer 1-4 and is positioned on one side adjacent to a metal source 1-6; dielectric passivation layers 1-10 cover the remaining surfaces of the barrier layers.
2. An enhancement mode GaN device with a P-type gate, comprising: the device comprises an insulated gate dielectric layer 2-1, a P-type wide bandgap semiconductor layer 2-3, a metal gate 2-2, a barrier layer 2-4, a channel layer 2-5, a metal source 2-6, a P-type electric field shielding region 2-7, an N-type current path region 2-8, an N-type voltage-withstanding layer 2-9, a first dielectric passivation layer 2-10, a second dielectric passivation layer 2-11, a substrate 2-12 and a metal drain 2-13, wherein the metal drain 2-13 is arranged below the substrate, the voltage-withstanding layer 2-9 is arranged on the substrate, the voltage-withstanding layer is provided with two P-type electric field shielding regions 2-7 and a current path region 2-8 between the two P-type electric field shielding regions, the metal drain 2-5 is arranged on the P-type electric field shielding regions and the current path region, and the barrier layer 2-4 is arranged on the channel layer;
the MOS transistor is characterized in that the insulated gate dielectric layer 2-3, the P-type wide bandgap semiconductor layer 2-1 and the metal gate 2-2 are sequentially stacked from bottom to top to form an MIS gate part, and the MIS gate part is arranged on the barrier layer; the first dielectric passivation layer 2-10 covers the rest of the surface of the barrier layer and the areas of the two sides of the P-type wide bandgap semiconductor layer 2-3, the second dielectric passivation layer 2-11 covers the first dielectric passivation layer and the upper surface of the metal gate 2-2, the metal source electrode 2-6 covers the upper surface of the second dielectric passivation layer, and the two sides of the metal source electrode are respectively contacted with the barrier layer 2-4, the channel layer 2-5 and the P-type electric field shielding region.
Further, in the first or second GaN device, the P-type wide bandgap semiconductor layer forms a schottky contact or an ohmic contact with the gate metal
Further, in the first or second GaN device, the P-type wide bandgap semiconductor is made of a P-type semiconductor material with a work function not less than 6ev, such as P-GaN or P-AlGaN, wherein an Al molar composition of AlGaN can be adjusted according to design requirements; the P-type wide bandgap semiconductor layer is doped to be larger than 1 × 10 19 cm -3 Is superior.
Further, in the first or second GaN device, the channel layer is made of GaN or InGaN.
Further, in the first or second GaN device, the barrier layer is made of AlGaN, gaN/AlGaN, alGaN/AlN, or InAlN.
Further, in the first or second GaN device described above, the substrate is made of Si, siC, or Al 2 O 3 And (4) preparing.
Further, in the first GaN device, the buffer layer is made of C-doped or Fe-doped high-resistance GaN or AlGaN.
Furthermore, the insulated gate dielectric layer 1-1 extends to cover the surface of the dielectric passivation layer 1-10 at two sides of the MIS gate part.
Further, in the second GaN device, the P-type electric field shielding region 2-7, the N-type current path region 2-8, and the N-type voltage-withstanding layer 2-9 are made of the same material, specifically GaN or AlGaN; the doping concentration of the N-type current path area is greater than that of the N-type voltage-resistant layer.
The invention has the effective effects that:
the invention provides an enhanced GaN device with a P-type gate, which comprises a transverse device and a longitudinal device, wherein high-concentration two-dimensional electron gas below a P-type wide bandgap semiconductor layer and a gate dielectric layer is exhausted by utilizing the high work function difference of the semiconductor below the P-type wide bandgap semiconductor layer and the gate dielectric layer to obtain the enhanced device; compared with an HEMT device adopting p-GaN arranged on a traditional barrier layer, the HEMT device has the advantages that the high threshold voltage is obtained, meanwhile, the conduction of a heterojunction diode parasitic in the traditional structure is avoided, so that extremely low grid leakage and extremely high grid voltage swing are obtained, and the driving loss, the design difficulty of a driving circuit and the complexity can be reduced; compared with the traditional MIS technology of directly arranging a metal gate electrode on a gate dielectric layer, the invention utilizes the characteristic that the work function of a P-type wide bandgap semiconductor is higher than that of a common metal, obtains high threshold voltage under the condition of thick barrier design, and avoids a plurality of defects caused by the recess-gate etching technology required by the traditional MIS structure.
In conclusion, by introducing the novel MIS gate structure, the invention realizes the enhancement type device with extremely low gate drive current and high threshold voltage of extremely high gate voltage swing under the thick barrier layer design without adopting a received-gate structure and a fluorine ion implantation process, and has the advantages of low specific on resistance, simple process, high consistency, low cost and high stability.
Drawings
Fig. 1 is a schematic diagram of a cell of a conventional p-GaN gate HEMT device.
FIG. 2 is a schematic diagram of a conventional received-gate HEMT device cell.
FIG. 3 is a schematic diagram of an enhanced lateral GaN device cell in example 1 of the invention; the device comprises a substrate, a metal grid, a barrier layer, a channel layer, a source ohmic contact metal layer, a drain ohmic contact metal layer, a buffer layer, a substrate and a medium passivation layer, wherein 1-1 is an insulated gate dielectric layer, 1-3 is a P-type wide bandgap semiconductor layer, 1-2 is the metal grid, 1-4 is the barrier layer, 1-5 is the channel layer, 1-6 is the source ohmic contact metal layer, 1-7 is the drain ohmic contact metal layer, 1-8 is the buffer layer, 1-9 is the substrate, and 1-10 is the medium passivation layer.
Fig. 4 is a graph showing transfer characteristics and gate current waveforms of the enhancement mode lateral GaN device in example 1 of the present invention.
Fig. 5 is a schematic diagram of an enhanced lateral GaN device cell in embodiment 2 of the invention.
FIG. 6 is a schematic view of an enhancement mode vertical GaN device cell in embodiment 3 of the invention; the metal gate structure comprises a substrate, a metal gate, a barrier layer, a UID channel layer, a metal source electrode, a P-type electric field shielding region, an N-type current circuit region, an N-type voltage-withstanding layer, a first dielectric passivation layer, a second dielectric passivation layer, a substrate and a metal drain electrode, wherein 2-1 is an insulated gate dielectric layer, 2-3 is a P-type wide bandgap semiconductor layer, 2-2 is a metal gate, 2-4 is the barrier layer, 2-5 is the UID channel layer, 2-6 is the metal source electrode, 2-7 is the P-type electric field shielding region, 2-8 is the N-type current circuit region, 2-9 is the N-type voltage-withstanding layer, 2-10 is the first dielectric passivation layer, 2-11 is the second dielectric passivation layer, 2-12 is the substrate, and 2-13 is the metal drain electrode.
Detailed Description
In order to make the objects, technical solutions and technical effects of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention.
Example 1
The present embodiment provides an enhancement type lateral GaN device with P-type gate, whose structure is shown in fig. 3, including: the structure of the thin film transistor comprises an insulated gate dielectric layer 1-1, a metal gate 1-2, a P type wide bandgap semiconductor layer 1-3, a barrier layer 1-4, an unintentional doping (UID) channel layer 1-5, a metal source 1-6, a metal drain 1-7, a buffer layer 1-8, a substrate 1-9 and a dielectric passivation layer 1-10, wherein the buffer layer 1-8 is arranged on the substrate, the channel layer 1-5 is arranged on the buffer layer, the barrier layer 1-4 is arranged on the channel layer, and the metal source 1-6 and the metal drain 1-7 are arranged on the channel layer 1-5 and are respectively positioned at two ends of the barrier layer 1-4;
the MIS grid part is formed by sequentially laminating an insulated gate dielectric layer 1-1, a P type wide bandgap semiconductor layer 1-3 and a metal grid 1-2 from bottom to top, and is arranged on the upper surface of a part of the barrier layer 1-4 and positioned at one side adjacent to the metal source 1-6; dielectric passivation layers 1-10 cover the remaining surfaces of the barrier layers.
Furthermore, in this embodiment, the substrate is P-type Si, the buffer layer is C-doped GaN, the channel layer is 400nm UID-GaN, the barrier layer is AlGaN with a molar composition of 0.2, the thickness thereof is 10nm, and the P-type wide bandgap semiconductor layer is doped with a concentration of 2 × 10 19 cm -3 、4×10 19 cm -3 、6×10 19 cm -3 Or 8X 10 19 cm -3 p-GaN of (2), the insulated gate dielectric being 25nm Al 2 O 3 The grid source interval and the grid drain interval are respectively 1.5 mu m and 10 mu m, the grid is 2 mu m long, the grid metal and the p-GaN layer are in contact with each other to form ohmic contact, and the medium passivation layer is 100nm SiN.
Based on the above parameters, the transfer characteristic curve and the gate current waveform of the MIS gate enhanced lateral GaN device in this embodiment are shown in fig. 4, and compare with the correlation curve of the conventional p-GaN HEMT under the same size design. As can be seen, the device of the invention realizes the enhancement characteristic, and the threshold voltage is under each p-GaN doping>2V, and is higher than the traditional p-GaN HEMT; more importantly, the device V GS The grid current density at the time of =15V is only in the pA/mm order, compared with the traditional p-GaN HEMTV GS The mA/mm magnitude is reduced by several orders of magnitude when the voltage is not less than 6V; because the grid current of the traditional p-GaN HEMT is too large, the grid voltage of the traditional p-GaN HEMT is generally limited below 6V, and the grid voltage can still keep extremely low grid current when being obviously increased to 15V or above, so that the design difficulty of a driving circuit is reduced, the grid voltage overvoltage protection requirement is lowered, and the power consumption of the driving circuit is reduced. Although the invention compares to p-GaN HEMTs with a specific on-resistance R on,sp Slightly increased, but will be significantly reduced compared with the MIS structure with the same threshold voltage by adopting the thick barrier layer design.
In terms of working principle: in the novel MIS gate structure, firstly, the introduction of the MIS gate avoids the conduction of a heterojunction diode formed by a gate and a barrier layer of the traditional p-GaN HEMT, thereby obtaining extremely low gate leakage and extremely high gate voltage swing; then, the two-dimensional electron gas below the p-GaN is further exhausted by utilizing the work function of the p-GaN which is higher than that of the traditional metal by about 2V, so that an enhanced device with high threshold voltage is obtained; because the work function of the p-GaN is extremely high, even the design of the thick barrier layer can easily exhaust the two-dimensional electron gas below the thick barrier layer, and the recess-gate technology required by the traditional metal gate MIS structure is avoided. Compared to the present inventor application No.: 202210146339.7, the present invention places p-GaN above the dielectric layer rather than below it, to avoid the influence of floating p-GaN under the dielectric layer on the stability of threshold voltage; in addition, the p-GaN doping arranged on the dielectric layer is difficult to diffuse to the AlGaN barrier layer and the UID channel layer through the dielectric layer, so that the problem that the compromise relationship between the diffusion state of impurities diffusing into the AlGaN barrier layer and the UID channel layer is difficult to optimize due to the doping and annealing conditions when the p-GaN is arranged below the dielectric layer is avoided, and the requirement on the specific annealing condition of the p-GaN is also avoided; in addition, the p-GaN arranged on the dielectric layer is completely ionized and exhausted at the interface of the dielectric layer, and even if the impurity activation energy of the p-GaN is very high, the design of the threshold voltage is not influenced, so that the requirement that the p-GaN activation energy is low in the traditional structure and the aforementioned patent is avoided, and the requirement of high hole concentration is obtained as far as possible, thereby reducing the activation requirement on the p-GaN and reducing the process difficulty and cost.
It is further noted that: in the device, when the substrate is replaced by SiC or sapphire, the buffer layer is replaced by high-resistance AlGaN, and the P-type wide bandgap semiconductor layer is replaced by P-AlGaN, the channel layer is replaced by InGaN, and the barrier layer is replaced by GaN/AlGaN, alGaN/AlN or InAlN.
It should be noted that the materials, the molar compositions of the materials, the doping concentrations, the lengths and the thicknesses illustrated in the embodiment do not limit the protection scope of the present invention, and all of the parameters can be adaptively and optimally designed according to the needs of the application; furthermore, the corresponding gate field plate, source electrode and drain field plate can be designed according to the requirement of voltage resistance.
Example 2
This example provides an enhancement mode lateral GaN device with P-type gate, the structure of which is shown in fig. 5, and the only difference from example 1 is that: the gate dielectric layer 1-1 extends to cover the upper surface of the dielectric passivation layer 1-10 at two sides of the MIS gate part; the present embodiment has the same operation principle and beneficial effects as embodiment 1.
Example 3
Based on the same MIS gate structure of embodiment 1, this embodiment provides an enhanced vertical GaN device with P-type gate, whose structure is shown in fig. 6, which specifically includes: the device comprises an insulated gate dielectric layer 2-1, a P-type wide bandgap semiconductor layer 2-3, a metal gate 2-2, a barrier layer 2-4, an unintended doping (UID) channel layer 2-5, a metal source 2-6, a P-type electric field shielding region 2-7, an N-type current path region 2-8, an N-type voltage-withstanding layer 2-9, a first dielectric passivation layer 2-10, a second dielectric passivation layer 2-11, a substrate 2-12 and a metal drain 2-13, wherein the metal drain 2-13 is arranged below the substrate, the voltage-withstanding layer 2-9 is arranged on the substrate, the voltage-withstanding layer is provided with two P-type electric field shielding regions 2-7 and a current path region 2-8 between the two P-type electric field shielding regions, the channel layer 2-5 is arranged on the P-type electric field shielding regions and the current path region, and the barrier layer 2-4 is arranged on the channel layer;
an insulating dielectric layer 2-1, a P type wide bandgap semiconductor layer 2-3 and a metal grid 2-2 are sequentially laminated from bottom to top to form an MIS grid part, and the MIS grid part is arranged on a barrier layer; the first dielectric passivation layer 2-10 covers the rest of the surface of the barrier layer and the two side regions of the P-type wide bandgap semiconductor layer 2-3 and the insulating dielectric layer 2-1, the second dielectric passivation layer 2-11 covers the first dielectric passivation layer and the upper surface of the metal gate 2-2, the metal source electrode 2-6 covers the upper surface of the second dielectric passivation layer, and the two sides of the metal source electrode are respectively contacted with the first dielectric passivation layer, the barrier layer 2-4, the channel layer 2-5 and the P-type electric field shielding region.
Further, in this embodiment, the substrate is made of heavily N-doped GaN or AlGaN, and the voltage-withstanding layer is made of lightly N-doped GaN or AlGaN, usually with a concentration of 1 × 10 14 ～1×10 17 cm -3 The current path region is made of N-type GaN or AlGaN and has a concentration higher than that of the voltage-resistant layer; the barrier layer is made of AlGaN, gaN/AlGaN, alGaN/AlN or InAlN, and the Al molar component of AlGaN or the In molar component of InAlN is adaptively designed according to the application requirement; the P-type wide bandgap semiconductor layer is P-type GaN or AlGaN with concentration greater than 1 × 10 19 cm -3 The molar composition of Al of the P-type AlGaN can be adjusted according to different requirements, and the thickness of the P-type wide bandgap semiconductor layer is adaptively designed according to application requirements.
In terms of working principle: in this embodiment, the MIS gate portion is the same as embodiment 1, the gate control principle is similar to that in embodiment 1, and the transfer characteristic curve and the gate current are also similar to those in embodiment 1, which have the same characteristics and advantageous effects.
Where mentioned above are merely embodiments of the invention, any feature disclosed in this specification may, unless stated otherwise, be replaced by alternative features serving equivalent or similar purposes; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.
Claims (10)
1. An enhancement mode GaN device with a P-type gate, comprising: the structure of the semiconductor device comprises an insulated gate dielectric layer (1-1), a metal gate (1-2), a P type wide bandgap semiconductor layer (1-3), a barrier layer (1-4), a channel layer (1-5), a metal source electrode (1-6), a metal drain electrode (1-7), a buffer layer (1-8), a substrate (1-9) and a dielectric passivation layer (1-10), wherein the buffer layer (1-8) is arranged on the substrate, the channel layer (1-5) is arranged on the buffer layer, the barrier layer (1-4) is arranged on the channel layer, and the metal source electrode (1-6) and the metal drain electrode (1-7) are arranged on the channel layer (1-5) and are respectively located at two ends of the barrier layer (1-4);
the metal gate structure is characterized in that the insulated gate dielectric layer (1-1), the P-type wide bandgap semiconductor layer (1-3) and the metal gate (1-2) are sequentially stacked from bottom to top to form an MIS gate part, and the MIS gate part is arranged on the upper surface of the barrier layer (1-4) and is positioned on one side adjacent to the metal source (1-6); a dielectric passivation layer (1-10) covers the remaining surface of the barrier layer.
2. An enhancement mode GaN device with a P-type gate, comprising: the field-effect transistor comprises an insulated gate dielectric layer (2-1), a P-type wide bandgap semiconductor layer (2-3), a metal gate (2-2), a barrier layer (2-4), a channel layer (2-5), a metal source electrode (2-6), a P-type electric field shielding region (2-7), an N-type current path region (2-8), an N-type voltage-withstanding layer (2-9), a first dielectric passivation layer (2-10), a second dielectric passivation layer (2-11), a substrate (2-12) and a metal drain electrode (2-13), wherein the metal drain electrode (2-13) is arranged below the substrate, the voltage-withstanding layer (2-9) is arranged on the channel layer, the voltage-withstanding layer is provided with two P-type electric field shielding regions (2-7) and a current path region (2-8) between the two P-type electric field shielding regions, the channel layer (2-5) is arranged on the P-type electric field shielding regions and the current path region, and the barrier layer (2-4) is arranged on the voltage-withstanding layer;
the MOS transistor is characterized in that the insulating gate dielectric layer (2-3), the P-type wide bandgap semiconductor layer (2-1) and the metal gate (2-2) are sequentially stacked from bottom to top to form an MIS gate part, and the MIS gate part is arranged on the barrier layer; the first dielectric passivation layer (2-10) covers the rest of the surface of the barrier layer and the two side regions of the P-type wide bandgap semiconductor layer (2-3), the second dielectric passivation layer (2-11) covers the first dielectric passivation layer and the upper surface of the metal gate (2-2), the metal source electrode (2-6) covers the upper surface of the second dielectric passivation layer (2-11), and the two sides of the metal source electrode are respectively contacted with the first dielectric passivation layer (2-10), the barrier layer (2-4), the channel layer (2-5) and the P-type electric field shielding region.
3. An enhancement mode GaN device with P-type gate as claimed in claim 1 or 2 wherein said P-type wide bandgap semiconductor layer forms a schottky contact or an ohmic contact with the gate metal.
4. The enhancement mode GaN device having P-type gate of claim 1 or 2 wherein said P-type wide bandgap semiconductor is made of P-type semiconductor material having a work function of not less than 6 eV.
5. The P-gated enhancement mode GaN device of claim 1 or 2 wherein said channel layer is GaN or InGaN.
6. The P-gated enhancement mode GaN device of claim 1 or 2, wherein said barrier layer is comprised of AlGaN, or GaN/AlGaN, or AlGaN/AlN, or InAlN.
7. The enhanced GaN device with P-type gate of claim 1 or 2, wherein the substrate is made of Si, siC or Al 2 O 3 And (4) preparing.
8. The enhanced GaN device with P-type gate of claim 1, wherein said buffer layer is made of high resistance GaN or AlGaN.
9. The enhanced GaN device with P-type gate of claim 1 wherein said insulated gate dielectric layer 1-1 extends over the surface of the dielectric passivation layer 1-10 on both sides of said MIS gate portion.
10. The enhancement mode GaN device with P-type gate of claim 2, wherein the P-type electric field shielding region, the N-type current path region and the N-type voltage-withstanding layer are made of the same material, specifically GaN or AlGaN.
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