CN115547938A - 半导体装置以及封装件 - Google Patents
半导体装置以及封装件 Download PDFInfo
- Publication number
- CN115547938A CN115547938A CN202210715398.1A CN202210715398A CN115547938A CN 115547938 A CN115547938 A CN 115547938A CN 202210715398 A CN202210715398 A CN 202210715398A CN 115547938 A CN115547938 A CN 115547938A
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- China
- Prior art keywords
- base substrate
- semiconductor device
- conductor pattern
- semiconductor chip
- bonding wire
- Prior art date
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Abstract
本发明涉及半导体装置以及封装件。半导体装置具备:基底基板,该基底基板是导电性的;半导体芯片,搭载于所述基底基板,具有信号焊盘;框体,包围所述半导体芯片并搭载于所述基底基板上,具有在俯视观察下具有内侧的第一上表面和比所述第一上表面高的外侧的第二上表面的台阶,设于所述第一上表面的第一导电体图案电连接于所述基底基板;电容性部件,搭载于所述第一导电体图案上;信号端子,搭载于所述框体的所述第二上表面上;第一接合线,将所述信号焊盘与所述电容性部件的上表面电连接;第二接合线,将所述电容性部件的上表面与所述信号端子电连接;以及盖,与所述框体的所述第二上表面接合,将所述半导体芯片密封于空隙。
Description
技术领域
本发明涉及半导体装置以及封装件(package),例如涉及搭载半导体芯片和电容性部件的半导体装置以及封装件。
背景技术
已知:半导体芯片、电容性部件以及框体搭载于基底基板上,通过接合线将半导体芯片上的焊盘与电容性部件的上表面连接,通过接合线将电容性部件的上表面与框体上的信号端子连接(例如专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2019-530202号公报
为了确保基底基板与框体的接合强度,要求将框体的宽度设为规定以上。因此,若在基底基板上的框体内搭载半导体芯片和电容性部件,则半导体装置会大型化。
发明内容
本公开是鉴于上述问题而完成的,其目的在于使半导体装置小型化。
本公开的一个实施方式是一种半导体装置,具备:基底基板,该基底基板是导电性的;半导体芯片,搭载于所述基底基板,具有信号焊盘;框体,包围所述半导体芯片并搭载于所述基底基板上,具有在俯视观察下具有内侧的第一上表面和比所述第一上表面高的外侧的第二上表面的台阶,设于所述第一上表面的第一导电体图案电连接于所述基底基板;电容性部件,搭载于所述第一导电体图案上;信号端子,搭载于所述框体的所述第二上表面上;第一接合线,将所述信号焊盘与所述电容性部件的上表面电连接;第二接合线,将所述电容性部件的上表面与所述信号端子电连接;以及盖,与所述框体的所述第二上表面接合,将所述半导体芯片密封于空隙。
本公开的一个实施方式是一种封装件,具备:基底基板,该基底基板是导电性的,具有能供半导体芯片搭载的区域;以及框体,包围所述半导体芯片并搭载于所述基底基板上,具有在俯视观察下具有内侧的第一上表面和比所述第一上表面高的外侧的第二上表面的台阶,所述第一上表面电连接于所述基底基板的上表面且所述第二上表面与所述基底基板电隔离,所述第一上表面具有能供电容性部件搭载的区域。
发明效果
根据本公开,能进行小型化。
附图说明
图1是实施例1的半导体装置的俯视图。
图2是图1的A-A剖视图。
图3是图2的半导体芯片和电容性部件附近的放大图。
图4是实施例1的半导体装置的电路图。
图5是比较例1的半导体装置的放大剖视图。
图6是比较例2的半导体装置的放大剖视图。
图7是实施例1的变形例1的半导体装置的放大剖视图。
图8是实施例1的变形例2的半导体装置的放大剖视图。
图9是实施例1的变形例3的半导体装置的放大剖视图。
图10是实施例1的变形例4的半导体装置的放大剖视图。
图11是实施例1的变形例5的半导体装置的俯视图。
图12是实施例1的变形例6的半导体装置的俯视图。
图13是实施例2的半导体装置的俯视图。
图14是实施例2中的半导体芯片和电容性部件附近的放大图。
图15是实施例2的变形例1的半导体装置的放大剖视图。
图16是实施例2的变形例2的半导体装置的放大剖视图。
图17是实施例2的变形例3的半导体装置的放大剖视图。
图18是实施例2的变形例4的半导体装置的放大剖视图。
附图标记说明
10:封装件
11:基底基板
12:框体
12a:厚膜部
12b:薄膜部
12c:中间部
13a:上表面(第二上表面)
13b:上表面(第一上表面)
13c:上表面(第三上表面)
14b:导电体图案(第一导电体图案)
14c:导电体图案(第二导电体图案)
14a~14c、15:导电体图案
16:贯通电极
16a、16c:导电体层
16b:内部布线
17、19、35、44:接合构件
18:盖
18a:侧部
18b:上部
20:输出引线(信号端子)
21:空隙
22:输入引线
24:接合线(第二接合线)
25:接合线(第一接合线)
26、27:接合线
30:半导体芯片
31:半导体基板
32、33:电极(信号焊盘)
34、42、43、47、48:电极
40、45:电容性部件
41、46:电介质基板
50:放大器
52:输出匹配电路
54:输入匹配电路
Q1:晶体管。
具体实施方式
[本公开的实施方式的说明]
首先,列举本公开的实施方式的内容来进行说明。
(1)本公开的一个实施方式是一种半导体装置,具备:基底基板,该基底基板是导电性的;半导体芯片,搭载于所述基底基板,具有信号焊盘;框体,包围所述半导体芯片并搭载于所述基底基板上,具有在俯视观察下具有内侧的第一上表面和比所述第一上表面高的外侧的第二上表面的台阶,设于所述第一上表面的第一导电体图案电连接于所述基底基板;电容性部件,搭载于所述第一导电体图案上;信号端子,搭载于所述框体的所述第二上表面上;第一接合线,将所述信号焊盘与所述电容性部件的上表面电连接;第二接合线,将所述电容性部件的上表面与所述信号端子电连接;以及盖,与所述框体的所述第二上表面接合,将所述半导体芯片密封于空隙。由此,能进行小型化。
(2)也可以是,所述第二接合线接合于所述信号端子。
(3)也可以是,所述电容性部件的上表面与所述信号端子的上表面的高度差比所述电容性部件的厚度与所述信号端子的厚度之差小。
(4)也可以是,所述盖具备:侧部,接合于所述框体的所述第二上表面;以及上部,设于所述半导体芯片的上方,所述侧部在俯视观察下的比所述第二接合线接合于所述信号端子的部位靠外侧接合于所述信号端子的上表面。
(5)也可以是,所述台阶在俯视观察下的所述第一上表面与所述第二上表面之间具有比所述第一上表面高且比所述第二上表面低的第三上表面,在所述第三上表面上设有与所述信号端子电连接的第二导电体图案,所述第二接合线经由所述第二导电体图案连接于所述信号端子。
(6)也可以是,所述电容性部件的上表面与所述第二导电体图案的上表面的高度差小于所述电容性部件的厚度与所述第一上表面和所述第二上表面的高度差之差。
(7)也可以是,所述盖具备:侧部,接合于所述框体的所述第二上表面;以及上部,设于所述半导体芯片的上方,所述侧部与所述第二上表面接合,不与所述第三上表面接合。
(8)也可以是,所述半导体芯片具备晶体管,所述信号焊盘是向所述晶体管输入高频信号的输入焊盘和从所述晶体管输出高频信号的输出焊盘中的至少一个。
(9)也可以是,所述第一导电体图案与所述基底基板通过贯通所述框体的贯通电极或设于所述框体的内侧的侧面的另外的导电体层被电连接。
(10)本公开的一个实施方式是一种封装件,具备:基底基板,该基底基板是导电性的,具有能供半导体芯片搭载的区域;以及框体,包围所述半导体芯片并搭载于所述基底基板上,具有在俯视观察下具有内侧的第一上表面和比所述第一上表面高的外侧的第二上表面的台阶,所述第一上表面电连接于所述基底基板的上表面且所述第二上表面与所述基底基板电隔离,所述第一上表面具有能供电容性部件搭载的区域。
[本公开的实施方式的详情]
以下,参照附图对本公开的实施方式的半导体装置以及封装件的具体例进行说明。需要说明的是,本公开并不限定于这些示例,而是由权利要求书示出,意图在于包括与权利要求书等同的含义和范围内的所有变更。
[实施例1]
图1是实施例1的半导体装置的俯视图。图2是图1的A-A剖视图。图1是卸下了盖18的俯视图。将基底基板11的上表面的法线方向设为Z方向,将从输入引线22到输出引线20的方向设为X方向,将与X方向和Z方向正交的方向设为Y方向。
如图1和图2所示,在实施例1的半导体装置100中,封装件10主要具有基底基板11、框体12以及盖18。基底基板11例如是铜和钼的层叠基板等导电性基板。接地电位等基准电位被供给至基底基板11。框体12和盖18例如是由FR-4(Flame Retardant Type 4:阻燃型4)等的树脂或陶瓷形成的电介质层。在±X侧的边,框体12成为内侧的上表面13b比外侧的上表面13a低的台阶。在上表面13a设有导电体图案14a,在上表面13b设有导电体图案14b。+X侧的导电体图案14b经由贯通电极16与基底基板11电连接。即,导电体图案14b与基底基板11为大致相同电位。导电体图案14a与基底基板11电隔离。导电体图案14a、14b和贯通电极16例如是金层或铜层等金属层,例如是镀覆金属。在-X侧的导电体图案14a上搭载有输入引线22,在+X侧的导电体图案14a上搭载有输出引线20。输入引线22和输出引线20例如是在铜引线上镀金而成的金属引线。基底基板11上具有能供半导体芯片30搭载的区域,框体12的薄膜部12b的上表面13b具有能供电容性部件40搭载的区域。
在基底基板11上搭载有半导体芯片30和电容性部件45。半导体芯片30具备:半导体基板31;电极32和33,设于半导体基板31的上表面;以及电极34(参照图3),形成于半导体基板31的下表面。电极32、33以及34分别是栅电极、漏电极以及源电极,电极32和33分别是输入焊盘和输出焊盘等信号焊盘。电极32、33以及34例如是金层等金属层。电极34电连接于基底基板11而短路。电容性部件45具备:电介质基板46;电极47,设于电介质基板46的上表面;以及电极48,设于电介质基板46的下表面。电极48电连接于基底基板11而短路。在设于上表面13b的导电体图案14b上搭载有电容性部件40。电容性部件40具备:电介质基板41;电极42,设于电介质基板41的上表面;以及电极43,设于电介质基板41的下表面。电极43经由贯通电极16电连接于基底基板11而短路。电极43与基底基板11为相同电位。电介质基板41和46例如是相对介电常数为30以上的高介电常数系陶瓷材料,电极42、43、47以及48是金层等金属层。
接合线24将输出引线20与电容性部件40的电极42电连接。接合线25将电容性部件40的电极42与半导体芯片30的电极33电连接。接合线26将半导体芯片30的电极32与电容性部件45的电极47电连接。接合线27将电容性部件45的电极47与输入引线22电连接。盖18具有:侧部18a,接合于框体12的上表面13a;以及上部18b,设于半导体芯片30、电容性部件40和45的上方。盖18将半导体芯片30、电容性部件40和45密封于作为气体的空隙21。
图3是图2的半导体芯片30和电容性部件40附近的放大图。如图3所示,框体12具有厚膜部12a和比厚膜部12a薄的薄膜部12b。厚膜部12a和薄膜部12b的下表面是大致平坦的。通过厚膜部12a和薄膜部12b的上表面形成台阶。厚膜部12a和薄膜部12b的上表面分别是上表面13a和13b。在框体12的下表面设有导电体图案15,导电体图案15与基底基板11通过接合构件17接合。接合构件17例如是导电性的钎料。半导体芯片30的电极34与基底基板11通过接合构件35连接。电容性部件40的电极43与导电体图案14b通过接合构件44接合。接合构件35和44例如是使银膏等金属膏烧结而成的导电性构件。框体12的上表面13a和输出引线20与盖18的侧部18a通过接合构件19接合。接合构件19例如是绝缘性树脂粘接剂。
在实施例1的图3中,将从基底基板11的上表面起到框体12的上表面13a和13b为止的高度分别设为H1和H2。导电体图案14a、14b、15和接合构件17与框体12相比足够薄,因此高度H1和H2大致为厚膜部12a和薄膜部12b的厚度。将从输出引线20的上表面起到盖18的上部18b的下表面为止的高度设为H4,将框体12与基底基板11的接合的宽度设为D1,将侧部18a与框体12和输出引线20的接合的宽度设为D2,将框体12与半导体芯片30的距离设为D3,将厚膜部12a与电容性部件40的距离设为D4,将盖18的下表面与接合线25的距离设为D5,将侧部18a的宽度设为D6。作为一个例子,H1、H2、H4、D1、D2、D3、D4、D5以及D6分别为0.5mm、0.25mm、0.8mm、1.25mm、0.55mm、0.3mm、0.2mm、0.43mm以及0.6mm。
图4是实施例1的半导体装置的电路图。如图4所示,半导体装置100是高输出放大电路,具备放大器50、输出匹配电路52以及输入匹配电路54。放大器50具备例如FET(FieldEffect Transistor:场效应晶体管)等晶体管Q1。晶体管Q1例如是GaN HEMT(GalliumNitride High Electron Mobility Transistor:氮化镓高电子迁移率晶体管)或LDMOS(Laterally Diffused Metal Oxide Semiconductor:横向扩散金属氧化物半导体)。晶体管Q1的源极S接地,栅极G经由输入匹配电路54连接于输入端子Tin,漏极D经由输出匹配电路52连接于输出端子Tout。放大器50对应于半导体芯片30,源极S、栅极G以及漏极D分别对应于电极34、32以及33。
输出匹配电路52具备电感器L1、L2和电容器C1。电感器L1和L2串联连接于漏极D与输出端子Tout之间。电容器C1的一端连接于电感器L1与L2之间的节点,另一端接地。电感器L1、L2和电容器C1分别对应于接合线25、24和电容性部件40。输出匹配电路52使放大器50的输出阻抗与输出端子Tout的输出阻抗匹配。
输入匹配电路54具备电感器L3、L4和电容器C2。电感器L3和L4串联连接于栅极G与输入端子Tin之间。电容器C2的一端连接于电感器L3与L4之间的节点,另一端接地。电感器L3、L4和电容器C2分别对应于接合线27、26和电容性部件45。输入匹配电路54使放大器50的输入阻抗与输入端子Tin的输入阻抗匹配。
放大电路例如是3.3GHz~3.8GHz的功率放大电路,从输入端子Tin输入的高频信号被放大器50放大并从输出端子Tout输出。
[比较例1]
图5是比较例1的半导体装置的放大剖视图。如图5所示,在封装件内未设置电容性部件40。即,未设置内部输出匹配电路。框体12未形成为阶梯状,在框体12的上表面13a设有输出引线20。接合线25将半导体芯片30的电极33与输出引线20电连接。为了确保通过接合构件17实现的基底基板11与框体12的接合,在设计规则上要求将宽度D1设为规定以上。另一方面,未要求侧部18a与框体12和输出引线20的接合的宽度D2像D1那样大。这是因为,可以将树脂系的绝缘性粘接剂用于接合构件19,而接合构件17使用导电性的钎料等。此外,这是因为,基底基板11例如是金属层,框体12是绝缘体,因此,热膨胀系数之差容易变大,在基底基板11与框体12之间容易施加热应力。在一个设计规则上,D1为1.55mm。H1、H4、D2以及D3例如为0.5mm、0.8mm、0.6mm以及0.3mm。
在比较例1中,半导体芯片30与输出引线20使用接合线25连接。半导体芯片30的输出阻抗非常低,因此,在比较例1中,输出引线20的输出阻抗会变低。因此,难以改善放大电路的特性。优选在半导体芯片30与输出引线20之间设置内部匹配电路。然而,为了将内部匹配电路设于基底封装件(base package)内,要将电容性部件40搭载于基底基板11上,半导体装置会大型化。
[比较例2]
图6是比较例2的半导体装置的放大剖视图。如图6所示,在比较例2中,在框体12上设有导电体图案14b。导电体图案14b与导电体图案14a电隔离。导电体图案14b经由贯通电极16电连接于基底基板11。在比较例2中,通过将电容性部件40搭载于框体12上,即使不扩大基底基板11的X方向的宽度,也能将电容性部件40搭载于封装件内。通过设置接合线24和25,能将图4的输出匹配电路52搭载于封装件内。由此,能使半导体装置小型化。能将电容性部件40搭载于框体12上是因为盖18的侧部18a与框体12的接合的宽度D2可以比框体12与基底基板11的接合的宽度D1窄。
在3.3GHz~3.8GHz频段的放大电路的情况下,图4中的输出匹配电路52的电感器L1的电感和电容器C1的电容的一个例子分别为0.387nH和8pF。在阻抗的匹配主要由电感器L1和电容器C1进行的情况下,将电感器L2的电感减小为0.15nH。电感器L1中的0.387nH的电感可以通过将接合线25的长度设为1.76mm、将接合线25的根数设为16根、将接合线25的间隔设为0.25mm来实现。需要说明的是,电感不仅影响接合线25的长度,而且还影响接合线25的形状。电容器C1中的8pF的电容可以通过将电介质基板41的相对介电常数设为250、将电介质基板41的厚度设为0.25mm、将电介质基板41的外形设为3.5mm×0.4mm、将电极42的形状设为3.4mm×0.3mm来实现。为了减小电感器L2的电感,缩短接合线24的长度,增加接合线24的根数。
若为了半导体装置的小型化而将半导体芯片30与框体12的距离D3符合设计规则地设为最小,并将接合线25的长度设定为例如1.76mm以便能作为电感器L1而得到所期望的电感,则接合线25与盖18的上部18b的下表面的距离D5例如变小为0.2mm。在形成接合线25后,将盖18接合于框体12上。此时,若接合线25与上部18b的下表面发生干扰(例如接触),则接合线25的形状发生变化。由此,电感器L1的电感会改变。由此,输出匹配电路52的特性会发生变化,可能会变得无法得到所期望的放大电路的性能。
为了抑制接合线25与盖18的上部18b的下表面的干扰,可以想到增大上部18b的下表面距基底基板11的高度。但是,封装件的高度变大,半导体装置会大型化。可以想到减薄框体12。但是,若减薄框体12,则输出引线20与被供给接地电位的基底基板11的距离变短,会影响输出引线20的高频信号的传播特性。
而且,在比较例2中,当电容性部件40的电极42比输出引线20的上表面高时,为了缩短接合线24,缩短盖18的侧部18a与电容性部件40的距离D4。距离D4例如为0.14mm。作为电容性部件40的搭载时和将盖18接合于框体12时的余量,距离D4的设计规则例如为0.2mm,无法满足设计规则。
根据实施例1,如图3所示,具有电极33(信号焊盘)的半导体芯片30搭载于基底基板11。框体12包围半导体芯片30并搭载于基底基板11上。框体12具有在俯视观察下具有内侧的上表面13b(第一上表面)和比上表面13b高的外侧的上表面13a(第二上表面)的台阶。设于上表面13b上的导电体图案14b(第一导电体图案)电连接于基底基板11。电容性部件40搭载于导电体图案14b上,输出引线20和导电体图案14a搭载于框体12的上表面13a上。接合线25(第一接合线)将电极33与电容性部件40的上表面电连接,接合线24(第二接合线)将电容性部件40的上表面与输出引线20电连接。盖18与框体12的上表面13a接合,将半导体芯片30密封于空隙21。
由此,电容性部件40配置于比比较例2更靠近基底基板11的高度的位置。由此,能增大盖18的上部18b的下表面与接合线25的距离D5。例如能使D5为0.43mm左右。由此,盖18不干扰接合线25,输出匹配电路52的特性不发生变化,并且能使半导体装置小型化。
接合线24直接接合于输出引线20的上表面。由此,能缩短接合线24。此外,通过适当地设定上表面13b的高度H2,能使电容性部件40的电极42的上表面与输出引线20的上表面的高度差H5比比较例2的电容性部件40的电极42的上表面与输出引线20的上表面的高度差H5a小。由此,即使将电容性部件40与侧部18a的距离D4设为作为设计规则的例如0.2mm,也能将接合线24的长度设为与比较例2的图6相同的程度。导电体图案14a、14b和接合构件44与电容性部件40和输出引线20相比足够薄。此时,为了使实施例1中的图3的高度差H5比比较例2中的高度差H5a小,高度差H5优选比电容性部件40的厚度T1与输出引线20的厚度T2之差小。高度差H5更优选为厚度T1与T2之差的1/2以下。
[实施例1的变形例1]
图7是实施例1的变形例1的半导体装置的放大剖视图。如图7所示,盖18的侧部18a的宽度D6与实施例1的图3相同。侧部18a的外侧的侧面位于以距离D8比框体12的外侧的侧面靠外侧的位置。距离D8例如为0.2mm。由此,能增大厚膜部12a的内侧的端面与侧部18a的内侧的侧面的距离D7。距离D7例如为0.25mm。侧部18a与框体12和输出引线20接合的宽度D2比实施例1小。在侧部18a与框体12的接合强度足够的情况下,可以缩短宽度D2。其他构成与实施例1相同,省略说明。
在实施例1的图3中,侧部18a的内侧的侧面与接合线24的距离小,在将盖18接合于框体12和输出引线20上时,接合线24可能会被压溃。在实施例1的变形例1中,将侧部18a配置于比实施例1靠外侧,因此能扩大距离D7。即,能扩大输出引线20上的对接合线24进行接合的区域。由此,能抑制接合线24的压溃。此外,通过使侧部18a的宽度D6与实施例1的图3相同,能维持侧部18a的强度。
[实施例1的变形例2]
图8是实施例1的变形例2的半导体装置的放大剖视图。如图8所示,在实施例1的变形例2中,与实施例1的变形例1相比,使侧部18a的宽度D6减薄至与宽度D2相同的大小。其他构成与实施例1的变形例1相同,省略说明。在实施例1的变形例2中,能与实施例1的变形例1同样地抑制接合线24的压溃。而且,侧部18a的外侧的侧面与框体12的外侧的侧面大致一致。由此,与实施例1的变形例1的图7相比,能使半导体装置的外形小型化为与实施例1相同的程度。
[实施例1的变形例3]
图9是实施例1的变形例3的半导体装置的放大剖视图。在实施例1的变形例3中,与实施例1的变形例2相比,以输出引线20的内侧的端面的位置与盖18的侧部18a的内侧的侧面的位置成为大致相同的方式使输出引线20的位置向外侧移动。其结果是,如图9所示,接合线24接合于导电体图案14a。其他构成与实施例1的变形例2相同,省略说明。如实施例1的变形例3那样,接合线24也可以接合于导电体图案14a。导电体图案14a和输出引线20作为输出端子发挥功能。
在实施例1及其变形例1~3中,接合线24接合于输出引线20或导电体图案14a(即信号端子)。由此,能将电容性部件40与输出端子电连接。盖18的侧部18a在俯视观察下的比接合线24接合于输出引线20或导电体图案14a的部位靠外侧接合于输出引线20。由此,能抑制在将盖18接合于框体12时会将接合线24压溃。如实施例1的变形例1~3那样,厚膜部12a的内侧的端面与侧部18a的内侧的侧面的距离D7优选为厚膜部12a的宽度的1/4以上。由此,能确保接合线24接合于输出引线20或导电体图案14a的区域。
[实施例1的变形例4]
图10是实施例1的变形例4的半导体装置的放大剖视图。如图10所示,未设置贯通电极16,导电体层16a设于薄膜部12b的内侧的侧面。导电体层16a将导电体图案14b与导电体图案15电连接。其他构成与实施例1相同,省略说明。
如实施例1及其变形例1~4那样,导电体图案14b与基底基板11通过贯通框体12的薄膜部12b的贯通电极16或设于框体12的薄膜部12b的内侧的侧面的另外的导电体层16a被电连接。由此,能简单地将导电体图案14b与基底基板11电连接。其结果是,能将搭载于框体12的薄膜部12b上的电容性部件40的下表面的电极43经由接合构件44简单地电连接于基底基板11。
[实施例1的变形例5]
图11是实施例1的变形例5的半导体装置的俯视图。如图11所示,电容性部件45搭载于输入引线22(-X)侧的框体12的上表面13b上。电容性部件45的电极48(未图示)经由贯通导电体图案14b和框体12的贯通电极连接于基底基板11。其他构成与实施例1相同,省略说明。如实施例1的变形例5那样,与输入匹配电路54的电容器C2对应的电容性部件45也可以搭载于上表面13b上。如此,供电容性部件40或45连接的半导体芯片30的信号焊盘是向晶体管输入高频信号的电极32(输入焊盘)和从晶体管输出高频信号的电极33(输出焊盘)中的至少一个。
[实施例1的变形例6]
图12是实施例1的变形例6的半导体装置的俯视图。如图12所示,在基底基板11上搭载有两个半导体芯片30和两个电容性部件45,在框体12的薄膜部12b的上表面13b上搭载有两个电容性部件40。在框体12的厚膜部12a的上表面13a上设有两个输入引线22和两个输出引线20。两个半导体芯片30例如相当于多赫蒂放大电路的载波放大器和峰值放大器。其他构成与实施例1相同,省略说明。也可以在半导体装置设有多个半导体芯片30、电容性部件40等。
[实施例2]
图13是实施例2的半导体装置的俯视图。图14是实施例2中的半导体芯片30和电容性部件40附近的放大图。如图13和图14所示,在半导体装置102中,框体12在薄膜部12b与厚膜部12a之间具有中间部12c。中间部12c比薄膜部12b厚且比厚膜部12a薄。在中间部12c的上表面13c设有导电体图案14c。导电体图案14c在厚膜部12a内延伸。导电体图案14a与14c通过厚膜部12a内的内部布线16b被电连接而短路。导电体图案14a与14c为相同电位。接合线24接合于导电体图案14c。中间部12c的上表面13c距基底基板11的高度为H3。H1、H2以及H3例如为0.5mm、0.125mm以及0.375mm。厚膜部12a的内侧的侧面与中间部12c的内侧的侧面的距离D9例如为0.2mm。其他构成与实施例1相同,省略说明。
根据实施例2,台阶在俯视观察下的厚膜部12a的上表面13a与薄膜部12b的上表面13b之间具有比上表面13b高且比上表面13a低的、中间部12c的上表面13c(第三上表面)。在中间部12c的上表面13c上设有导电体图案14c(第二导电体图案)。导电体图案14c经由内部布线16b电连接于输出引线20(信号端子)。接合线24接合于导电体图案14c,经由导电体图案14c、内部布线16b以及导电体图案14a电连接于输出引线20。
由此,与实施例1的图3相比,能进一步降低搭载电容性部件40的位置。由此,能增长盖18的上部18b的下表面与接合线25的距离D5。由此,能抑制盖18的上部18b与接合线25的干扰。
此外,即使搭载电容性部件40的薄膜部12b的上表面13b的高度H2比实施例1低,也能减小电容性部件40的电极42的上表面与导电体图案14c的上表面的高度差H5b。由此,即使将接合线24的长度设为与比较例2相同的程度,也能确保电容性部件40的侧面与中间部12c的内侧的侧面的距离D4。由此,能使半导体装置小型化。导电体图案14a~14c和接合构件44与框体12、电容性部件40以及输出引线20相比足够薄。此时,为了使实施例2中的图14的高度差H5b比实施例1中的高度差H5小,高度差H5b优选小于电容性部件40的厚度T1与薄膜部12b的上表面13b和厚膜部12a的上表面13a的高度差H1-H2之差。高度差H5b更优选为厚度T1与差H1-H2之差的1/2以下。
[实施例2的变形例1]
图15是实施例2的变形例1的半导体装置的放大剖视图。如图15所示,盖18的侧部18a的宽度D6与实施例2的图14相同。侧部18a的外侧的侧面位于以距离D8比框体12的外侧的侧面靠外侧的位置。距离D8例如为0.15mm。由此,能增大中间部12c的端面与侧部18a的内侧的侧面的距离D7。在侧部18a与框体12的接合强度足够的情况下,可以缩短宽度D2。其他构成与实施例2相同,省略说明。
在实施例2的变形例1中,将侧部18a配置于比实施例2靠外侧,因此能扩大距离D7。由此,能抑制接合线24的压溃。此外,通过使侧部18a的宽度D6与实施例2的图14相同,能维持侧部18a的强度。
[实施例2的变形例2]
图16是实施例2的变形例2的半导体装置的放大剖视图。如图16所示,侧部18a的宽度D6跟侧部18a与输出引线20的接合的宽度D2相同。其他构成与实施例2的变形例1相同,省略说明。在实施例2的变形例2中,能与实施例2的变形例1同样地抑制接合线24的压溃。而且,侧部18a的外侧的侧面与框体12的外侧的侧面大致一致。由此,与实施例2的变形例1的图15相比,能使半导体装置的外形小型化为与实施例2相同的程度。
[实施例1的变形例3]
图17是实施例2的变形例3的半导体装置的放大剖视图。如图17所示,侧部18a与输出引线20的接合的宽度D2跟侧部18a的宽度D6大致相同。D2和D6例如为0.25mm。侧部18a的内侧的侧面位于以例如0.2mm比厚膜部12a的内侧的侧面靠外侧的位置。由此,能扩大中间部12c的内侧的侧面与侧部18a的距离D7。其他构成与实施例2的变形例2相同,省略说明。
在实施例2的变形例3中,能比实施例2的变形例2进一步抑制接合线24的压溃。而且,侧部18a的外侧的侧面与框体12的外侧的侧面大致一致。由此,能使半导体装置的外形小型化为与实施例2相同的程度。
如实施例2及其变形例那样,侧部18a与上表面13a接合,不与上表面13c接合。由此,能抑制在将盖18接合于框体12时会将接合线24压溃。
[实施例2的变形例4]
图18是实施例2的变形例4的半导体装置的放大剖视图。如图18所示,在实施例2的变形例4中,在薄膜部12b的端部的侧面设有导电体层16a来代替贯通电极16。导电体层16a将导电体图案14b与15电连接而短路。在上表面13a与13c之间的厚膜部12a的内侧的侧面设有导电体层16c来代替内部布线16b。导电体层16c将导电体图案14a与14c电连接而短路。其他构成与实施例2相同,省略说明。在实施例2的变形例4中,也可以不使导电体图案14c在框体12内延伸。因此,框体12的制造变得容易。
如实施例2及其变形例1~4那样,导电体图案14c与输出引线20可以通过框体12内的内部布线16b被电连接,也可以通过设于厚膜部12a的侧面的导电体层16c被电连接。在实施例1、2及其变形例中,框体12既可以成型为多个构件,之后进行接合,也可以树脂成型为一体。
应该认为本次所公开的实施方式在所有方面均是示例而不是限制性的。本公开的范围并不是由上述的含义示出,而是由权利要求书示出,意图在于包括与权利要求书等同的含义和范围内的所有变更。
Claims (10)
1.一种半导体装置,具备:
基底基板,该基底基板是导电性的;
半导体芯片,搭载于所述基底基板,具有信号焊盘;
框体,包围所述半导体芯片并搭载于所述基底基板上,具有在俯视观察下具有内侧的第一上表面和比所述第一上表面高的外侧的第二上表面的台阶,设于所述第一上表面的第一导电体图案电连接于所述基底基板;
电容性部件,搭载于所述第一导电体图案上;
信号端子,搭载于所述框体的所述第二上表面上;
第一接合线,将所述信号焊盘与所述电容性部件的上表面电连接;
第二接合线,将所述电容性部件的上表面与所述信号端子电连接;以及
盖,与所述框体的所述第二上表面接合,将所述半导体芯片密封于空隙。
2.根据权利要求1所述的半导体装置,其中,
所述第二接合线接合于所述信号端子。
3.根据权利要求2所述的半导体装置,其中,
所述电容性部件的上表面与所述信号端子的上表面的高度差比所述电容性部件的厚度与所述信号端子的厚度之差小。
4.根据权利要求2或3所述的半导体装置,其中,
所述盖具备:侧部,接合于所述框体的所述第二上表面;以及上部,设于所述半导体芯片的上方,
所述侧部在俯视观察下的比所述第二接合线接合于所述信号端子的部位靠外侧接合于所述信号端子的上表面。
5.根据权利要求1所述的半导体装置,其中,
所述台阶在俯视观察下的所述第一上表面与所述第二上表面之间具有比所述第一上表面高且比所述第二上表面低的第三上表面,在所述第三上表面上设有与所述信号端子电连接的第二导电体图案,
所述第二接合线经由所述第二导电体图案连接于所述信号端子。
6.根据权利要求5所述的半导体装置,其中,
所述电容性部件的上表面与所述第二导电体图案的上表面的高度差小于所述电容性部件的厚度与所述第一上表面和所述第二上表面的高度差之差。
7.根据权利要求5或6所述的半导体装置,其中,
所述盖具备:侧部,接合于所述框体的所述第二上表面;以及上部,设于所述半导体芯片的上方,
所述侧部与所述第二上表面接合,不与所述第三上表面接合。
8.根据权利要求1至7中任一项所述的半导体装置,其中,
所述半导体芯片具备晶体管,所述信号焊盘是向所述晶体管输入高频信号的输入焊盘和从所述晶体管输出高频信号的输出焊盘中的至少一个。
9.根据权利要求1至8中任一项所述的半导体装置,其中,
所述第一导电体图案与所述基底基板通过贯通所述框体的贯通电极或设于所述框体的内侧的侧面的另外的导电体层被电连接。
10.一种封装件,具备:
基底基板,该基底基板是导电性的,具有能供半导体芯片搭载的区域;以及
框体,包围所述半导体芯片并搭载于所述基底基板上,具有在俯视观察下具有内侧的第一上表面和比所述第一上表面高的外侧的第二上表面的台阶,所述第一上表面电连接于所述基底基板的上表面且所述第二上表面与所述基底基板电隔离,所述第一上表面具有能供电容性部件搭载的区域。
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