CN115526848A

CN115526848A - Circuit detection method, circuit detection device, electronic equipment, computer readable medium and product

Info

Publication number: CN115526848A
Application number: CN202211139416.2A
Authority: CN
Inventors: 谢怡彤
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-09-19
Filing date: 2022-09-19
Publication date: 2022-12-27

Abstract

The application discloses a circuit detection method, a circuit detection device, an electronic device, a computer readable medium and a computer readable product, wherein the method comprises the following steps: acquiring a to-be-detected picture and a to-be-detected mark corresponding to a to-be-detected circuit board, wherein the to-be-detected mark comprises a mark corresponding to a to-be-detected connecting line in the to-be-detected circuit board; extracting a region corresponding to the connecting line corresponding to the identifier to be detected from the picture to be detected based on the identifier to be detected, and using the region as a target connecting line region; and determining an identification result of the circuit board to be detected based on the difference between the target connecting line region and the standard connecting line region, wherein the identification result is used for representing that the target connecting line region has defects or does not have defects. The target connecting line region is determined based on the mark to be detected, and the difference between the target connecting line region and the standard connecting line region is compared, so that whether the circuit board to be detected has defects can be determined, the consumption of computing resources can be reduced, the time consumption of processing is reduced, and the efficiency is improved.

Description

Circuit detection method, circuit detection device, electronic equipment, computer readable medium and product

Technical Field

The present disclosure relates to the field of circuit board technologies, and in particular, to a circuit detection method, an apparatus, an electronic device, a computer-readable medium, and a computer product.

Background

At present, with the rapid development of electronic information technology, the wiring on the circuit board is more and more dense. Although the defect detection can be performed on the produced circuit board, the current method for performing defect detection on the circuit board consumes more computing resources and requires longer processing time.

Disclosure of Invention

The present application provides a circuit detection method, apparatus, electronic device, computer readable medium and product, so as to overcome the above-mentioned drawbacks.

In a first aspect, an embodiment of the present application provides a circuit detection method, where the method includes: taking a picture to be detected and a mark to be detected corresponding to a circuit board to be detected, wherein the mark to be detected comprises a mark corresponding to a connecting line to be detected in the circuit board to be detected; extracting a region corresponding to the connecting line corresponding to the identifier to be detected from the picture to be detected based on the identifier to be detected, and using the region as a target connecting line region; and determining an identification result of the circuit board to be detected based on the difference between the target connecting line region and the standard connecting line region, wherein the identification result is used for representing whether the target connecting line region has defects or does not have defects.

In a second aspect, an embodiment of the present application further provides a circuit detection apparatus, which is applied to an electronic device, and the apparatus includes: the acquiring unit is used for responding to a preemption request of a target thread and acquiring a lock holding state of a current thread, wherein the lock holding state comprises a public lock or no public lock; the processing unit is used for releasing the public lock held by the current thread and seizing CPU resources occupied by the current thread if the lock holding state of the current thread is that the public lock is held; and the execution unit is used for executing the target thread based on the preempted CPU resource.

In a third aspect, an embodiment of the present application further provides an electronic device, including: one or more processors; a memory; one or more computer programs, wherein the one or more computer programs are stored in the memory and configured to be executed by the one or more processors to cause the electronic device to perform the method of the first aspect.

In a fourth aspect, this application further provides a computer-readable storage medium storing program code executable by a processor, where the program code causes the processor to execute the method of the first aspect when executed by the processor.

In a fifth aspect, the present application further provides a computer program product, which includes a computer program/instruction, and when executed by a processor, the computer program/instruction implements the method of the first aspect.

According to the circuit detection method, the circuit detection device, the electronic equipment, the computer readable medium and the computer readable product, firstly, a picture to be detected and a mark to be detected corresponding to a circuit board to be detected are obtained, then, based on the mark to be detected, a region corresponding to a connecting line corresponding to the mark to be detected is extracted from the picture to be detected and is used as a target connecting line region, and finally, based on the difference between the target connecting line region and a standard connecting line region, a recognition result of the circuit board to be detected is determined, wherein the recognition result is used for representing that the target connecting line region has defects or does not have defects. If the circuit board to be detected has defects by comparing all the areas in the picture to be detected corresponding to the circuit board to be detected with all the areas in the standard template picture, more computing resources are consumed, the processing time is more, and the efficiency is lower. Because the area with the defects in the circuit board to be detected is generally the area corresponding to the connecting line, the target connecting line area is determined based on the mark to be detected, and the difference between the target connecting line area and the standard connecting line area is compared, so that whether the circuit board to be detected has the defects or not can be determined, the consumption of computing resources can be reduced, the processing time is reduced, and the efficiency is improved.

Additional features and advantages of embodiments of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of embodiments of the present application. The objectives and other advantages of the embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a flow chart of a method of circuit detection provided by an embodiment of the present application;

FIG. 2 illustrates a schematic diagram of a circuit board provided by an embodiment of the present application;

FIG. 3 illustrates a schematic diagram of a circuit board provided by yet another embodiment of the present application;

FIG. 4 illustrates a schematic diagram of a circuit board provided by yet another embodiment of the present application;

FIG. 5 illustrates a method flow diagram of a circuit detection method provided by yet another embodiment of the present application;

FIG. 6 shows a diagram of an embodiment of step S250;

fig. 7 shows an implementation diagram of step S251;

FIG. 8 is a flow chart of a method of circuit detection provided by a further embodiment of the present application;

FIG. 9 shows a diagram of an embodiment of step S350;

FIG. 10 is a block diagram of a circuit testing device according to an embodiment of the present disclosure;

fig. 11 shows a block diagram of an electronic device provided in an embodiment of the present application;

FIG. 12 is a block diagram illustrating a structure of a computer-readable storage medium provided by an embodiment of the present application;

fig. 13 shows a block diagram of a computer program product provided in an embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

At present, with the rapid development of electronic information technology, the wiring on the circuit board is more and more dense. Although the defect detection can be performed on the produced circuit board, the current method for performing defect detection on the circuit board consumes more computing resources and requires longer processing time. How to consume less computing resources and detect the defects of the circuit board in a shorter time is an urgent problem to be solved.

At present, more and more functions can be realized by electronic equipment, a circuit board is used as an important component of the electronic equipment, the wiring on the circuit board is more and more dense, and more electronic components are arranged. Furthermore, an integrated chip can be arranged on the circuit board, the integrated chip can be packaged in a packaging substrate, and the packaging substrate is arranged on the circuit board. The packaging substrate can protect, fix and support the integrated chip on one hand, enhances the heat conduction and heat dissipation performance of the integrated chip, ensures that the integrated chip is not easily damaged physically, and on the other hand, the upper layer of the packaging substrate is connected with the chip, and the lower layer of the packaging substrate is connected with the circuit board to realize electrical and physical connection, power distribution, signal distribution and the like, for example, different wiring on the circuit board can be electrically connected with different pins of the integrated chip in the packaging substrate.

However, when a circuit board or a package substrate is manufactured, a trace connection error, such as a missing connection or a misconnection, may occur. For example, if the trace A1 and the trace A2 on the circuit board are designed to be isolated from each other, and the trace A1 and the trace A2 are electrically connected by mistake during production, a short circuit may occur between the trace A1 and the trace A2. For another example, if the trace A1 and the trace A2 on the circuit board should be electrically connected when being designed, and the trace A1 and the trace A2 are erroneously isolated during generation, an open circuit may occur between the trace A1 and the trace A2. Therefore, it is necessary to perform defect inspection on the produced circuit board or package substrate.

For some solutions, open/short circuit tests may be generally performed on a circuit board or package substrate. If in the open circuit/short circuit test, some circuit boards or package substrates are found to have open circuit or short circuit problems, the circuit boards or package substrates with the problems can be screened out for further defect detection, so as to determine the specific positions causing the open circuit or short circuit defects.

In the traditional circuit board production industry, a magnifier is generally adopted for manual detection and visual detection, and whether the circuit board has the defect of short circuit or open circuit is mainly judged through appearance detection.

In other schemes, the short circuit or open circuit defect in the picture can be determined by acquiring the pictures of the produced circuit boards or packaging substrates, acquiring the template pictures through a large number of circuit boards or packaging substrates which are determined to be good products, and comparing the pictures with the template pictures.

However, the inventors found in their research that the above-mentioned method for detecting defects manually has a large workload, a low inspection efficiency, a high possibility of missing, a low accuracy, and a low yield. In the method for determining the defects in the pictures by comparing the pictures with the template pictures, a good-product template needs to be determined by a large number of circuit boards or packaging substrates which are determined to be good products, and the template pictures are difficult to obtain for the circuit boards and the packaging substrates manufactured in small batches. And the image is compared with the template image, so that more resources are consumed, and the defect determining efficiency is not high.

Therefore, in order to overcome the above-mentioned drawbacks, the present application provides a circuit detection method, an apparatus, an electronic device, and a computer-readable medium and product.

Referring to fig. 1, fig. 1 illustrates a circuit detection method provided in an embodiment of the present application, where the method may be applied to an electronic device, and a specific execution subject may be a processor in the electronic device, and the method includes steps S110 to S130.

Step S110: the method comprises the steps of obtaining a picture to be detected and a mark to be detected corresponding to a circuit board to be detected, wherein the mark to be detected comprises a mark corresponding to a connecting line to be detected in the circuit board to be detected.

For some embodiments, a portion of the produced circuit boards may be selected for testing as the circuit board to be tested.

For some embodiments, the circuit board may be a single layer, wherein the circuit board may have a connecting line thereon, and the connecting line is generally made of a metal conductor material, such as copper, i.e., different positions on the connecting line are generally conducted for the same connecting line. In one example, the connection line includes a trace. Different components electrically connected to the circuit board or the package substrate can be electrically connected through the wiring. For example, if the first pin of the component 1 is connected to the trace A1 and the second pin of the component 2 is connected to the trace A1, the first pin of the component 1 and the second pin of the component 2 are substantially electrically connected.

Different wires can be isolated from each other, namely are not electrically connected with each other; different traces can also be electrically connected to each other. For example, referring to fig. 2, fig. 2 shows a schematic diagram of a circuit board 200, and the circuit board 200 shown in fig. 2 includes a trace 201, a trace 202 and a trace 203. The trace 201 is respectively isolated from the trace 202 and the trace 203, that is, the trace 201 is not electrically connected to the trace 202, and the trace 201 is not electrically connected to the trace 203; and trace 202 is electrically connected to trace 203. Therefore, the trace 202 and the trace 203 can form a connection line.

Different wires can have different widths, and the maximum current values that can be borne by the wires with different widths are different. It will be readily appreciated that the greater the width of the track, the greater the maximum current value that can be tolerated on the track. For example, if the width of the trace is 10 mils (Mil), the maximum current value that can be sustained on the trace may be 1 ampere (a); if the width of the trace is 30 mils, the maximum current value that can be borne by the trace can be 1.9 amperes; if the width of the trace is 100 mils, the maximum current that can be sustained on the trace can be 4.2 amps.

Further, for some more complex circuit boards, the target function may not be achieved by a single layer, so that the circuit board may also be a multilayer, such as a double layer, a quadruple layer, etc. For some embodiments, for a circuit board with a multi-layer structure, the connecting lines may further include vias, and the vias and the traces are similar and may generally be made of a metal conductor material, such as copper. The circuit board with the plurality of layers can be including routing layer and the layer of punching, wherein the routing layer can be provided with the line, and the layer of punching can be provided with the via hole, and the layer of punching can realize two adjacent routing layers through the via hole and electrically connect.

Therefore, for two routing layers adjacent to the same punching layer, the via holes at the same position are substantially electrically connected, and further, the routing of different layers connected with the via holes are substantially electrically connected. Fig. 3 shows a schematic diagram of a circuit board 300, which includes a first routing layer 301, a first via hole layer 302, and a second routing layer 303, where the first routing layer 301 is provided with a routing 3011, the second routing layer 303 is provided with a routing 3031, the first via hole layer 302 is provided with a via hole 3021, and the first via hole 3021 is connected to the routing 3011 and the routing 3031, respectively, so that the routing 3011 and the routing 3031 are substantially electrically connected through the via hole 3021.

The circuit board may include traces and vias, and the connection line may include a trace or a via; the connecting line may also include a plurality of traces and a plurality of vias. Optionally, as can be seen from the foregoing analysis, the circuit board may include multiple layers, and therefore, the connection line may further include traces or vias in different layers, where the traces and vias belonging to the same connection line are electrically connected. For example, referring to fig. 4, fig. 4 shows a circuit board 400 including three layers, specifically including a first routing layer 401, a first via layer 402, and a second routing layer 403, where the first routing layer 401 includes traces 4011, traces 4012, and vias 4013, the first via layer 402 includes vias 4013, and the second routing layer 403 includes traces 4031, traces 4032, and vias 4013. The trace 4011 of the first routing layer 401 is electrically connected to the trace 4031 of the second routing layer 403 through the via 4013, so that the trace 4011, the via 4013, and the trace 4031 may belong to the same connection line.

For an embodiment provided by the application, the circuit board to be detected can be a plurality of circuit boards obtained by production, namely, the circuit boards obtained by production are detected; the circuit board to be detected may also be a circuit board with defects after a plurality of produced circuit boards are subjected to pre-detection, and reference may be specifically made to the following embodiments.

Through the analysis, the circuit board to be detected can comprise a plurality of connecting wires, and if each connecting wire in the circuit board to be detected is detected, more computing resources are consumed, and the detection efficiency is low. Therefore, when the circuit board to be detected is detected, the mark to be detected of the circuit board to be detected is firstly acquired, the mark to be detected comprises the mark corresponding to the connecting wire to be detected in the circuit board to be detected, and then the connecting wire corresponding to the mark to be detected in the circuit board to be detected is only detected, so that the occupation of resources can be reduced, and the detection efficiency is improved.

The mark to be detected may be a mark corresponding to a connecting line which is easy to have a defect, and may be directly specified by a user, for example, the user may specify the mark corresponding to the ground connecting line in the circuit board to be detected as the mark to be detected. For other embodiments, the plurality of produced circuit boards can be pre-detected in advance, the circuit board with the defects after the plurality of circuit boards are pre-detected serves as the circuit board to be detected, wherein if the circuit board is found to have the defects after the pre-detection, the connecting wire corresponding to the defects can be acquired, at this time, the connecting wire with the defects can be directly used as the mark to be detected, the mark corresponding to the connecting wire to be detected in the circuit board to be detected comprises the mark to be detected, then the defect detection is carried out on the circuit board to be detected based on the mark to be detected, the occupation of resources can be reduced, and the detection efficiency can be improved.

Furthermore, the picture corresponding to the circuit board to be detected is the picture to be detected. It is easy to understand that the number of the point detection pictures and the number of the points and the number of the layers of the circuit board to be detected should have a corresponding relationship. Namely, if the circuit board to be detected is a single layer, the number of pictures to be detected can be one; and if the circuit board to be detected comprises a plurality of layers, the number of the pictures to be detected is more than one, and each picture to be detected corresponds to one layer of the circuit board to be detected.

Optionally, the circuit board obtained through the production may be used as a circuit board to be detected, the package substrate obtained through the production may be used as a circuit board to be detected, and the MLO board or SLP-type carrier board obtained through the production may also be used as a circuit board to be detected, which is not limited in this application.

Step S120: and based on the identifier to be detected, extracting a region corresponding to the connecting line corresponding to the identifier to be detected from the picture to be detected, and using the region as a target connecting line region.

For some embodiments, in order to detect whether a defect exists in a connecting line corresponding to an identifier to be detected in a circuit board to be detected, a region corresponding to the connecting line corresponding to the identifier to be detected may be extracted from a picture to be detected corresponding to the circuit board to be detected, and the extracted region is used as a target connecting line region. And then determining whether the connecting line corresponding to the mark to be detected in the circuit board to be detected has defects or not based on the target connecting line area.

If the circuit board to be detected is only one layer, the target area corresponding to the connecting line in the picture to be detected corresponding to the circuit board to be detected on the layer can be determined directly according to the mark to be detected. Because the circuit board to be detected is only one layer, the layer of circuit board to be detected is the top layer circuit board. It is easy to understand that, for the circuit board, the top circuit board is generally provided with identification information for representing different connecting lines, i.e. silk-screen information. For example, a "GND" identifier may be provided at the ground connection line to characterize the connection line as a ground connection line, and a "3.3V" identifier may be provided at the 3.3V connection line to characterize the connection line as a 3.3V power connection line. Therefore, for the condition that the circuit board to be detected is only one layer, the picture corresponding to the circuit board to be detected on the top layer is the picture to be detected on the top layer, each identification in the picture to be detected on the top layer can be firstly obtained, then the obtained identifications are compared with the identification to be detected, the identification which is the same as the identification to be detected is used as a target identification, then the target identification is used for determining the detection area corresponding to the connecting line corresponding to the target identification in the picture to be detected on the top layer, and at the moment, the detection area corresponding to the connecting line corresponding to the target identification in the picture to be detected on the top layer can be directly used as the target connecting line area.

Further, if the circuit board to be detected is multi-layered, the pictures to be detected corresponding to the circuit to be detected may include the top-layer pictures to be detected and other layers of pictures to be detected except the top-layer pictures to be detected. Similar to the above method, the detection area corresponding to the connection line corresponding to the target identifier in the top-layer picture to be detected can also be determined by the target identifier. And then determining the target connecting line region based on the region to be detected and other layers of pictures to be detected. Specific methods can be described with reference to the following examples.

Step S130: and determining an identification result of the circuit board to be detected based on the difference between the target connecting line region and the standard connecting line region, wherein the identification result is used for representing that the target connecting line region has defects or does not have defects.

It is easily understood that the connecting line region determined by the design file may be a standard connecting line region. Therefore, the standard connecting line region can be a connecting line region determined by the mark to be detected in the design file corresponding to the circuit board to be detected. The smaller the difference between the connecting line region on the produced circuit board and the connecting line region determined by the design file is, the smaller the defect existing in the connecting line region representing the produced circuit board is, and when the connecting line region on the produced circuit board is not different from the connecting line region determined by the design file, the defect existing in the target connecting line region representing the produced circuit board is.

For some embodiments, the obtained target connecting line region may be compared with a standard connecting line region, so as to determine an identification result of the circuit board to be detected, where the identification result is used to represent that the target connecting line region has a defect or does not have a defect.

It is easy to understand that if the range corresponding to the target connecting line region is the same as the range corresponding to the standard connecting line region, it represents that there is no difference between the target connecting line region and the standard connecting line region, and it can be determined that there is no defect in the target connecting line region of the circuit board to be detected. If the range corresponding to the target connecting line region is different from the range corresponding to the standard connecting line region, the difference between the target connecting line region and the standard connecting line region is represented, and the target connecting line region of the circuit board to be detected can be determined to have the defect.

Further, the target connection line region and the standard connection line region have a difference, which may include that the range corresponding to the target connection line region is larger than the range corresponding to the standard connection line region, and the range corresponding to the target connection line region is smaller than the range corresponding to the standard connection line region. Through the relationship between the range corresponding to the target connecting line region and the range corresponding to the standard connecting line region, it can be determined that the target connecting line region has different defects, and specifically, reference may be made to the description of the subsequent embodiment.

For example, the target connecting line region may be identified in a highlighted manner in the picture to be detected.

Referring to fig. 5, fig. 5 illustrates a circuit detection method provided in an embodiment of the present application, where the method may be applied to an electronic device, and a specific execution subject may be a processor in the electronic device, and the method includes steps S210 to S260.

Step S210: the method comprises the steps of obtaining a picture to be detected and a mark to be detected corresponding to a circuit board to be detected, wherein the mark to be detected comprises a mark corresponding to a connecting line to be detected in the circuit board to be detected.

The to-be-detected picture and the to-be-detected mark corresponding to the to-be-detected circuit board are obtained, which have been described in detail in the foregoing embodiments, and are not described here again.

For some embodiments, the acquired to-be-detected picture of the to-be-detected circuit board may include different colors, for example, the circuit board may be identified by a green ground color, the trace or via hole in the circuit board may be identified by yellow, and the chip or component arranged on the circuit board may be identified by black. It will be readily appreciated that the areas of the circuit board to be inspected where defects are present may typically be traces or vias. Therefore, after the picture to be detected of the circuit board to be detected is obtained, the picture to be detected can be preprocessed, so that the wiring and the via hole are highlighted in the picture to be detected. For example, the obtained picture to be detected may be subjected to binarization processing. Specifically, the gray value of each pixel point in the picture to be detected can be obtained, then the gray value of each pixel point in the picture to be detected is compared with the specified threshold by setting the specified threshold, and the pixel point corresponding to the gray value smaller than the specified threshold can be set as a first color, and the pixel point corresponding to the gray value equal to or larger than the specified threshold can be set as a second color. Therefore, the picture to be detected can be processed to only comprise two colors through the binarization processing, the routing and the via hole can be displayed as one color through setting a specified threshold value, and other parts can be displayed as a second color.

Further, according to the analysis, the circuit board to be detected can comprise a plurality of layers, so that a picture to be detected can be collected from each layer of the circuit board to be detected, and a plurality of pictures to be detected can be obtained, wherein each picture to be detected corresponds to each layer of the circuit board to be detected.

Optionally, because there may be a small error in the size of each acquired picture to be detected, for some embodiments, the acquired pictures to be detected may be subjected to size unification processing to obtain the pictures to be detected with the same size.

Step S220: and acquiring the identifier in the top layer picture to be detected.

Step S230: and taking the mark in the top layer picture to be detected which is the same as the mark to be detected as a target mark.

For some embodiments, the circuit board to be detected includes a plurality of layers, and the picture to be detected includes a plurality of pictures, it is easily understood that the picture to be detected may be a picture corresponding to each layer of the circuit board to be detected, and therefore each picture to be detected corresponds to each layer of the circuit board to be detected in sequence. For example, if the circuit board to be detected includes three layers, the number of the pictures to be detected is three, the first layer of the circuit board to be detected corresponds to the first picture to be detected, the second layer of the circuit board to be detected corresponds to the second picture to be detected, and the third layer of the circuit board to be detected corresponds to the third picture to be detected. The first layer of circuit board to be detected can be the top layer of circuit board to be detected, so the first layer of picture to be detected can be the top layer of picture to be detected.

Through the analysis, the top layer circuit board to be detected is generally provided with identification information for representing different connecting lines, so that the identification in the top layer picture to be detected can be obtained firstly. And further, the mark in the top-layer picture to be detected, which is the same as the mark to be detected, in the obtained mark is used as a target mark. For example, if the obtaining of the identifier in the top-level picture to be detected includes: "3.3V", "5V", "SIG" already "GND", if the identifier to be detected obtained in the foregoing step includes "GND", it is easy to know that the identifier "GND" in the picture to be detected on the top layer is the same as the identifier to be detected, that is, the identifier "GND" can be used as the target identifier.

Step S240: and extracting a to-be-detected area corresponding to the connecting line corresponding to the target identification from the top layer to-be-detected picture.

For some embodiments, as can be seen from the foregoing analysis, the top layer of the circuit board to be detected includes the connection lines, and the target mark corresponds to a portion of the connection lines. Therefore, the connecting lines included in the top-layer circuit board to be detected also exist in the top-layer picture to be detected corresponding to the top-layer circuit board to be detected, so that the area to be detected corresponding to the connecting lines corresponding to the target identification can be extracted from the top-layer picture to be detected.

Wherein, the top layer is to detect the sign that includes in the picture, and the correspondence has the connecting wire, and further, different signs correspond and have different connecting wires. Therefore, the area where the connecting line corresponding to the target identifier is located in the top-layer picture to be detected can be used as the area to be detected.

Optionally, for other embodiments, after the identifier to be detected is obtained, a region corresponding to the identifier to be detected in a design file corresponding to the circuit board to be detected may also be searched, where the design file includes a standard identifier and a connecting line region corresponding to the identifier. And then comparing the design file with the top-layer picture to be detected, thereby determining the region to be detected in the top-layer picture to be detected.

Step S250: and determining the target connecting line region based on the region to be detected.

By introducing the foregoing steps, the region to be detected is a corresponding region in the top-layer picture to be detected. However, the circuit board to be detected may include multiple layers, and if only the region to be detected in the top layer picture to be detected is determined, it is essential that only the region to be detected in the top layer circuit board to be detected is subjected to defect detection, which may cause defects in other layers to be missed. Therefore, after the region to be detected corresponding to the top layer picture to be detected is determined, the corresponding region in the pictures to be detected of other layers except the top layer picture to be detected can be determined based on the region to be detected, and the region to be detected and the corresponding region are integrated to obtain the target connecting line region. Therefore, the target connecting line area comprises an area corresponding to the mark to be detected in each layer of circuit board to be detected.

Specifically, referring to fig. 6, fig. 6 shows an implementation diagram of step S250, which specifically includes step S251 and step S252.

Step S251: and determining a subordinate to-be-detected region which has a connection relation with the to-be-detected region from each to-be-detected picture except the top layer to-be-detected picture in the plurality of to-be-detected pictures.

Step S252: and integrating to obtain the target connecting line region based on the region to be detected and the subordinate region to be detected.

As can be seen from the foregoing analysis, each layer of the circuit board to be tested may include a connection line, and the connection lines of each layer may have an electrical connection relationship with each other. Therefore, after the area to be detected is determined by the top-layer picture to be detected, because the area to be detected is substantially the area corresponding to the connecting line to be detected in the top-layer picture to be detected, a plurality of subordinate areas to be detected in each picture to be detected except the top-layer picture to be detected, which have a connection relationship with the area to be detected, can be obtained, that is, a plurality of layers of circuit boards to be detected can be obtained, and a subordinate connecting line to be detected, which has a connection relationship with the connecting line to be detected, is in each layer of circuit boards to be detected except the top-layer circuit board to be detected.

The connection relationship may include a direct connection relationship and an indirect connection relationship. The region connected with the region to be detected in the next picture to be detected in the top layer can be used as the region having a direct connection relation with the region to be detected. Further, if there is an area connected with the area to be detected, the other layers of the picture to be detected except the picture to be detected on the top layer and the picture to be detected next to the picture to be detected on the top layer can be used as an indirect connection relation with the area to be detected. Specifically, referring to fig. 7, fig. 7 is a diagram illustrating an implementation of step S251, which specifically includes step S253 and step S254.

Step S253: and based on the detection sequence, taking the region connected with the region to be detected in the next picture to be detected in the top layer picture to be detected as a subordinate region to be detected with a direct connection relationship.

Step S254: traversing each subsequent picture to be detected of the next picture to be detected based on the detection sequence, and taking a region connected with the subordinate region to be detected with the direct connection relationship in each subsequent picture to be detected of the next picture as the subordinate region to be detected with the indirect connection relationship.

For some embodiments, each layer of the circuit boards to be detected corresponds to one picture to be detected, and the plurality of pictures to be detected may be arranged according to a detection sequence, where the detection sequence may be an arrangement sequence of the plurality of layers of circuit boards to be detected.

Therefore, after the region to be detected is determined through the foregoing steps, a region connected to the region to be detected in a next picture to be detected in the top layer picture to be detected can be used as a subordinate region to be detected having a direct connection relationship, based on the detection sequence.

Specifically, the determination of the region connected to the region to be detected is substantially to determine whether a connection line corresponding to the region to be detected included in the top layer picture to be detected and a connection line in the next picture to be detected have an electrical connection relationship. For an implementation manner, the top-layer picture to be detected and the next picture to be detected which are preprocessed in the previous step can be overlapped, then whether a connecting line which is at least partially overlapped with the connecting line corresponding to the region to be detected in the top-layer picture to be detected exists in the next picture to be detected or not is searched, if the connecting line which is at least partially overlapped with the connecting line corresponding to the region to be detected exists, the connecting line which is at least partially overlapped with the connecting line corresponding to the region to be detected can be determined to have a direct connection relation, and therefore the region corresponding to the connecting line which is directly connected in the next picture to be detected can be used as an auxiliary region to be detected.

Furthermore, the circuit board to be detected can be multilayer, so that each subsequent picture to be detected of the next picture to be detected can be traversed continuously according to the detection sequence, whether a connecting line which is at least partially overlapped with a connecting line corresponding to a subordinate region to be detected in the next picture to be detected exists in each picture to be detected is searched, if the connecting line which is at least partially overlapped exists in each picture to be detected and the connecting line corresponding to the subordinate region to be detected can be determined to have a connection relationship, and therefore the connecting line which is at least partially overlapped and the connecting line corresponding to the region to be detected in the picture to be detected on the top layer can be determined to have an indirect connection relationship. Therefore, the area corresponding to the connecting line with the indirect connection relation can be used as the subordinate area to be detected.

As can be seen from the above analysis, for a multilayer circuit board to be detected, the top circuit board to be detected may generally be a routing layer, and the routing layer and the punching layer are generally disposed at an interval, so the next routing layer may be a punching layer, and the next punching layer may be another routing layer. Therefore, for example, when traversing each subsequent picture to be detected of the next picture to be detected, if the current picture to be detected is the nth routing layer, it may be known that the connecting line in the current picture to be detected includes the routing, and if the next layer of the current picture to be detected is the mth perforation layer, it may be indicated by tracetovia (Ln, vm) that the subordinate region to be detected having an association relationship in the mth perforation layer is searched through the nth routing layer. If the current picture to be detected is the mth layer of the perforated layer, it can be known that the connecting line in the current picture to be detected comprises a through hole, and if the next layer of the current picture to be detected is the nth layer of the wiring layer, it can be represented by viatrack (Vm, ln) that the subordinate region to be detected with the correlation in the mth layer of the perforated layer is searched for through the nth layer of the wiring layer.

Therefore, for some further embodiments, if it is assumed that the multi-layer circuit board to be tested includes x + y layers, for example, an x routing layer and a y via layer. Wherein the top layer picture to be detected may comprise a first routing layer and may therefore be characterized by L1, and the next layer picture to be detected of the top layer picture to be detected may comprise a first perforation layer and may therefore be characterized by V1. Therefore, the area connected with the area to be detected in the first wiring layer in the first layer of the perforated layer can be searched as the subordinate area to be detected with a direct connection relationship by calling tracetovia (L1, V1) firstly. Furthermore, viatrack (V1, L2) can be executed to search for a region in the second routing layer, which is connected to the subordinate region to be detected in the first drilling layer, as the subordinate region to be detected having an indirect connection relationship. Further, the execution of tracetovia and viaatotrace may be continued at intervals, for example, tracetovia (L2, V2) may be executed until tracetovia (L (x-1), vy) and viaatotrace (Vy, lx) are executed, so as to complete the traversal of each picture to be detected.

Optionally, after traversing each picture to be detected, the traversal of each picture to be detected may be performed again starting from the lowest picture to be detected, that is, starting from performing tracetovia (Lx, vy), and then performing viatone (L (x-1), vy) until tracetovia (L2, V1) and viatone (V _1, L \\ 1) are performed, so that each picture to be detected is traversed. The number of times of traversing each picture to be detected can be set according to the requirements of a user, and it is understood that the accuracy of the obtained subordinate region to be detected having a connection relation with the region to be detected is higher if the number of times of traversing each picture to be detected is more, and the time spent on traversing is shorter and the consumed computing resources are less if the number of times of traversing each picture to be detected is less.

Further, after the subordinate region to be detected is ejected, the target connecting line region may be obtained through integration based on the region to be detected and the subordinate region to be detected.

Step S260: and determining an identification result of the circuit board to be detected based on the difference between the target connecting line region and the standard connecting line region, wherein the identification result is used for representing that the target connecting line region has defects or does not have defects.

Step S260 is described in detail in the foregoing embodiments, and is not described herein again.

Referring to fig. 8, fig. 8 illustrates a circuit detection method provided by an embodiment of the present application, where the method may be applied to an electronic device, and a specific execution subject may be a processor in the electronic device, and the method includes steps S310 to S350.

Step S310: and detecting the circuit board with open circuit or short circuit in the plurality of circuit boards as the circuit board to be detected.

Step S320: and taking the mark corresponding to the connecting line with the open circuit or the short circuit in the circuit board to be detected as the mark to be detected.

For some embodiments, because the number of the produced circuit boards is generally large, if each produced circuit board is used as a circuit board to be detected and whether a defect exists is detected by the method described in the foregoing embodiment, more processing resources are consumed, and the processing efficiency is reduced. Thus, the produced circuit board can be first subjected to preliminary inspection, for example, open/short inspection. Through open circuit/short circuit detection, the circuit board with open circuit or short circuit in the produced circuit board can be determined, so that the circuit board with open circuit or short circuit is used as the circuit board to be detected, the number of the circuit boards to be detected can be reduced, meanwhile, the detection accuracy is not affected, the consumption of processing resources is reduced, and the processing efficiency is improved.

Further, if a defect is found in the circuit board after the pre-detection, the connecting line corresponding to the defect can be acquired, at this time, the connecting line with the defect can be directly used as the mark to be detected, the mark corresponding to the connecting line to be detected in the circuit board to be detected comprises the mark, and then the defect detection is performed on the circuit board to be detected based on the mark to be detected. As described in the above example, if the pre-detection is open circuit/short circuit detection, after the open circuit/short circuit detection is performed, the identification corresponding to the connection line of the circuit board to be detected, which is open circuit or short circuit, may also be determined, for example, the "GND" connection line has a short circuit, and at this time, the identification "GND" may be obtained as the identification to be detected.

Step S330: the method comprises the steps of obtaining a picture to be detected and a mark to be detected corresponding to a circuit board to be detected, wherein the mark to be detected comprises a mark corresponding to a connecting line to be detected in the circuit board to be detected.

Step S340: and based on the identifier to be detected, extracting a region corresponding to the connecting line corresponding to the identifier to be detected from the picture to be detected, and using the region as a target connecting line region.

Step S350: and determining an identification result of the circuit board to be detected based on the difference between the target connecting line region and the standard connecting line region, wherein the identification result is used for representing whether the target connecting line region has defects or does not have defects.

Wherein, the steps S330 and S340 have been described in detail in the foregoing embodiments, and are not described herein again.

For some embodiments, the defects may include open circuits and short circuits, and the presence or absence of the defect in the target connecting line region of the circuit board to be detected may be determined by comparing the difference between the target connecting line region and the standard connecting line region. Further, when there is a defect in the target connecting line region, the defect may also be determined as an open circuit or a short circuit. Specifically, referring to fig. 9, fig. 9 shows an implementation diagram of step S350, which includes step S351 and step S352.

Step S351: if the range corresponding to the target connecting line region is larger than the range corresponding to the standard connecting line region, determining the region except the range corresponding to the standard connecting line region in the range corresponding to the target connecting line region as the region of the target connecting line region on the circuit board to be detected with short circuit.

Step S352: if the range corresponding to the target connecting line region is smaller than the range corresponding to the standard connecting line region, determining the region except the range corresponding to the target connecting line region in the range corresponding to the standard connecting line region as the region of the target connecting line region on the circuit board to be detected with an open circuit.

It is easy to understand that if the range corresponding to the target connecting line region is larger than the range corresponding to the standard connecting line region, it is characterized that there is a part of target connecting lines outside the standard connecting line region, and then a short circuit may be caused. And because the circuit board to be detected is a circuit board with an open circuit or a short circuit, the target connecting line area on the circuit board to be detected can be determined to have the short circuit. The short-circuited area may be specifically an area in a range corresponding to the standard connecting line area, except for a range corresponding to the target connecting line area.

Similarly, if the range corresponding to the target connecting line region is smaller than the range corresponding to the standard connecting line region, it is represented that the target connecting line region does not exist in some regions in the range corresponding to the standard connecting line region, and an open circuit may be caused. And because the circuit board to be detected is a circuit board with an open circuit or a short circuit, the open circuit of the target connecting line region on the circuit board to be detected can be determined. The short-circuited area may be specifically an area in a range corresponding to the standard connecting line area, except for a range corresponding to the target connecting line area. The area where the open circuit exists may be specifically an area in a range corresponding to the standard connecting line area, except for a range corresponding to the target connecting line area.

According to the circuit detection method, the circuit detection device, the electronic equipment, the computer readable medium and the computer readable product, firstly, a circuit board to be detected with defects is determined from a plurality of circuit boards, and an identifier corresponding to a connecting line with an open circuit or a short circuit in the circuit board to be detected is used as the identifier to be detected; then, a picture to be detected and an identifier to be detected, which correspond to the circuit board to be detected, are obtained, then, based on the identifier to be detected, a region corresponding to a connecting line, which corresponds to the identifier to be detected, is extracted from the picture to be detected, and is used as a target connecting line region, and finally, an identification result of the circuit board to be detected can be determined based on the difference between the target connecting line region and a standard connecting line region, wherein the identification result is used for representing that the target connecting line region has defects or does not have defects. If each circuit board obtained by production is determined to have an identification result based on the difference between the target connecting line region and the standard connecting line region, more processing resources are consumed, and the detection efficiency is reduced. And this application is through in a plurality of circuit boards from the production, determine the circuit of awaiting measuring that has open circuit or short circuit defect, detect to the circuit of awaiting measuring again, when can not reduce the accuracy that detects the defect, can reduce the occupation to processing resource to improve the treatment effeciency.

Referring to fig. 10, a block diagram of a circuit detecting device 1000 according to an embodiment of the present disclosure is shown, including: an acquisition unit 1010, an extraction unit 1020, and a determination unit 1030.

The obtaining unit 1010 is configured to obtain a to-be-detected picture and a to-be-detected mark corresponding to a to-be-detected circuit board, where the to-be-detected mark includes a mark corresponding to a to-be-detected connecting line in the to-be-detected circuit board.

Further, the obtaining unit 1010 is further configured to detect a circuit board with an open circuit or a short circuit among the plurality of circuit boards, as a circuit board to be detected; and taking the mark corresponding to the connecting line with the open circuit or the short circuit in the circuit board to be detected as the mark to be detected.

An extracting unit 1020, configured to extract, from the picture to be detected, a region corresponding to the connecting line corresponding to the identifier to be detected, based on the identifier to be detected, as a target connecting line region.

Further, the extracting unit 1020 is further configured to obtain an identifier in the top-layer picture to be detected; taking the mark in the top layer picture to be detected which is the same as the mark to be detected as a target mark; extracting a to-be-detected area corresponding to the connecting line corresponding to the target identification from the top layer to-be-detected picture; and determining the target connecting line region based on the region to be detected.

Further, the extracting unit 1020 determines a subordinate to-be-detected region having a connection relation with the to-be-detected region from each to-be-detected picture except the top to-be-detected picture among the plurality of to-be-detected pictures; and integrating to obtain the target connecting line region based on the region to be detected and the subordinate region to be detected.

Further, the extracting unit 1020 regards, as a subordinate to-be-detected region having a direct connection relationship, a region connected to the to-be-detected region in a to-be-detected picture next to the top-layer to-be-detected picture based on the detection order; traversing each subsequent picture to be detected of the next picture to be detected based on the detection sequence, and taking a region connected with the subordinate region to be detected with the direct connection relationship in each subsequent picture to be detected of the next picture as the subordinate region to be detected with the indirect connection relationship.

A determining unit 1030, configured to determine an identification result of the circuit board to be detected based on a difference between the target connecting line region and the standard connecting line region, where the identification result is used to represent that the target connecting line region has a defect or does not have a defect.

Further, the determining unit 1030 is further configured to determine, if the range corresponding to the target connection line region is greater than the range corresponding to the standard connection line region, a region other than the range corresponding to the standard connection line region in the range corresponding to the target connection line region as a region where the target connection line region on the circuit board to be detected has a short circuit; if the range corresponding to the target connecting line region is smaller than the range corresponding to the standard connecting line region, determining the region except the range corresponding to the target connecting line region in the range corresponding to the standard connecting line region as the region of the target connecting line region on the circuit board to be detected with an open circuit.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, the coupling between the units may be electrical, mechanical or other type of coupling.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

Referring to fig. 11, fig. 11 is a block diagram illustrating a structure of an electronic device 1100 according to an embodiment of the present application, and the circuit detection method according to the foregoing embodiment of the present application may be applied to the electronic device 1100. The electronic device 1100 in the present application may include one or more of the following components: a processor 1110 and a memory 1120, and one or more applications, wherein the processor 1110 is electrically connected to the memory 1120, and the one or more programs are configured to perform the methods as described in the foregoing method embodiments.

Processor 1110 may include one or more processing cores. The processor 1110 interfaces with various parts throughout the electronic device 100 using various interfaces and lines to perform various functions of the electronic device 100 and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 1120 and invoking data stored in the memory 1120. Alternatively, the processor 1110 may be implemented in hardware using at least one of Digital Signal Processing (DSP), field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 1110 may integrate one or a combination of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, a computer program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is to be appreciated that the modem can be implemented by a single communication chip without being integrated into the processor 1110. In particular, the processor 1110 may be configured to perform the methods of the above embodiments.

For some embodiments, memory 1120 may include Random Access Memory (RAM) and may also include Read-Only Memory (Read-Only Memory). The memory 1120 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing various method embodiments described below, and the like. The stored data area may also store data created during use by the electronic device 1100, and the like.

Referring to fig. 12, a block diagram of a computer-readable storage medium according to an embodiment of the present application is shown. The computer readable medium 1200 has stored therein a program code which can be called by a processor to execute the method described in the above method embodiments.

The computer-readable storage medium 1200 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 1200 includes a non-volatile computer-readable storage medium. The computer readable storage medium 1200 has storage space for program code 1210 that performs any of the method steps described above. The program code can be read from or written to one or more computer program products. The program code 1210 may be compressed, for example, in a suitable form.

Referring to fig. 13, a block diagram 1300 of a computer program product according to an embodiment of the present application is shown. The computer program product 1300 comprises computer programs/instructions 1310, which computer programs/instructions 1310 when executed by a processor implement the steps of the method described above.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A method of circuit detection, the method comprising:

acquiring a to-be-detected picture and a to-be-detected mark corresponding to a to-be-detected circuit board, wherein the to-be-detected mark comprises a mark corresponding to a to-be-detected connecting line in the to-be-detected circuit board;

extracting a region corresponding to the connecting line corresponding to the identifier to be detected from the picture to be detected based on the identifier to be detected, and using the region as a target connecting line region;

and determining an identification result of the circuit board to be detected based on the difference between the target connecting line region and the standard connecting line region, wherein the identification result is used for representing whether the target connecting line region has defects or does not have defects.

2. The method according to claim 1, wherein the circuit board to be detected includes a plurality of layers, the picture to be detected includes a plurality of pictures, each picture to be detected corresponds to each layer of the circuit board to be detected in sequence, and the extracting, from the picture to be detected, a region corresponding to the connection line corresponding to the identifier to be detected as a target connection line region based on the identifier to be detected includes:

acquiring a mark in a top layer picture to be detected;

taking the mark in the top layer picture to be detected which is the same as the mark to be detected as a target mark;

extracting a to-be-detected area corresponding to the connecting line corresponding to the target identification from the top layer to-be-detected picture;

and determining the target connecting line region based on the region to be detected.

3. The method according to claim 2, wherein the determining the target connecting line region based on the region to be detected comprises:

determining a subordinate to-be-detected region which has a connection relation with the to-be-detected region from each to-be-detected picture except the top layer to-be-detected picture in the plurality of to-be-detected pictures;

and integrating to obtain the target connecting line region based on the region to be detected and the subordinate region to be detected.

4. The method according to claim 3, wherein a plurality of the pictures to be detected are arranged in a detection sequence, the connection relationship includes a direct connection relationship and an indirect connection relationship, and the determining, from each picture to be detected except the top picture, of the plurality of pictures to be detected, a subordinate picture to be detected having a connection relationship with the picture to be detected comprises:

based on the detection sequence, taking a region connected with the region to be detected in a next picture to be detected in the top layer picture to be detected as a subordinate region to be detected with a direct connection relationship;

traversing each subsequent picture to be detected of the next picture to be detected based on the detection sequence, and taking a region connected with a subordinate region to be detected with a direct connection relationship in each subsequent picture to be detected of the next picture as a subordinate region to be detected with an indirect connection relationship.

5. The method according to claim 1, wherein the defects include open circuits and short circuits, and the determining the recognition result of the circuit board to be detected based on the difference between the target connecting line region and the standard connecting line region comprises:

if the range corresponding to the target connecting line region is larger than the range corresponding to the standard connecting line region, determining the region except the range corresponding to the standard connecting line region in the range corresponding to the target connecting line region as the region of the target connecting line region on the circuit board to be detected with short circuit;

if the range corresponding to the target connecting line region is smaller than the range corresponding to the standard connecting line region, determining the region except the range corresponding to the target connecting line region in the range corresponding to the standard connecting line region as the region of the target connecting line region on the circuit board to be detected with an open circuit.

6. The method according to claim 1, wherein before the obtaining of the picture to be detected and the mark to be detected corresponding to the circuit board to be detected, the method further comprises:

detecting a circuit board with an open circuit or a short circuit in the plurality of circuit boards as a circuit board to be detected;

and taking the mark corresponding to the connecting line with the open circuit or the short circuit in the circuit board to be detected as the mark to be detected.

7. A circuit testing apparatus, the apparatus comprising:

the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a to-be-detected picture and a to-be-detected mark corresponding to a to-be-detected circuit board, and the to-be-detected mark comprises a mark corresponding to a to-be-detected connecting line in the to-be-detected circuit board;

the extraction unit is used for extracting a region corresponding to the connecting line corresponding to the identifier to be detected from the picture to be detected based on the identifier to be detected, and the region is used as a target connecting line region;

and the determining unit is used for determining the identification result of the circuit board to be detected based on the difference between the target connecting line region and the standard connecting line region, and the identification result is used for representing that the target connecting line region has defects or does not have defects.

8. An electronic device, comprising: one or more processors;

a memory;

one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of any of claims 1-6.

9. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 1 to 6.

10. A computer program product comprising computer programs/instructions, characterized in that the computer programs/instructions, when executed by a processor, implement the method of any of claims 1-6.