CN115513017A - Spindt cathode electron source and preparation method and application thereof - Google Patents

Abstract

The invention discloses a Spindt cathode electron source and a preparation method and application thereof, wherein the cathode electron source comprises the following structures: the silicon substrate, the insulating layer and the grid are sequentially arranged from bottom to top, and an insulating layer cavity is formed among the silicon substrate, the insulating layer and the grid through hole; an emission sharp cone arranged on the silicon substrate and positioned in the cavity of the insulating layer, wherein the emission sharp cone corresponds to the gate through hole; the coating layer is arranged on the silicon substrate, is positioned in the insulating layer cavity and completely covers the exposed silicon substrate in the insulating layer cavity; the attached oxide layer is positioned between the coating layer and the emission pointed cone and coats the lower side surface of the emission pointed cone; the upper side surface of the emission tip cone is exposed outside the incidental oxide layer. The cathode electron source structure avoids the unexpected electron emission of the three-combination point, thereby effectively preventing the common discharge along the network and the space arc failure caused by the discharge.

Description

Spindt cathode electron source and preparation method and application thereof

Technical Field

The invention relates to the technical field of vacuum electronics. More particularly, relates to a Spindt cathode electron source, a preparation method and application thereof.

Background

The field emission electron source based on the principle that the strong electric field induces the electron escape has the advantages of no need of external energy, room temperature work, instant start and high current density, replaces the traditional hot cathode electron source in a vacuum electronic device, is expected to retain the advantages of high frequency, high power, high temperature resistance and radiation resistance of the device, can realize smaller volume and lighter weight, and has good comprehensive advantages. The field emission electron source has potential application, including various scenes such as high-end analytical instruments, display devices, X-ray emitters, microwave power devices, high-energy particle accelerating devices, space propelling devices and the like. The development of a high-performance field emission electron source has very important significance for the development and progress of vacuum electronic devices.

The Spindt cathode is the most mature field emission electron source in the earliest development and application, and many field emission electron source researches in the later period are used as reference. Spindt cathode is an array cathode with a large number of integrated micro-emission units, and fig. 1 shows a typical unit structure, and the reference numbers of each component in fig. 1 are respectively as follows: 101-silicon substrate, 201-insulating layer, 301-gate and 401-emission tip. In normal operation, a strong electric field is generated at the surface of the 401-emission taper by applying a forward bias to the 101-silicon substrate and the 301-gate, resulting in electron emission. As the gate bias increases, the cell emission current can increase rapidly in an exponential fashion. The micro-emission units are integrated in a large number, so that the Spindt cathode can simultaneously maintain a large current density and a total current.

However, the Spindt cathode electron source often has arc failure in high-current application, which affects the reliability of the device. Relevant researches show that the most main cause of arc failure is that when a very high voltage is applied between a 301-grid electrode and a 101-silicon substrate, undesired electron emission is generated at the junction of the 101-silicon substrate, a 201-insulating layer and a vacuum, the undesired emitted electrons climb to the 301-grid electrode along the side wall of the 201-insulating layer under the action of an electric field, and are continuously collided to generate electron multiplication during the process, so that the flashover is formed, and finally, arcs are induced at the 301-grid electrode and a 401-emitting sharp cone to cause damage. For such arc failures, two related types of counterpatent technologies have been proposed in the early days.

One class of techniques seeks to block the path of electrons discharging along the network. The structure of JP-A8-321255, as shown in fig. 2, introduces a second insulating layer material, which constitutes 3 alternating insulating layers 201, 202 and 203, and in fact may also constitute 5, 7 or more layers, and the insulating sidewalls of the overall corrugated structure can be realized by using the lateral etching difference caused by the different etching selection ratios of the two materials. The side wall is insulated by the fold structure, so that electrons are generated from the 101-silicon substrate, the 201-insulating layer and the vacuum triple joint position, and the difficulty of moving to the 301-grid along the wall and generating along-the-line discharge is greatly increased. The structure of US6075315A, as shown in figure 3, also introduces another insulating layer material, but only builds up a 204-shield between the 201-insulating layer and the 301-gate. The special structure is designed to enable the 301-grid to be retracted moderately, and a 204-shielding layer is used for isolating the space from the 101-silicon substrate, the 201-insulating layer and the vacuum triple joint part to the 301-grid to be viewed directly, so that undesired emission electrons are difficult to generate along-the-line discharge to reach the 301-grid. However, this type of technique does not prevent undesired electron emission, and although increasing the difficulty of electron discharge along the channel, does not solve the fundamental problem. In addition, in the structure of the U.S. patent, due to the retraction of the 301-grid electrode, the electric field intensity of the surface of a 401-emission sharp cone under the same working voltage is greatly reduced, and the electron emission capability of the Spindt cathode is weakened.

Another type of technique seeks to interrupt the path that generates the spatial arc. The structure of US6369496B1, as shown in fig. 4, uses another insulating material to construct 205-insulating collar column to surround 401-emission tip cone, isolating it from 201-insulating layer and 301-gate to avoid space arcing. The structure of US005442193A, as shown in figure 5, uses another insulating material to construct a 206-cap layer, which completely conformal caps the 201-insulating layer and the 301-gate electrode in order to block them from spatial arcing with the 401-emission tip. However, these techniques also do not prevent the undesired electron emission fundamentally, and the former are not completely isolated, while the latter require higher operating voltages for insulation shielding reasons and also lead to insulation breakdown and spatial arcing.

Disclosure of Invention

Based on the facts, the invention aims to provide a Spindt cathode electron source, and a preparation method and application thereof, which solve the problem that the prior art cannot completely overcome the unexpected electron emission, and further can effectively prevent the common along-the-channel discharge and space arc failure of the electron source with the traditional structure.

In one aspect, the present invention provides a Spindt cathode electron source, which comprises:

the silicon substrate, the insulating layer and the grid are sequentially arranged from bottom to top, and an insulating layer cavity is formed among the silicon substrate, the insulating layer and the grid through hole;

the emission sharp cone is arranged on the silicon substrate and positioned in the cavity of the insulating layer, and corresponds to the gate through hole; and (c) a second step of,

the coating layer is arranged on the silicon substrate, is positioned in the insulating layer cavity and completely covers the exposed silicon substrate in the insulating layer cavity;

the attached oxide layer is positioned between the coating layer and the emission tip cone and coated on the lower side surface of the emission tip cone; the upper side surface of the emission tip cone is exposed outside the incidental oxide layer.

Further, the coating layer is silicon dioxide obtained by thermal oxidation of the surface of the silicon substrate.

Further, the thickness of the coating layer is 30-100nm.

Further, the height of the upper side surface of the emission tip exposed outside the incidental oxide layer is 0.3 to 0.4 μm.

Further, the material of the emission tip cone is selected from high-melting-point and low-work-function pure metals, and is preferably W or Mo.

Furthermore, the diameter of the bottom of the emission sharp cone is 0.6-1 μm, the height is 0.8-2.2 μm, and the radius of curvature of the top is 20-50nm.

Further, the height of the upper side surface of the emission tip cone exposed outside the attached oxide layer is 15-50% of the overall height of the emission tip cone.

Furthermore, the material of the attached oxide layer is obtained by thermal oxidation of the surface of the lower side surface of the emission pointed cone.

Further, the silicon substrate is selected from a semiconductor process standard N-type doped silicon wafer.

Further, the silicon substrate has a resistivity of 0.005-5 Ω · cm.

Further, the insulating layer material is selected from silicon dioxide or silicon nitride.

Further, the thickness of the insulating layer material is 0.8-2 μm.

Further, the material of the grid electrode is selected from high-melting-point pure metals, preferably W or Mo; preferably, the thickness of the grid electrode is 100-200nm, and the diameter of the grid through hole is 0.8-1.2 μm.

In another aspect, the invention provides a method for preparing the Spindt cathode electron source, which comprises the following steps:

forming an insulating layer on the silicon substrate;

vacuum coating, forming a grid layer on the insulating layer;

etching the grid layer and the insulating layer in sequence until reaching the silicon substrate by photoetching to form a grid containing a grid through hole and an insulating layer cavity;

rotating the substrate, and performing vacuum coating on the surface of the grid only with a sacrificial layer by adopting a method of small surface inclination angle to reduce the through holes of the grid;

vacuum coating a layer of emission pointed cone material on the surface of the substrate vertically, and forming an emission pointed cone in the cavity;

removing the sacrificial layer and the emission pointed cone material deposited on the sacrificial layer;

rotating the substrate, and vacuum-coating a protective layer on the surface of the grid electrode and the upper side surface of the emission pointed cone only by adopting a method of large surface inclination angle;

thermally oxidizing the silicon substrate, wherein the coating layer is formed on the surface of the silicon substrate in the cavity, and the unprotected part of the emission sharp cone is subjected to oxidation to form an attached oxidation layer;

and corroding and removing the protective layer to expose the grid and the upper side surface of the emission pointed cone to obtain the Spindt cathode electron source.

In a further aspect, the present invention provides the use of a Spindt cathode electron source as described above in a device for vacuum electronics.

The invention has the following beneficial effects:

according to the Spindt cathode electron source provided by the invention, the coating layer completely covers the silicon substrate, so that a triple-joint point structure formed by the silicon substrate, the insulating layer and vacuum is eliminated, and unexpected electron emission generated by the structure point is avoided. Compared with the technology of blocking the electron along the network discharge transmission path or the arc discharge path in the early stage, the invention eliminates the electron emission source generating discharge and arc, can effectively prevent the electron source with the traditional structure from generating network discharge and space arc failure easily in the high-voltage and high-current working state, and effectively improves the working reliability of the electron source.

The manufacturing method of the Spindt cathode electron source provided by the invention implements two steps of manufacturing the emission pointed cone protective layer and manufacturing the substrate coating layer only after the traditional structure is completed, and the whole manufacturing method has simple and easy process flow and strong compatibility.

Drawings

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a Spindt cathode electron source showing a typical structure in the prior art.

Fig. 2 shows a schematic structural diagram of a Spindt cathode electron source with a multi-insulating layer corrugated sidewall structure in the prior art.

Fig. 3 shows a schematic structure diagram of a cathode electron source with a grid shielding layer Spindt in the prior art.

Fig. 4 shows a schematic structure diagram of a prior art Spindt cathode electron source with an emission tip cone insulating ring column.

Fig. 5 shows a schematic structure diagram of a Spindt cathode electron source with a masking layer in the prior art.

Fig. 6 shows a schematic of a substrate-coated Spindt cathode electron source according to the present invention.

Fig. 7 a-7 h show a flow chart of the fabrication of a substrate-coated Spindt cathode electron source of the present invention.

FIGS. 8a and 8b show photographs of a conventional aspect ratio Spindt cathode electron source with a substrate coating and a partially magnified photograph of the present invention.

FIGS. 9 a-9 c show scanning electron photographs of a high aspect ratio Spindt cathode electron source with a substrate coating for making an array of emission cones and finally a locally enlarged emission unit in a primary and secondary cycle according to the present invention.

FIGS. 10 a-10 b show emission performance test curves of a Spindt cathode electron source obtained in example 1 and example 2 of the present invention, respectively.

Detailed Description

In order to more clearly illustrate the present invention, the present invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.

In order to solve the problems that arc failure often occurs in Spindt cathode electron sources in the prior art in high-current applications, the reliability of devices is affected, and related technologies can not well overcome the defects, a specific embodiment of the present invention provides a Spindt cathode electron source, as shown in fig. 6, the Spindt cathode electron source has a structure including:

the silicon substrate 101, the insulating layer 201 and the grid electrode 301 are arranged from bottom to top in sequence, and an insulating layer cavity is formed among the silicon substrate 101, the insulating layer 201 and the grid electrode through hole;

an emission sharp cone 401 disposed on the silicon substrate 101 in the cavity of the insulating layer, the emission sharp cone 401 corresponding to the gate through hole; and the number of the first and second groups,

a coating layer 207 disposed on the silicon substrate 101, the coating layer 207 being disposed in the insulating layer cavity and completely covering the exposed silicon substrate 101 in the insulating layer cavity;

an attached oxide layer 402 between the coating layer 207 and the emission tip 401 and coating the lower side of the emission tip 401; the upper side of the emission tip 401 is exposed outside the incidental oxide layer 402.

In this embodiment, the diameter of the gate through hole is smaller than the diameter of the insulating layer cavity.

By constructing the coating layer 207, a three-joint point structure formed by the silicon substrate, the insulating layer and vacuum of the traditional Spindt cathode electron source is eliminated, and unexpected electron emission, and the resulting edge-to-edge discharge and space arc are avoided, so that the working reliability of the Spindt cathode electron source under high voltage and large current is improved.

The coating 207 functions to effectively mask the silicon substrate 101 and requires a certain thickness to withstand electric field breakdown. The coating layer 207 is positioned in a cavity formed by the silicon substrate 101, the emission tip cone 401 and the insulating layer 201, and completely covers the silicon substrate 101 to isolate vacuum, so that three bonding points formed by the silicon substrate, the insulating layer and the vacuum in the traditional structure are eliminated. The coating layer 207-is made of thermal oxide silicon dioxide by comprehensively considering the position and the process of the coating layer. The coating 207 is preferably 30-100nm thick for effective barrier formation.

In some preferred examples, the coating layer is silicon dioxide obtained by thermally oxidizing the surface of the silicon substrate.

The function of the emission tip is to emit electrons, and in a preferred example, the material of the emission tip 401 is selected from a high melting point, low work function pure metal to achieve efficient emission of electrons. For example, the material of the emission tip 401 may preferably be molybdenum (melting point 2620 ℃, work function 4.2 eV) or tungsten (melting point 3420 ℃, work function 4.5 eV), which can overcome the problems of large work function, chemical instability, poor conductivity and thermal conductivity, etc. compared with the silicon material commonly used in semiconductor process, thereby providing stable electron emission with large current.

The emission cusp 401 shape affects the surface electric field strength and thus the field electron emission. The optimized position of the height of the sharp cone is between the upper surface and the lower surface of the grid, and is determined by the thicknesses of the insulating layer 201 and the grid 301, and the range is preferably 0.8-2.2 mu m; the curvature radius of the top end of the pointed cone is determined by the height of the emission pointed cone 401, the diameter of the gate through hole 301 and the thickness of the bidirectional deposition film layer for manufacturing the pointed cone, and the optimization range is 20-50nm; the diameter of the bottom of the emission tip cone is determined by the diameter of the hole of the grid 301 and the deposition thickness of the inclined direction for manufacturing the tip cone, and the range is 0.6-1 mu m.

The principle of the Spindt cathode field emission electron source is that field electron emission exists only in a small area range at the top of the emission tip 401. Illustratively, the upper side of the emission tip is exposed outside the incidental oxide layer to a height of 15-50% of the overall height of the emission tip. Under the condition, the upper side surface (upper half part) of the emission sharp cone 401 keeps the original material characteristics, so that the Spindt cathode electron source keeps the required electron emission performance. The lower side (bottom half) of the emission tip 401 coated with the incidental oxide layer does not affect the electron source performance for positional reasons.

In still other preferred examples, the upper side of the emission tip is exposed to the incidental oxide layer at a height of 0.3 to 0.4 μm.

Illustratively, the material of the attached oxide layer is obtained by thermal oxidation of the surface of the lower side of the emission cone. The silicon substrate simultaneously plays a role of a bearing structure and is suitable for the characteristics of a micro-processing process, and a micro-electronic standard size silicon wafer is selected; the silicon substrate 101 plays a role in providing electron emission and cathode conduction, a semiconductor process standard N-type doped silicon wafer is preferably selected, and the resistivity is preferably 0.005-5 omega cm.

The insulating layer 201 functions to withstand high operating voltages between the silicon substrate 101 and the gate 301, requiring a high breakdown field strength and thickness of the insulating layer 201. The thickness of the insulating layer is determined according to the comprehensive influence of the breakdown field intensity, the diameter of the gate through hole and the shape of the emission sharp cone 401, and the preferable range is 0.8-2 mu m; the material of the insulating layer 201 is preferably selected from silicon dioxide or silicon nitride compatible with the process, more preferably, according to the process implementation method, when the thickness of the insulating layer 201 is 0.8-1.2 μm, the material is selected from thermal oxide silicon dioxide with better comprehensive performance, and when the thickness is 1.2-2 μm, the material is selected from chemical vapor deposition silicon nitride with better preparation process.

The grid electrode has the function of forming a strong electric field on the surface of the emission pointed cone 401 through loaded high voltage to extract electrons, and the grid electrode needs to bear structural strength and certain leakage heat power dissipation. The material of the gate 301 is selected from a high melting point metal material, and in a preferred example, the material of the gate 301 is selected from molybdenum or tungsten. The thickness of the gate 301, which is influenced by the structural strength and the micromachining process, is preferably 100 to 200nm according to the actual application. The diameter of the gate through hole, which affects the electric field intensity on the surface of the emission tip 401 and the electron emission performance under the applied voltage, is preferably 0.8-1.2 μm according to the practical application.

According to another embodiment of the invention, a method for preparing a Spindt cathode electron source is provided, which comprises the following steps:

1) An insulating layer 201 is formed on the silicon substrate 101.

The insulating layer material is preferably thermal oxidation silicon dioxide which is formed by directly oxidizing a silicon wafer material and has the best combination effect with the silicon wafer; however, the thermal oxidation growth of silicon dioxide is very slow after a certain thickness is exceeded, so that thermal oxidation silicon dioxide is selected when the insulating layer is thin, and silicon nitride prepared by a chemical vapor deposition method is selected after a certain thickness is exceeded. In one example, the insulating layer of thermal oxide silicon dioxide, thickness range 0.8-1.2 μm; in another example, the silicon dioxide insulating layer is chemically vapor deposited to a thickness in the range of 1.2-2 μm. The chemical vapor deposition method can also deposit silicon nitride material as the insulating layer.

2) And vacuum plating to form a gate layer 301 on the insulating layer 201, as shown in fig. 7 a.

The grid material is selected from high-melting-point metal materials, preferably W or Mo. The gate 301 is formed by a vacuum coating technique, preferably by a magnetron sputtering coating method, and the sputtering coating can obtain better film bonding force compared with other coating techniques. The thickness of the gate 301 can be adjusted according to the application, and is preferably 100-200nm.

3) The gate electrode 301 having the gate through-hole and the insulating layer cavity are formed by photolithography and etching the gate electrode layer 301 and the insulating layer 201 in sequence up to the silicon substrate 101, as shown in fig. 7 b.

The semiconductor technology is a conventional photoetching technology, is used for forming a masking layer of a grid through hole pattern, and can copy and transfer the pattern on the masking layer to a structural layer through a subsequent etching technology, wherein the structural layer is a grid layer.

Etching the grid electrode 301 through the pattern masking layer to form a grid electrode through hole, wherein the etching is preferably a reactive ion etching method; reactive ion etching is a highly anisotropic dry etching method that produces deep direction etching while substantially maintaining the width direction dimension. For the gate through hole etching of the invention, the etching in the depth direction of 301-gate 100-200nm can be completed, and the diameter of the gate through hole of 0.8-1.2 μm defined by the photoetching masking layer is maintained to be basically unchanged, so that an approximately steep side wall is obtained.

Etching the insulating layer through the gate through hole to form an insulating layer gate control cavity, wherein the etching is preferably a combination method of reactive ion etching and wet chemical etching; firstly, reactive ion etching is carried out to realize the basically complete depth etching of the insulating layer with the thickness of 0.8-2 mu m, and the transverse underetching is not generated in the process, thereby avoiding the infirm combination of the grid electrode suspension and the insulating layer; the wet chemical etching is used for rinsing and etching in a short time to ensure that the cavity of the insulating layer is etched until reaching the silicon substrate. The wet chemical etching method has a good etching selection ratio, so that the process can only basically aim at the insulating layer material without damaging the silicon substrate. The short wet chemical etching process produces a slight lateral undercutting, which results in insulating cavities having lateral dimensions slightly larger than the gate via diameter of 0.8-1.2 μm.

4) And (4) rotating the substrate, and performing vacuum plating on the surface of the grid electrode only by adopting a method of small surface inclination angle to form a sacrificial layer and reduce the through holes of the grid electrode, as shown in figure 7 c.

The purpose of depositing the sacrificial layer at a small inclination angle is to control the size of the bottom of the 4-emission pointed cone 401 by reducing the hole diameter of the gate 301; and the second is to completely wrap the gate 301, so that the film layer deposited for manufacturing the emission tip 401 in the subsequent process is effectively isolated from the gate 301.

The sacrificial layer 501 material is selected from materials having an etching selectivity with respect to the silicon substrate 101, the insulating layer 201, the gate electrodes 301 and 401, and the emission tip 401, and is preferably selected from metal oxide materials to facilitate the formation of a fine uniform film. In a preferred embodiment, selected from alumina.

The sacrificial layer 501 is selected from a low tilt deposition in order that the sacrificial layer 501 material is present only on the surface of the gate 301, including the top surface and the edges of the gate through hole, but not at a line of sight into the cavity formed by the silicon substrates 101 and 201-insulating layer. Preferably, the small tilt angle is selected in the range of 15-30 degrees from the gate plane.

The sacrificial layer 501 is vacuum-coated, preferably by vacuum evaporation from parallel beam incident. Parallel beam is incident to ensure the closing-up consistency of the grid of each unit on the Spindt cathode array; vacuum evaporation is carried out to ensure that the particles of the deposition material are fine so as to form smooth edges at the through holes of the grid electrode. In a preferred embodiment, the vacuum coating is selected from electron beam evaporation coating.

The thickness of the sacrificial layer 501 deposition is mainly determined by the reduction of the openings of the through holes of the gate 301, and the incident angle of the deposition material beam. Preferably, the opening diameter of the gate through hole is reduced to about 0.2 μm, and accordingly the sacrificial layer 501 is deposited to a thickness in the range of 100-200nm.

5) The surface is vacuum coated perpendicularly with a layer of emission tip material to form an emission tip 401 in the cavity, as shown in fig. 7 d.

The surface is deposited vertically for the purpose of forming an emission tip 401. A vertically deposited material partially deposited on the sacrificial layer 501 to form a deposited incidental layer 403; part of the material passes through the gate through hole reduced by the sacrificial layer 501 and is deposited on the silicon substrate 101, and the material deposited on the silicon substrate 101 is reduced continuously because the material continuously deposited in the process also shrinks the gate through hole, so that the conical emission tip 401 is formed.

The emission tip material is selected from high melting point, low work function pure metals, such as molybdenum or tungsten, for example, to achieve efficient emission of electrons. In another preferred example, a high melting point, low work function, conductive non-metallic material, such as zirconium carbide, may also be deposited on the surface of the emission tip 401 as an electron emission material.

Depositing an emission pointed cone material, namely selecting vacuum evaporation to ensure that the particles of the deposition material are fine and uniform so as to form an emission pointed cone with a compact structure and a smooth surface; the deposition requirement of high-melting point materials is met, and the emission tip cone material deposition is selected from electron beam evaporation coating.

The thickness of the deposited emission tip material is substantially (1-1.2): 1 ratio, depending on the desired height of the emission tip 401 to be formed. For the formation of a sharp taper with a height in the range of 0.8-1 μm, a deposition thickness of 1-1.2 μm is preferred. Considering that in the preferred structure, the small angle deposition of the sacrificial layer 501 has reduced the gate through hole to 0.6-1 μm, the height of the emission tip 401 formed by one deposition of material will not exceed 1 μm because the gate through hole will be reduced until completely closed, so that the deposition material can not enter the cavity to increase the emission tip 401. Thus, multiple emission tip material deposition processes are required for the formation of tips in the height range of 1-2.2 μm.

6) The sacrificial layer 501 and the emission tip material deposited on the sacrificial layer are removed as shown in fig. 7 e.

The material of the sacrificial layer 501 is selected from materials having etching selectivity with the silicon substrate 101, the insulating layer 201, the gate electrode 301, the emission tip 401 and the subsequent coating layer 207, so that when the material of the sacrificial layer is removed by etching, the etching solution does not damage other materials. In a preferred embodiment, the sacrificial layer is selected from alumina, and correspondingly, the etching solution is selected from hot phosphoric acid with the temperature of 120 ℃ or potassium hydroxide solution with the concentration of 20%.

7) The substrate is rotated and a protective layer 601 and 602 is vacuum coated on the surface of the gate electrode 301 and the emission tip 601 only by a method of large surface inclination, as shown in fig. 7 f.

The purpose of the large-tilt angle deposition protection layer is to form a temporary protection layer on the surfaces of the gate electrode 301 and the emission tip 401, so that the surface states of the gate electrode 301 and the emission tip 401 are not affected in the subsequent process of forming the coating layer 207.

The protective layer material, which is selected from materials having an etch selectivity with the silicon substrate 101, the insulating layer 201, the gate electrode 301 and the emission tip 401 and is not affected by the subsequent process of forming the coating layer 207, is preferably selected from metal oxide materials to facilitate the formation of a fine uniform film layer. In a preferred embodiment, selected from alumina.

The protective layer is selected from a large tilt angle deposition, relative to the small tilt angle deposition of the sacrificial layer described above, in order to present the protective layer material to the gate 301 surface, including the upper surface and the edges of the gate through hole, and the upper half surface of the emission tip 401; incidentally, the protective layer material may also be present in the upper half 601 of the sidewall of the insulating layer 201, which is not of practical use; the protective layer material should ensure that no line of sight angle reaches the surface of the silicon substrate 101 to avoid affecting the formation of the subsequent coating layer 207. Preferably, the large tilt angle is selected from the range of 30-60 degrees from the plane of the grid 301.

And (3) performing vacuum coating on the protective layer, preferably performing vacuum evaporation coating from parallel beam incidence. Parallel beam current is incident, and it is ensured that no disorderly particles enter the cavity to reach the surface of the silicon substrate 101 during dip angle evaporation; vacuum evaporation is carried out, and deposition material particles are enabled to be fine to form uniform protection. In a preferred embodiment, the vacuum coating is selected from electron beam evaporation coating.

The protective layer is deposited to a thickness preferably in the range of 50-100nm, based on the formation of a continuous dense thin film on the surfaces of the gate electrode 301 and the emission tip 401.

8) And thermally oxidizing the silicon substrate 101, forming the coating layer 207 on the surface of the silicon substrate 101 in the cavity, and additionally oxidizing the unprotected part of the emission tip cone 401 to form an additional oxidation layer 402, as shown in fig. 7 g.

The purpose of thermally oxidizing the silicon substrate 101 is to directly oxidize the silicon material, and the formed silicon dioxide forms a coating layer 207 on the surface of the silicon substrate 101 in the cavity to completely cover the silicon substrate, so as to eliminate triple bonding points formed by the silicon substrate 101, the insulating layer 201 and the vacuum in the cavity. The coating layer 207 is required to have a thickness to withstand electric field breakdown and to effectively form an electron emission barrier, and the thickness is preferably 30 to 100nm.

The silicon wafer can be naturally oxidized at normal temperature, but the thickness of the oxide layer is generally not more than 20nm and can not meet the requirement of the coating layer 207, so that a high-temperature oxidation method is used. Preferably, the thermal oxidation of the silicon substrate 101 uses a lower temperature of 700-800 deg.C, both to ensure that the desired oxide layer thickness is achieved, and not to unduly affect the bonding of the emission tip 401 and the silicon substrate 101. More preferably, the thermal oxidation may be dry thermal oxidation, which may result in a dense oxide layer at a slow rate, or steam thermal oxidation, which may result in a shorter process time at a fast rate.

9) And (5) removing the protective layers 601, 602 and 603 by etching to expose the grid electrode 301 and the upper side surface of the emission pointed cone 401, thereby obtaining the Spindt cathode electron source, as shown in fig. 7 h.

The materials of the emission tip cone protection layer 601 and the gate protection layer 602 are selected from materials having etching selection ratios with the silicon substrate 101, the insulating layer 201, the gate 301, the emission tip cone 401 and the coating layer 207, and when the materials of the protection layer are removed by etching, the etching solution can not damage other materials. In a preferred embodiment, the sacrificial layer material is selected from aluminum oxide, and correspondingly the etching solution is selected from hot phosphoric acid with the temperature of 120 ℃ or potassium hydroxide solution with the concentration of 20%.

The following description is given with reference to specific examples:

example 1

A Spindt cathode electron source with a substrate coating, the emission tip cone having a conventional aspect ratio of approximately 1:1, the structure of which is shown in fig. 6, comprises a silicon substrate 101, an emission tip 401, an attached oxide layer 402, a cladding layer 207, an insulating layer 201 and a gate 301, which are arranged in sequence from bottom to top. The manufacturing method comprises the following steps:

1) The silicon substrate 101 is an N-type doped silicon wafer with a crystal orientation of <100> and a resistivity of 0.01 omega cm, and is thermally oxidized at 1200 ℃ for 16 hours to grow a layer of silicon dioxide with a thickness of 0.8 mu m as an insulating layer 201.

2) Using a radio frequency magnetron sputtering vacuum coating method, sputtering for 3 minutes under 600W power, a layer of molybdenum with a thickness of 0.2 μm is deposited on the insulating layer 201 as the gate electrode 301, as shown in fig. 7 a.

3) Coating Shipley S1818 photoresist with the thickness of 1.4 mu m on the grid electrode 301, and forming a circular hole array with the diameter of 1 mu m on the photoresist layer by using ultraviolet lithography to serve as a masking layer; etching the grid 301 by using sulfur hexafluoride process atmosphere through the photoresist masking layer and an inductive coupling plasma method at the discharge power of 500W and the etching power of 300W for 4 minutes to obtain open holes (through holes) of the grid 301; etching the insulating layer 201 through the gate opening by an inductively coupled plasma method using a trifluoromethane process atmosphere with a discharge power of 500W and an etching power of 300w for 6 minutes to a depth of about 0.6 μm, and then continuing the etching using a BOE buffer (hydrofluoric acid: ammonium fluoride: water =3ml:6g: 10ml), completely etching the silicon oxide insulating layer for 5 minutes until the silicon substrate 101 while generating a certain degree of lateral undercutting; the remaining Shipley S1818 photoresist is removed to form the gate controlled cavity structure as shown in fig. 7 b.

4) The substrate rotates along the normal direction of a plane at 30RPM, meanwhile, in the direction of a plane included angle of 20 degrees, aluminum oxide is evaporated by an electron beam, the deposition is carried out for 10 minutes at the power of 2kW, and the aluminum oxide with the thickness of 200nm is formed on the plane of the grid electrode 301 to serve as a sacrificial layer 501; the sacrificial layer completely wraps the top surface and sides of the gate 301 and reduces the gate opening from 1 μm to 0.8 μm as shown in fig. 7 c.

5) The substrate is vertically evaporated by electron beam, the deposition material reaches the 101-silicon substrate 101 through the 301-gate 301 opening, and the emission tip 401 is gradually formed on the silicon substrate 101 as the gate opening is gradually reduced. 4kW power deposition for 40 minutes, depositing a molybdenum layer with a thickness of 1.1 μm, resulting in an emission cone 401 with a height of about 0.9 μm, while forming an additional deposition layer 403 with a thickness of 1.1 μm on the sacrificial layer 501 plane, as shown in FIG. 7 d.

6) The sacrificial layer 501 was etched using hot phosphoric acid of 85% concentration at 120 c for 1 minute to completely dissolve, and the incidental deposition layer 403 on the sacrificial layer 501 subsequently peeled off the substrate, leaving a conventional structure Spindt cathode electron source of the silicon substrate 101, emission tip 401, insulating layer 201 and gate 301, as shown in fig. 7 e.

7) The substrate rotates along the plane normal direction at 30RPM, aluminum oxide is evaporated by using an electron beam in the direction of a plane included angle of 45 degrees, deposition is carried out for 2 minutes at the power of 2kW, a gate protection layer 602 with the thickness of 50nm is formed on the plane of the gate 301, the upper surface and the side surface of an opening of the gate 301 are completely wrapped, an emission pointed cone protection layer 601 with the thickness of 50nm is formed on the upper half part of the emission pointed cone 401, and an electron emission part at the top end of the emission pointed cone 401 is completely wrapped; while an additional protective layer is formed on the sidewalls of the insulating layer 201 as shown in fig. 7 f.

8) Thermal oxidation was carried out, and dry oxidation was carried out at 800 ℃ for 5 hours to form a silicon dioxide 207-coating layer 207 with a thickness of 30nm in the cavity 101-the surface of the silicon substrate 101, while an oxidized surface attached oxide layer 402 was additionally formed on the unprotected portion of the lower half portion of the 401-emission cone, as shown in FIG. 7 g.

9) The emission tip protective layer 601, the gate protective layer 602 and the additional protective layer 603 were etched using hot phosphoric acid having a concentration of 85% and a temperature of 120 ℃ for 1 minute to be completely dissolved, and the gate electrode 301 and the upper half portion of the emission tip 401 were exposed, to obtain a substrate-coated Spindt cathode electron source, as shown in fig. 7 h.

The Spindt cathode electron source coated by the substrate is obtained through the process, the opening diameter of the grid of the emission array unit is 1 micrometer, the thickness of the insulating layer is 0.8 micrometer, the thickness of the grid is 0.2 micrometer, the height of the emission sharp cone is 0.9 micrometer, the curvature radius of the tip of the emission sharp cone is 50nm, and the thickness of the coating layer is 30nm, and scanning electronic photographs of the Spindt cathode electron source array and the local amplification emission unit are respectively shown in fig. 8a and 8 b.

Example 2

A substrate-coated Spindt cathode electron source emitting a cone with a conventional aspect ratio of approximately 1.5: the structure of the silicon substrate 1 is as shown in fig. 6, and comprises a silicon substrate 101, an emission tip 401, an attached oxide layer 402, a cladding layer 207, an insulating layer 201 and a gate 301 which are arranged in sequence from bottom to top. The method of manufacture comprises repeating example 1 with the following differences:

in step 1, the 201-insulating layer 201 is grown by chemical vapor deposition, and tetraethyl orthosilicate (TEOS) is decomposed for 120 minutes at 640 degrees to obtain a silicon dioxide insulating layer with a thickness of 1.2 μm.

In step 3, the insulating layer 201 is etched in a trifluoromethane process atmosphere, with process parameters unchanged, for 15 minutes to etch approximately 1 μm deep silicon dioxide.

The steps 4-6 need to be circularly performed twice: in the first cycle, the thickness of the molybdenum layer deposited in step 5 is 0.6 μm, and the height of the emission cone 401 is about 0.5 μm. Performing a second circulation, evaporating aluminum oxide by using the electron beam in the step 4, forming a sacrificial layer 501 with the thickness of 250nm on the plane of the gate 301, and reducing the opening of the gate from 1 micrometer to 0.7 micrometer; in step 5, the thickness of the deposited molybdenum layer is 1 μm, and 0.8 μm is superposed on the height of the emission tip 401, which is already 0.5 μm.

In step 8, the silicon substrate 101 is subjected to hydrothermal oxidation at 800 ℃ for 2 hours to form a silicon dioxide coating layer 207 with the thickness of 100nm on the surface of the silicon substrate in the cavity.

The Spindt cathode electron source coated by the substrate is obtained through the process, the diameter of the opening of the grid of the emission array unit is 1 micrometer, the thickness of the insulating layer is 1.2 micrometers, the thickness of the grid is 0.2 micrometer, the height of the emission sharp cone is 1.3 micrometers, the curvature radius of the tip of the emission sharp cone is 40nm, and the thickness of the coating layer is 100nm, and scanning electron photographs of the Spindt cathode electron source for manufacturing the emission sharp cone array and the final local amplification emission unit in a primary and secondary circulation mode are respectively shown in figures 9a, 9b and 9 c.

The verification results of the above embodiments show that the substrate-coated Spindt cathode electron source provided by the invention can effectively eliminate the undesirable electron emission generated at the junction of the silicon substrate, the insulating layer and the vacuum, thereby avoiding the problem of vacuum arc electron source failure caused by the undesirable electron emission.

Taking the structural parameters (mainly the diameter of a gate hole, the height of an emission pointed cone and the radius of curvature of the top end of the pointed cone) and materials of the embodiment as examples, the Spindt cathode electron source without a substrate coating structure generates a gate voltage threshold value of 70-80V for electron emission, the emission current increases with the increase of the gate voltage, but when the gate voltage exceeds 120-130V, obvious vacuum arc can be generated, and the cathode electron source is damaged. In the Spindt cathode electron source with the substrate coating structure in embodiment 1, the gate voltage threshold for generating electron emission is basically unchanged, and the Spindt cathode electron source can still stably work when the gate voltage exceeds 130V or more, so that the emission of a large current is reliably maintained. The verification of the embodiment 2 and other embodiments shows similar results, which show that the invention can better solve the problem of vacuum arc failure caused by undesired electrons at the three binding points of the Spindt cathode electron source.

FIG. 10 shows the emission performance test curves of two Spindt cathode electron sources with substrate coating structures, and the test environment vacuum degree is 2X 10 ^-7 Pa. The test adopts a three-pole test with an external anode, the external anode applies fixed high voltage, the grid voltage is gradually increased to test the emission current, and the total emission current comprises anode current and grid sectionAnd obtaining the current. FIG. 10a shows that a Spindt cathode comprising 11000 emitting unit arrays and 5 μm cell center-to-center spacing, obtained in accordance with example 1, starts to generate electron emission at a gate voltage of 70V, and obtains a stable emission current of 24.62mA at 148V, with a corresponding emission current density of 8.7A/cm ² . FIG. 10b shows that a Spindt cathode comprising 25 arrays of emissive cells and a cell center-to-center spacing of 5 μm obtained in example 2 starts to generate electron emission at a gate voltage of 80V, and obtains a stable emission current of 159 μ A at 160V, corresponding to an emission current density of 25.4A/cm ² 。

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims (10)

1. A Spindt cathode electron source, characterized in that the structure comprises:

the silicon substrate, the insulating layer and the grid are sequentially arranged from bottom to top, and an insulating layer cavity is formed among the silicon substrate, the insulating layer and the grid through hole;

an emission sharp cone arranged on the silicon substrate and positioned in the cavity of the insulating layer, wherein the emission sharp cone corresponds to the gate through hole; and the number of the first and second groups,

a coating layer arranged on the silicon substrate, wherein the coating layer is positioned in the insulating layer cavity and completely covers the silicon substrate exposed in the insulating layer cavity;

the attached oxide layer is positioned between the coating layer and the emission tip cone and coated on the lower side surface of the emission tip cone; the upper side surface of the emission tip cone is exposed outside the incidental oxide layer.

2. The Spindt cathode electron source of claim 1, wherein the coating layer is silicon dioxide obtained by thermal oxidation of the surface of the silicon substrate;

preferably, the coating layer has a thickness of 30-100nm.

3. A Spindt cathode electron source according to claim 1, wherein the upper side of the emission tip is exposed outside the incidental oxide layer to a height of 0.3-0.4 μm;

preferably, the material of the emission tip cone is selected from pure metals with high melting point and low work function, preferably W or Mo;

preferably, the diameter of the bottom of the emission sharp cone is 0.6-1 μm, the height is 0.8-2.2 μm, and the radius of curvature of the top is 20-50nm.

4. A Spindt cathode electron source according to claim 1, wherein the upper side of the emission tip is exposed outside the incidental oxide layer to a height of 15-50% of the overall height of the emission tip.

5. A Spindt cathode electron source according to claim 1, wherein the incidental oxide layer is thermally oxidised from the surface of the underside of the emission cusp.

6. The Spindt cathode electron source of claim 1, wherein the silicon substrate is selected from a semiconductor process standard N-type doped silicon wafer; preferably, the silicon substrate has a resistivity of 0.005 to 5 Ω · cm.

7. A Spindt cathode electron source according to claim 1, wherein the insulating layer material is selected from silicon dioxide or silicon nitride; preferably, the thickness of the insulating layer material is 0.8-2 μm.

8. A Spindt cathode electron source according to claim 1, wherein the material of the grid is selected from a high melting point pure metal, preferably W or Mo; preferably, the thickness of the grid electrode is 100-200nm, and the diameter of the grid through hole is 0.8-1.2 μm.

9. A method of producing a Spindt cathode electron source according to any of claims 1 to 8, comprising the steps of:

forming an insulating layer on the silicon substrate;

vacuum coating, forming a grid layer on the insulating layer;

etching the grid layer and the insulating layer in sequence until reaching the silicon substrate by photoetching to form a grid containing a grid through hole and an insulating layer cavity;

rotating the substrate, and performing vacuum coating on the surface of the grid only by adopting a method with a small surface inclination angle to form a sacrificial layer and reduce the through holes of the grid;

vacuum coating a layer of emission pointed cone material on the surface of the hollow cavity in a vertical manner to form an emission pointed cone in the hollow cavity;

removing the sacrificial layer and the emission pointed cone material deposited on the sacrificial layer;

rotating the substrate, and performing vacuum coating on the surface of the grid and the upper side surface of the emission pointed cone only by adopting a method of large surface inclination angle to form a protective layer;

thermally oxidizing the silicon substrate, wherein the coating layer is formed on the surface of the silicon substrate in the cavity, and the unprotected part of the emission sharp cone is subjected to oxidation to form an attached oxidation layer;

and corroding and removing the protective layer to expose the grid and the upper side surface of the emission pointed cone to obtain the Spindt cathode electron source.

10. Use of a Spindt cathode electron source according to any of the claims 1-8 in a device for vacuum electronics.

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