CN115483212A

CN115483212A - Semiconductor device with contact plug

Info

Publication number: CN115483212A
Application number: CN202210386239.1A
Authority: CN
Inventors: 崔祐荣; 吴周城; 黄有商
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2021-06-14
Filing date: 2022-04-13
Publication date: 2022-12-16
Also published as: US20220399343A1; US11785763B2; US20240008260A1; TW202249257A; KR20220167542A

Abstract

A semiconductor device, comprising: a substrate including a cell region having a first active region and a peripheral circuit region having a second active region; a direct contact contacting the first active region in the cell region; a bit line structure disposed on the direct contact; a capacitor structure electrically connected to the first active region; a gate structure disposed on the second active region in the peripheral circuit region; a lower wiring layer disposed adjacent to the gate structure and electrically connected to the second active region; an upper wiring layer disposed on the lower wiring layer; a wiring insulating layer disposed between the lower wiring layer and the upper wiring layer; and an upper contact plug connected to at least one of the lower wiring layer and the upper wiring layer and extending through the wiring insulating layer.

Description

Semiconductor device with contact plug

Technical Field

Exemplary embodiments of the present disclosure relate to a semiconductor device having a contact plug.

Background

The size of such semiconductor devices is being scaled down in accordance with the demand for high integration and miniaturization of the semiconductor devices. Therefore, a semiconductor memory device used in an electronic apparatus also requires a high integration degree, and therefore, the design rule of the constituent elements of the semiconductor memory device is reduced. For example, there is a need for a technique for reducing the size of a device by arranging wirings in a narrow space in a core/peripheral region.

Disclosure of Invention

Exemplary embodiments of the present disclosure provide an upper wiring layer and an upper contact plug.

The semiconductor device according to an exemplary embodiment of the present disclosure may include: a substrate extending in a first direction and a second direction perpendicular to the first direction and including a cell region having a first active region and a peripheral circuit region having a second active region; a direct contact contacting the first active region in the cell region; a bit line structure disposed on the direct contact; a capacitor structure electrically connected to the first active region; a gate structure disposed on the second active region in the peripheral circuit region; a lower wiring layer disposed adjacent to the gate structure and electrically connected to the second active region; an upper wiring layer disposed on the lower wiring layer; a wiring insulating layer disposed between the lower wiring layer and the upper wiring layer; and an upper contact plug connected to at least one of the lower wiring layer and the upper wiring layer and extending through the wiring insulating layer in a third direction perpendicular to the first direction and the second direction.

The semiconductor device according to an exemplary embodiment of the present disclosure may include: a substrate extending in a first direction and a second direction perpendicular to the first direction and including a cell region having a first active region and a peripheral circuit region having a second active region; a direct contact contacting the first active region in the cell region; a bit line structure disposed on the direct contact; a capacitor structure electrically connected to the first active region; a board layer covering the capacitor structure; a gate structure disposed on the second active region in the peripheral circuit region; a lower wiring layer disposed adjacent to the gate structure and electrically connected to the second active region; an upper wiring layer disposed on the lower wiring layer; a wiring insulating layer provided between the lower wiring layer and the upper wiring layer; and an upper contact plug connected to at least one of the lower wiring layer and the upper wiring layer and extending through the wiring insulating layer in a third direction perpendicular to the first direction and the second direction. The board layer may include the same material as the upper wiring layer.

The semiconductor device according to an exemplary embodiment of the present disclosure may include: a substrate extending in a first direction and a second direction perpendicular to the first direction and including a cell region having a first active region and a peripheral circuit region having a second active region; a direct contact contacting the first active region in the cell region; a bit line structure disposed on the direct contact; a capacitor structure electrically connected to the first active region, the capacitor structure including a lower electrode, a capacitor dielectric layer covering the lower electrode, and an upper electrode covering the capacitor dielectric layer; a sheet layer covering the upper electrode; a capacitor contact plug connected to the board layer; a gate structure disposed on the second active region in the peripheral circuit region; a lower wiring layer disposed adjacent to the gate structure and electrically connected to the second active region; an upper wiring layer disposed on the lower wiring layer; a wiring insulating layer provided between the lower wiring layer and the upper wiring layer; and an upper contact plug connected to at least one of the lower wiring layer and the upper wiring layer and extending through the wiring insulating layer in a third direction perpendicular to the first direction and the second direction.

Drawings

The above and other objects, features and advantages of the present inventive concept will become more apparent to those skilled in the art from the following detailed description, which is to be considered with reference to the accompanying drawings.

Fig. 1 is a plan view of a semiconductor device according to an example embodiment of the inventive concepts.

Fig. 2 is a vertical cross-sectional view of the semiconductor device taken along lines I-I 'and II-II' shown in fig. 1.

Fig. 3 is an enlarged view of the semiconductor device shown in fig. 2.

Fig. 4 to 7 are vertical sectional views of a semiconductor device according to example embodiments of the inventive concepts.

Fig. 8 is a layout of a wiring layer according to an example embodiment of the inventive concepts.

Fig. 9 to 27 are a plan view and a vertical sectional view illustrating a process sequence according to a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept.

Fig. 28 and 29 are vertical sectional views of a semiconductor device according to example embodiments of the inventive concepts.

Detailed Description

Fig. 1 is a plan view of a semiconductor device according to an example embodiment of the inventive concepts. Fig. 2 is a vertical cross-sectional view of the semiconductor device taken along lines I-I 'and II-II' shown in fig. 1.

Referring to fig. 1 and 2, the semiconductor device 100 may include a substrate 102, a gate electrode WL, a bit line structure BLS, a gate structure GS, an insulation spacer 132, a buried contact BC, a landing pad LP, a lower contact plug CL, a lower wiring layer LL, a lower electrode 162, a capacitor dielectric layer 164, an upper electrode 166, a wiring insulation layer IL, an upper wiring layer LU, and a first upper contact plug CU1.

The substrate 102 may include a cell area MCA, an interface area IA, and a peripheral circuit area CPA. The cell area MCA may denote an area in which memory cells of the DRAM device are disposed. The interface area IA may be disposed between the cell area MCA and the peripheral circuit area CPA while surrounding the cell area MCA. The peripheral circuit area CPA may be a core/peripheral area. The substrate 102 may include or may be formed of a semiconductor material. For example, the substrate 102 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate.

The substrate 102 may include a first active region AR1, a second active region AR2, an element isolation layer 104, and an area isolation layer 106. The element isolation layer 104 may be an insulating layer extending downward (i.e., a longitudinal direction in a direction perpendicular to the x direction and the y direction) from the upper surface of the substrate 102, and may define a first active region AR1 in the cell area MCA. For example, the active regions AR1 may respectively correspond to portions of the upper surface of the substrate 102 surrounded by the element isolation layer 104. The first active regions AR1 may have the form of stripes having a shorter axis and a longer axis when viewed in a plan view, and may be spaced apart from each other. The element isolation layer 104 may define a second active region AR2 in the peripheral circuit region CPA. An area isolation layer 106 may be disposed in interface area IA. The region isolation layer 106 may electrically insulate the first active region AR1 from a portion of the substrate 102 in the interface region IA. An item, layer, or portion of an item or layer described as extending "longitudinally" in a particular direction has a length in that particular direction and a width perpendicular to that direction, where the length is greater than the width.

The gate electrodes WL extend in the x direction while being spaced apart from each other in the y direction when viewed in a plan view. In addition, the gate electrode WL may cross the first active region AR1. For example, two gate electrodes WL may cross one first active region AR1. The gate electrodes WL may be buried in the substrate 102, and may be respectively disposed in trenches formed in the substrate 102, for example. The upper surface of the gate electrode WL may be coplanar with the upper surfaces of the element isolation layer 104 and the region isolation layer 106. Terms such as "identical," "equal," "planar," or "coplanar," as used herein, include identical or nearly identical, including variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to emphasize such meaning unless context or other statement indicates otherwise.

The semiconductor device 100 may further include a buffer layer 110 between the substrate 102 and the bit line structure BLS. The buffer layer 110 may cover upper surfaces of the element isolation layer 104 and the area isolation layer 106. In an embodiment, the buffer layer 110 may include silicon nitride or may be formed of silicon nitride.

The bit line structures BLS extend in the y-direction while being spaced apart from each other in the x-direction when viewed in a plan view. The bitline structure BLS may have the form of a bar extending in the y-direction. The bit line structure BLS may include a first conductive layer 112C, a second conductive layer 114C, a third conductive layer 116C, a first capping layer 118C, an insulating pad 122, and a second capping layer 130C sequentially stacked on the buffer layer 110 when viewed in a cross-sectional view. The first conductive layer 112C, the second conductive layer 114C, the third conductive layer 116C, and the first capping layer 118C may extend in the y direction and may have substantially the same width when viewed in a cross-sectional view. The insulating liner 122 may cover the first cover layer 118C in the cell area MCA, and may extend to the interface area IA and the peripheral circuit area CPA. For example, the insulating liner 122 may cover the upper surface of the substrate 102 and the upper surface of the area isolation layer 106. The second cover layer 130C may cover the insulating liner 122 in the cell area MCA. The second cover layer 130 may be disposed at the same level as the second cover layer 130C, and may extend to the interface area IA and the peripheral circuit area CPA.

The first conductive layer 112C may include or may be formed of polysilicon, and each of the second and third

conductive layers

114C and 116C may include or may be formed of titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicide, or a combination thereof. The first capping layer 118C, the insulation pad 122, and the second capping layer 130C may include or may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the first capping layer 118C, the insulating liner 122, and the second capping layer 130C may include silicon nitride or may be formed of silicon nitride.

The buffer layer 110, the first conductive layer 112C, the second conductive layer 114C, the third conductive layer 116C, and the first capping layer 118C may further extend to the interface area IA. For example, the buffer layer 110, the first conductive layer 112C, the second conductive layer 114C, the third conductive layer 116C, and the end portion of the first capping layer 118C may be disposed on the area isolation layer 106.

The semiconductor device 100 may further include a direct contact DC disposed under the bit line structure BLS at a portion of the bit line structure BLS contacting the first active region AR1. For example, the direct contact DC may fill a recess formed at the upper surface of the substrate 102. The direct contact DC may contact a middle portion of the active region when viewed in a plan view. The upper surface directly contacting the DC may be disposed at the same level as the upper surface of the first conductive layer 112C. The direct contact DC may electrically connect the first active region AR1 to the bit line structure BLS. For example, the direct contact DC may extend through the first conductive layer 112C of the bit line structure BLS and may be electrically connected to the second conductive layer 114C and the third conductive layer 116C. The direct contact DC may include or may be formed of polysilicon.

The gate structure GS may be disposed on the second active region AR2 in the peripheral circuit region CPA. Although not shown, source/drain regions may be disposed at the upper surface of the second active region AR2 while being adjacent to the gate structure GS. The gate structure GS may include a gate dielectric layer 111, a first conductive layer 112P, a second conductive layer 114P, a third conductive layer 116P, and a first capping layer 118P, which are sequentially stacked. The first conductive layer 112P, the second conductive layer 114P, the third conductive layer 116P, and the first capping layer 118P may include the same material as the first conductive layer 112C, the second conductive layer 114C, the third conductive layer 116C, and the first capping layer 118C, respectively.

Semiconductor device 100 may also include edge spacers 120C and gate spacers 120P. The edge spacer 120C may cover the ends of the buffer layer 110, the first conductive layer 112C, the second conductive layer 114C, the third conductive layer 116C, and the first capping layer 118C. Edge spacers 120C may be disposed in the interface region IA and, for example, may be disposed on the region isolation layer 106. The edge spacer 120C may be covered by an insulating liner 122 extending from the cell area MCA.

The gate spacer 120P may cover a side surface of the gate structure GS. For example, the gate spacer 120P may surround the gate structure GS when viewed in a plan view. The gate structure GS and the gate spacer 120P may be covered by an insulation liner 122 extending from the cell region MCA. The gate spacer 120P may include the same material as the edge spacer 120C. For example, the edge spacers 120C and the gate spacers 120P may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The semiconductor device 100 may further include an underlying interlayer insulating layer 124. The lower interlayer insulating layer 124 may be disposed on the insulating pad 122 in the interface area IA and the peripheral circuit area CPA, and may contact the lower surface of the second cover layer 130. In addition, an underlying interlayer insulating layer 124 may be disposed at side surfaces of the edge spacer 120C and the gate spacer 120P. An upper surface of the lower interlayer insulating layer 124 may be coplanar with an upper surface of the insulating liner 122 in the cell area MCA. The lower interlayer insulating layer 124 may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The insulating spacers 132 may be disposed at opposite side surfaces of the bit line structure BLS, respectively, and may extend in the y-direction. A portion of the insulating spacer 132 may extend into the recess of the substrate 102 and may cover the side surface that directly contacts the DC. The insulating spacer 132 may be composed of a single layer or a plurality of layers.

The buried contacts BC may be disposed between the bit line structures BLS. An upper surface of the buried contact BC may be disposed at a lower level than an upper surface of the second capping layer 130C, and a lower portion of the buried contact BC may extend into the substrate 102. For example, the lower end of the buried contact BC may be disposed at a lower level than the upper surface of the substrate 102, and may contact the first active region AR1. The semiconductor device 100 may further include fence insulating layers (not shown) alternately arranged with the buried contacts BC in the y direction when viewed in a plan view. The fence insulating layer may overlap the gate electrode WL. The buried contact BC may include or may be formed of polysilicon.

Landing pad LP may be disposed on bit line structure BLS and may contact buried contact BC. The landing pad LP may include a barrier pattern 151 and a conductive pattern 153. The barrier pattern 151 may be conformally formed along the upper surface of the bit line structure BLS and the upper surface of the buried contact BC, and the conductive pattern 153 may be disposed on the barrier pattern 151. For example, the lower surface of the conductive pattern 153 may be disposed at a lower level than the upper surface of the second cover layer 130C, and may correspond to the buried contact BC. The upper surface of the landing pad LP may be disposed at a higher level than the second cover layer 130C. The landing pad LP may be electrically connected to the active region via the buried contact BC.

Semiconductor device 100 may further include an insulating structure 155 disposed between landing pads LP. The insulating structure 155 may electrically insulate the landing pads LP from each other. The upper surface of the insulating structure 155 may be coplanar with the upper surface of the landing pad LP. In an embodiment, the landing pad LP may include or may be formed of tungsten, and the insulating structure 155 may include or may be formed of silicon oxide. The barrier pattern 151 and the conductive pattern 153 falling on the pad LP may extend to the interface area IA. For example, the barrier patterns 151 and the conductive patterns 153 may be disposed on the second cover layer 130 in the interface area IA.

The lower contact plug CL and the lower wiring layer LL may be disposed adjacent to the gate structure GS in the peripheral circuit region CPA. The lower contact plug CL may contact the second active region AR2 while extending through the lower interlayer insulating layer 124 and the second capping layer 130. The lower wiring layer LL may be disposed on the lower contact plug CL and may be electrically connected to the second active region AR2 via the lower contact plug CL. An upper surface of the lower wiring layer LL may be disposed at the same level as an upper surface of the landing pad LP, and the lower contact plug CL and the lower wiring layer LL may include the same material as the landing pad LP. For example, the lower contact plug CL and the lower wiring layer LL may include a conductive layer 152 and a barrier layer 150 surrounding a lower surface of the conductive layer 152. The lower contact plug CL may be continuous over the lower wiring layer LL material. For example, the barrier layer 150 and the conductive layer 152 constituting the lower contact plug CL may be continuous with the barrier layer 150 and the conductive layer 152 constituting the lower wiring layer LL in material. In an embodiment, the lower wiring layer LL may have the form of a line extending in a horizontal direction or the form of islands spaced apart from each other. The insulation structure 155 may electrically insulate the lower wiring layers LL from each other. As used herein, the term "materially continuous" may refer to structures, patterns, and/or layers formed simultaneously and from the same material, without interruption of the continuity of the material from which they are formed. As one example, a "continuous-on-material" structure, pattern, and/or layer may be a homogenous, monolithic structure.

The semiconductor device 100 may further include an etch stop layer 160 disposed on the landing pad LP, the insulating structure 155, and the lower wiring layer LL. The wiring insulating layer IL may be disposed on the etch stop layer 160 in the interface area IA and the peripheral circuit area CPA. The wiring insulating layer IL may include a groove at an upper surface thereof. In one embodiment, the wiring insulating layer IL may further extend to the cell area MCA. The etch stop layer 160 and the wiring insulating layer IL may include silicon nitride or may be formed of silicon nitride.

The capacitor structure of the semiconductor device 100 may be disposed on the landing pad LP in the cell area MCA. The capacitor structure may be comprised of a lower electrode 162, a capacitor dielectric layer 164, and an upper electrode 166. The lower electrodes 162 may be disposed to contact corresponding ones of the landing pads LP while respectively extending through the etch stop layer 160, and the capacitor dielectric layer 164 may be conformally disposed along the insulating structure 155 and the lower electrodes 162. An upper electrode 166 may be disposed on the capacitor dielectric layer 164. In an embodiment, the capacitor dielectric layer 164 and the upper electrode 166 may partially cover the wiring insulating layer IL.

The semiconductor device 100 may further include a first support S1 connected to the lower electrode 162 while extending in the horizontal direction and a second support S2 on the first support S1. The first and second supports S1 and S2 may prevent the lower electrode 162 from collapsing, and may be covered by the capacitor dielectric layer 164. The first and second supports S1 and S2 may include silicon nitride or may be formed of silicon nitride.

The semiconductor device 100 may further include a dummy electrode 163 extending in the vertical direction while being supported by the first and second supports S1 and S2. The dummy electrode 163 may be the lower electrode 162 closest to the peripheral circuit area CPA among the lower electrodes 162. In one embodiment, the dummy electrode 163 may contact an upper surface of the wiring insulating layer IL, and may be covered by the capacitor dielectric layer 164. The dummy electrode 163 may include the same material as the lower electrode 162.

The semiconductor device 100 may further include a plate layer 170 covering the upper electrode 166. The plate layer 170 may cover the upper surface and the side surfaces of the upper electrode 166 in the cell area MCA. In one embodiment, the board layer 170 may partially cover an upper surface of the wiring insulating layer IL. For example, the plate layer 170 may include a first horizontal portion 170a extending in a horizontal direction while covering the upper surface of the upper electrode 166, a vertical portion 170b extending in a vertical direction while covering the side surface of the upper electrode 166, and a second horizontal portion 170c extending in a horizontal direction while covering the upper surface of the wiring insulating layer IL. In an embodiment, the second horizontal portion 170c may be omitted. The plate layer 170 may include a conductive material, and may be electrically connected to the upper electrode 166. For example, the plate layer 170 may include or may be formed of tungsten (W).

The upper wiring layer LU may be provided on the wiring insulating layer IL in the peripheral circuit region CPA. The upper wiring layer LU may be disposed at a lower level than the upper surface of the capacitor structure, for example, the upper surface of the upper wiring layer LU may be disposed at a lower level than the upper surface of the upper electrode 166. The lower surface of the upper wiring layer LU may be disposed at the same level as the lower surfaces of the vertical portion 170b and the second horizontal portion 170c of the board layer 170. The board layer 170 and the upper wiring layer LU may be formed by patterning a conductive layer covering the upper electrodes 166 and the wiring insulating layer IL in the cell area MCA, the interface area IA, and the peripheral circuit area CPA. Therefore, the upper wiring layer LU may include the same material as the board layer 170. The upper wiring layers LU may be disposed to be spaced apart from each other. In an embodiment, the upper wiring layer LU may have the form of a line extending in the horizontal direction or the form of islands spaced apart from each other.

The semiconductor device 100 may further include an upper insulating layer 172 covering the board layer 170 and the upper wiring layer LU and an upper interlayer insulating layer 174 covering the upper insulating layer 172. For example, the upper insulating layer 172 may cover the board layer 170 in the cell area MCA and may cover the upper wiring layer LU in the peripheral circuit area CPA. The upper interlayer insulating layer 174 may be disposed in the interface area IA and the peripheral circuit area CPA, and an upper surface of the upper interlayer insulating layer 174 may be coplanar with an upper surface of the upper insulating layer 172. The upper insulating layer 172 may include or may be formed of silicon oxynitride, and the upper interlayer insulating layer 174 may include or may be formed of silicon oxide.

The first upper contact plug CU1 may be connected to and in contact with the upper wiring layer LU while extending through the upper insulating layer 172 and the upper interlayer insulating layer 174 in the peripheral circuit region CPA. An upper surface of the first upper contact plug CU1 may be coplanar with an upper surface of the upper interlayer insulating layer 174. Further, the first upper contact plug CU1 may be connected to and in contact with the lower wiring layer LL while extending through the wiring insulation layer IL and the etch stop layer 160. The first upper contact plug CU1 may be electrically connected to the lower wiring layer LL and the upper wiring layer LU. The first upper contact plug CU1 may include or may be formed of a metal such as Ti, W, ni, co, or the like, or a metal nitride such as TiN, tiSiN, tiAlN, taN, taSiN, WN, or the like. It will be understood that when an element is referred to as being "connected" or "coupled" to or "on" another element, it can be directly connected or coupled to the other element or on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or "contacting" another element, there are no intervening elements present at the point of contact.

The semiconductor device 100 may further include a capacitor contact plug 178, the capacitor contact plug 178 being connected to the plate layer 170 while extending through the upper insulation layer 172 in the cell region MCA. The capacitor contact plug 178 may be electrically connected to the upper electrode 166 via the plate layer 170. An upper surface of the capacitor contact plug 178 may be coplanar with an upper surface of the upper insulating layer 172 and an upper surface of the upper interlayer insulating layer 174. The capacitor contact plug 178 may include the same material as the first upper contact plug CU1.

The semiconductor device 100 may further include an insulating layer 180, contact plugs 182 and 183, and

wiring patterns

184 and 185. An insulating layer 180 may be disposed on the upper insulating layer 172 and the upper interlayer insulating layer 174. The contact plugs 182 may be connected to the first upper contact plugs CU1, respectively. The wiring patterns 184 may be disposed on the insulating layer 180, and may be connected to the contact plugs 182, respectively. The contact plug 183 may be connected to the capacitor contact plug 178 in the cell area MCA. The wiring pattern 185 may be disposed on the insulating layer 180, and may be connected to the contact plug 183.

Fig. 3 is an enlarged view of the semiconductor device shown in fig. 2.

Referring to fig. 3, the first upper contact plug CU1 may include a lower portion CU1a, a middle portion CU1b, and an upper portion CU1c. For example, a portion of the first upper contact plug CU1 lower than the upper surface of the wiring insulation layer IL may be referred to as a lower portion CU1a, a portion of the first upper contact plug CU1 extending through the upper insulation layer 172 and the upper wiring layer LU may be referred to as a middle portion CU1b, and a portion of the first upper contact plug CU1 disposed above the middle portion CU1b may be referred to as an upper portion CU1c. In an embodiment, the horizontal width of the middle portion CU1b may be smaller than the horizontal width of the upper portion CU1c, and the horizontal width of the lower portion CU1a may be smaller than the horizontal width of the middle portion CU1 b. Of course, the exemplary embodiments of the present disclosure are not limited to the above conditions, and in an embodiment, the horizontal widths of the lower portion CU1a, the middle portion CU1b, and the upper portion CU1c may be substantially equal. In another embodiment, the horizontal width of the middle portion CU1b may be greater than the horizontal width of the upper portion CU1c, and the horizontal width of the lower portion CU1a may be greater than the horizontal width of the middle portion CU1 b. In another embodiment, the side surface of the first upper contact plug CU1 may not have a step, and may have a tapered shape having a width gradually decreasing as the first upper contact plug CU1 extends from the upper portion CU1c to the lower portion CU1 a.

Referring to fig. 4, the semiconductor device 200 may further include second and third upper contact plugs CU2 and CU3 in addition to the first upper contact plug CU1. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In an embodiment, the second upper contact plug CU2 may be connected to and in contact with the lower wiring layer LL, and may not be connected to and in contact with the upper wiring layer LU. For example, the second upper contact plug CU2 may not overlap the upper wiring layer LU in the vertical direction, and may be disposed to be spaced apart from the upper wiring layer LU in the horizontal direction. The second upper contact plug CU2 may include a lower portion CU2a, a middle portion CU2b, and an upper portion CU2c. The lower portion CU2a may extend completely through the wiring insulating layer IL and may extend partially through the upper interlayer insulating layer 174. That is, the upper end of the lower portion CU2a may be disposed at a higher level than the upper surface of the wiring insulation layer IL, and the side surface of the second upper contact plug CU2 may have a step at a higher level than the upper surface of the wiring insulation layer IL.

The third upper contact plug CU3 may not be connected to and not in contact with the lower wiring layer LL, and may be connected to and in contact with the upper wiring layer LU. In an embodiment, the lower surface of the third upper contact plug CU3 may be disposed at a higher level than the lower surface of the wiring insulation layer IL. For example, the lower surface of the third upper contact plug CU3 may contact the upper surface of the wiring insulation layer IL. The third upper contact plug CU3 may include a lower portion CU3a and an upper portion CU3b. The lower portion CU3a of the third upper contact plug CU3 may extend through the upper wiring layer LU and the upper insulating layer 172. The upper portion CU3b of the third upper contact plug CU3 may extend through the upper interlayer insulating layer 174. The upper wiring layer LU connected to the third upper contact plug CU3 may be connected to the first upper contact plug CU1, and thus may perform a wiring function. Similar to the first upper contact plug CU1, the second and third upper contact plugs CU2 and CU3 may include or may be formed of a metal such as Ti, W, ni, co, or the like, or a metal nitride such as TiN, tiSiN, tiAlN, taN, taSiN, WN, or the like. Ordinal numbers such as "first," "second," "third," etc. may be used merely as labels to certain elements, steps, etc. to distinguish them. Terms that are not described in the specification using "first", "second", and the like may be still referred to as "first" or "second" in the claims. Furthermore, terms referenced with a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

Referring to fig. 5, the semiconductor device 300 may include a second upper contact plug CU2 connected to the lower wiring layer LL. Fig. 5 may further include first and third upper contact plugs CU1 and CU3. The first and third upper contact plugs CU1 and CU3 shown in fig. 5 may be similar to the first and third upper contact plugs CU1 and CU3 shown in fig. 4. As shown in fig. 5, the second upper contact plug CU2 may include a lower portion CU2a, a middle portion CU2b, and an upper portion CU2c. In one embodiment, the upper end of the lower portion CU2a of the second upper contact plug CU2 may be disposed at the same level as the upper surface of the wiring insulation layer IL. For example, the side surface of the second upper contact plug CU2 may have a step at the same level as the upper surface of the wiring insulating layer IL.

Referring to fig. 6, the semiconductor device 400 may include a fourth upper contact plug CU4 connected to the upper wiring layer LU. Fig. 6 may further include first and second upper contact plugs CU1 and CU2. The first and second upper contact plugs CU1 and CU2 shown in fig. 6 may be similar to the first and second upper contact plugs CU1 and CU2 shown in fig. 4. As shown in fig. 6, the horizontal width of the fourth upper contact plug CU4 may be smaller than the horizontal widths of the first and second upper contact plugs CU1 and CU2. The fourth upper contact plug CU4 may not extend completely through the upper wiring layer LU. The fourth upper contact plug CU4 may not be connected to and contact the lower wiring layer LL, and may be connected to and contact the upper wiring layer LU. For example, the lower surface of the fourth upper contact plug CU4 may be disposed at a higher level than the upper surface of the wiring insulation layer IL. Similar to the first upper contact plug CU1, the fourth upper contact plug CU4 may include or may be formed of a metal such as Ti, W, ni, co, or the like, or a metal nitride such as TiN, tiSiN, tiAlN, taN, taSiN, WN, or the like.

Referring to fig. 7, the semiconductor device 500 may include a fifth upper contact plug CU5 connected to the gate structure GS. Fig. 7 may further include first and third upper contact plugs CU1 and CU3. The fifth upper contact plug CU5 may be connected to and in contact with the third conductive layer 116P while extending through the upper interlayer insulating layer 174, the wiring insulating layer IL, the etch stop layer 160, the insulating structure 155, the second capping layer 130, the insulating liner 122, and the first capping layer 118P. The fifth upper contact plug CU5 may be electrically insulated from the lower wiring layer LL and the upper wiring layer LU. For example, the insulating structure 155 may electrically insulate the fifth upper contact plug CU5 from the lower wiring layer LL, and the upper interlayer insulating layer 174 may electrically insulate the fifth upper contact plug CU5 from the upper wiring layer LU.

Referring to fig. 8, the semiconductor device 600 may include upper contact plugs CU1, CU2, and CU3 shown in fig. 5 to 7. Although not specifically shown, the semiconductor device 600 may further include upper contact plugs CU4 and CU5. For example, the semiconductor device 600 may include a first lower wiring layer LL1, a second lower wiring layer LL2, a third lower wiring layer LL3, a first upper wiring layer LU1, a second upper wiring layer LU2, a third upper wiring layer LU3, a fourth upper wiring layer LU4, a first upper contact plug CU1, a second upper contact plug CU2, and a third upper contact plug CU3. In an embodiment, the first lower wiring layer LL1, the second lower wiring layer LL2, and the third lower wiring layer LL3 may have the form of lines extending in the horizontal direction. The first, second, and third upper contact plugs CU1, CU2, and CU3 may have the form of lines extending in the vertical direction, and the fourth upper wiring layer LU4 may have the form of islands spaced apart from the remaining upper wiring layers LU.

The first upper wiring layer LU1 and the second lower wiring layer LL2 may be interconnected by the first upper contact plug CU1. Further, the first upper wiring layer LU1 may be connected to the wiring pattern 184 through the third upper contact plug CU3. Therefore, the first upper wiring layer LU1 can function as a wiring that electrically interconnects the second lower wiring layer LL2 and the wiring pattern 184. In an embodiment, a portion of the first upper contact plug CU1 connected to the first upper wiring layer LU1 higher than the upper surface of the first upper wiring layer LU1 may not be used as a wiring.

The second lower wiring layer LL2 may also be connected to the fourth upper wiring layer LU4 and the first upper contact plugs CU1, the first upper contact plugs CU1 interconnecting the second lower wiring layer LL2 and the fourth upper wiring layer LU 4. The second upper wiring layer LU2 and the first lower wiring layer LL1 may be interconnected by the first upper contact plug CU1. The second upper wiring layer LU2 may also be connected to the third upper contact plug CU3. The third upper wiring layer LU3 may be connected to the third upper contact plug CU3, and the third lower wiring layer LL3 may be connected to the second lower contact plug CL.

Referring to fig. 9, an element isolation layer 104 and an area isolation layer 106 may be formed at a substrate 102. The substrate 102 may include a cell area MCA, an interface area IA, and a peripheral circuit area CPA. The interface area IA may be disposed between the cell area MCA and the peripheral circuit area CPA while surrounding the cell area MCA. The element isolation layer 104 may be disposed in the cell area MCA and the peripheral circuit area CPA, and the area isolation layer 106 may be disposed in the interface area IA.

The element isolation layer 104 and the region isolation layer 106 may be formed by forming a trench at an upper surface of the substrate 102 and filling the trench with an insulating material. The first active region AR1 may be defined by the element isolation layer 104 in the cell area MCA, and the second active region AR2 may be defined by the element isolation layer 104 in the peripheral circuit area CPA. For example, the first active region AR1 and the second active region AR2 may correspond to portions of the upper surface of the substrate 102 surrounded by the element isolation layer 104. The first active regions AR1 may have the form of stripes having a shorter axis and a longer axis when viewed in a plan view, and may be spaced apart from each other. The element isolation layers 104 and the region isolation layers 106 may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The element isolation layer 104 and the region isolation layer 106 may be composed of a single layer or a plurality of layers. Although the element isolation layer 104 is illustrated as having the same depth as the element isolation layer 106, example embodiments of the present disclosure are not limited thereto. The horizontal width of the region isolation layer 106 may be larger than the horizontal width of the element isolation layer 104.

Although not shown in the sectional view, the gate electrode WL may be formed to intersect the active region in the cell region MCA. For example, the gate electrode WL may be formed by forming a trench extending in the x direction at the upper surface of the substrate 102 and forming an electrode material in the trench. The gate electrodes WL may be spaced apart from each other in the y direction. The gate electrode WL may include or may be formed of Ti, tiN, ta, taN, W, WN, tiSiN, WSiN, or a combination thereof.

In an embodiment, after forming the gate electrodes WL, impurity ions may be implanted into portions of the first active region AR1 of the substrate 102 at opposite sides of each gate electrode WL, thereby forming source and drain regions. In another embodiment, an impurity ion implantation process for forming the source and drain regions may be performed before the gate electrode WL is formed. In addition, an impurity ion implantation process for forming a source region and a drain region may also be performed in the second active region AR2.

Referring to fig. 10, a buffer layer 110, a first conductive material layer 112, a direct contact DC, a second conductive material layer 114, a third conductive material layer 116, and a first capping material layer 118 may be formed on the substrate 102 in the cell area MCA and the interface area IA. The buffer layer 110 may cover the element isolation layer 104, the area isolation layer 106, the first active region AR1, and the second active region AR2. The first conductive material layer 112 may cover the buffer layer 110. The buffer layer 110 may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. The first conductive material layer 112 may include or may be formed of polysilicon.

Thereafter, a groove may be formed at the upper surface of the substrate 102 through an anisotropic etching process. The direct contact DC may be formed by filling the groove with a conductive material and performing a planarization process. The upper surface of the direct contact DC may be coplanar with the upper surface of the first conductive material layer 112. The direct contact DC may be formed in the active region, and may contact the source region of the first active region AR1, for example. Further, the direct contact DC may extend through the buffer layer 110 and the first conductive material layer 112, and may fill the groove.

The second conductive material layer 114, the third conductive material layer 116, and the first capping material layer 118 may be sequentially stacked on the first conductive material layer 112 and the direct contact DC. The first, second, and third conductive material layers 112, 114, and 116 may constitute a bit line material layer BLp. The bit line material layer BLp may cover the cell area MCA, the interface area IA, and the peripheral circuit area CPA.

The direct contact DC may include or be formed of Si, ge, W, WN, co, ni, al, mo, ru, ti, tiN, ta, taN, cu, or combinations thereof. In some embodiments, the direct contact DC may include or may be formed of polysilicon. Each of the second and third conductive material layers 114 and 116 may include or be formed of TiN, tiSiN, W, tungsten silicide, or a combination thereof. The first cover material layer 118 may include silicon nitride or may be formed of silicon nitride.

The gate dielectric layer 111 may be formed on the second active region AR2 in the peripheral circuit region CPA. In an embodiment, the gate dielectric layer 111 may be formed by performing a thermal oxidation process on an upper surface of the second active region AR2, and may include silicon oxide or may be formed of silicon oxide. The first conductive material layer 112 may cover the element isolation layer 104 and the gate dielectric layer 111.

Referring to fig. 11, the buffer layer 110, the bit line material layer BLp, and the first capping material layer 118 may be partially etched. Since the first conductive material layer 112, the second conductive material layer 114, the third conductive material layer 116, and the first capping material layer 118 are etched, a first conductive layer 112C, a second conductive layer 114C, a third conductive layer 116C, and a first capping layer 118C may be formed, respectively. For example, the bit line material layer BLp may be partially etched, and an end surface of the bit line material layer BLp may be disposed on the region isolation layer 106 in the interface region IA.

In the peripheral circuit region CPA, the gate dielectric layer 111, the bit line material layer BLp, and the first cover material layer 118 may be etched, thereby forming the gate structure GS. Since the first conductive material layer 112, the second conductive material layer 114, the third conductive material layer 116, and the first capping material layer 118 are etched, a first conductive layer 112P, a second conductive layer 114P, a third conductive layer 116P, and a first capping layer 118P may be formed, respectively. The buffer layer 110, the first conductive layer 112P, the second conductive layer 114P, the third conductive layer 116P, and the first capping layer 118P may form a gate structure GS. The gate structure GS may be disposed adjacent to the source/drain region in the second active region AR2. For example, the source/drain regions may be disposed on opposite sides of the gate structure GS.

After the etching of the bit line material layer BLp, the edge spacer 120C and the gate spacer 120P may be formed. For example, edge spacers 120C and gate spacers 120P may be formed by: an insulating material is deposited such that the insulating material covers the substrate 102, the element isolation layer 104, the region isolation layer 106, and the etched bit line material layer BLp, and then the insulating material is etched through an anisotropic etching process. The edge spacer 102C may be disposed in the interface area IA, and may cover side surfaces of the buffer layer 110, the first conductive layer 112C, the second conductive layer 114C, the third conductive layer 116C, and the first capping layer 118C. The gate spacer 120P may be disposed in the peripheral circuit region CPA, and may cover side surfaces of the buffer layer 110, the first conductive layer 112P, the second conductive layer 114P, the third conductive layer 116P, and the first cover layer 118P.

The edge spacers 120C and the gate spacers 120P may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the edge spacers 120C and the gate spacers 120P may include or may be formed of silicon oxide.

Subsequently, an insulating material may be deposited, thereby forming the insulating liner 122. The insulating liner 122 may be conformally formed on the cell area MCA, the interface area IA, and the peripheral circuit area CPA. For example, the insulating liner 122 may cover the substrate 102, the first capping layer 118C, the edge spacer 120C, the gate structure GS, and the gate spacer 120P. In an embodiment, the insulating liner 122 may include silicon nitride or may be formed of silicon nitride.

Referring to fig. 12, a lower interlayer insulating layer 124 and a second capping layer 130 may be formed. The lower interlayer insulating layer 124 may be formed by depositing an insulating material on the insulating liner 122 and then performing a planarization process such that the upper surface of the insulating liner 122 is exposed. Although the upper surface of the lower interlayer insulating layer 124 may be coplanar with the upper surface of the insulating liner 122, example embodiments of the present disclosure are not limited thereto. In an embodiment, a portion of the insulation pad 122 on the first capping layer 118C may be removed by a planarization process, and an upper surface of the lower interlayer insulation layer 124 may be coplanar with an upper surface of the first capping layer 118C. The lower interlayer insulating layer 124 may include silicon oxide or may be formed of silicon oxide.

The second capping layer 130 may be formed on the insulating pad 122 and the lower interlayer insulating layer 124. The second capping layer 130 may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the second capping layer 130 may include silicon nitride or may be formed of silicon nitride.

Referring to fig. 13, the buffer layer 110, the first conductive layer 112C, the second conductive layer 114C, the third conductive layer 116C, the first capping layer 118C, and the second capping layer 130 may be etched to form a trench T extending in the y-direction, thereby forming a bit line structure BLS. The first conductive layer 112C, the second conductive layer 114C, the third conductive layer 116C, the first capping layer 118C, the insulating pad 122, and the second capping layer 130C may constitute a bit line structure BLS. The bit line structure BLS may have the form of a bar extending in the y direction.

After the bit line structure BLS is formed, an insulating spacer 132 may be formed at a side surface of the bit line structure BLS. The insulating spacers 132 may be formed by depositing an insulating material covering the inner walls of the trench T and the bit line structure BLS and then anisotropically etching the insulating material. The insulating spacer 132 may cover a side surface of the bit line structure BLS, and may also cover a side surface directly contacting the DC. The insulating spacer 132 may be composed of a single layer or a plurality of layers, and may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

After forming the insulating spacer 132, the buried contact BC may be formed at a side surface of the bit line structure BLS. The buried contact BC may be formed as follows: a sacrificial layer (not shown) extending in the y direction is formed while filling the trench T at the side surface of the bit line structure BLS, a fence insulating layer (not shown) is formed at a portion of the sacrificial layer overlapping the gate electrode WL in the vertical direction, the sacrificial layer is removed, and then a conductive material is deposited at the opposite side of the bit line structure BLS.

After the buried contact BC is formed, an etch-back process for etching an upper portion of the buried contact BC may be further performed. For example, the upper surface of the buried contact BC may be disposed at a lower level than the upper surface of the bit line structure BLS. The buried contact BC may extend into the substrate 102. For example, the lower end of the buried contact BC may be disposed at a lower level than the upper surface of the substrate 102, and may contact the drain region of the first active region AR1. The insulating spacer 132 may be disposed between the buried contact BC and the bit line structure BLS, and thus may electrically insulate the buried contact BC and the bit line structure BLS from each other. The buried contact BC may include or may be formed of polysilicon.

A first contact hole H1 exposing the second active region AR2 may be formed in the peripheral circuit region CPA. The first contact hole H1 may be formed by anisotropically etching the lower interlayer insulating layer 124 and the second capping layer 130, and may be formed adjacent to the gate structure GS.

Referring to fig. 14, a barrier layer 150 and a conductive layer 152 may be formed. A barrier layer 150 may be conformally formed on the resulting structure of fig. 13. For example, the barrier layer 150 may be formed along the bit line structure BLS, the trench T, the second capping layer 130, and the first contact hole H1. Conductive layer 152 can be deposited on barrier layer 150. In an embodiment, a process for forming a metal silicide layer on the buried contact BC may be further performed before forming the barrier layer 150.

The barrier layer 150 may include or be formed of a metal silicide such as cobalt silicide, nickel silicide, and manganese silicide. Conductive layer 152 may include or be formed from polysilicon, metal silicide, conductive metal nitride, or combinations thereof. In an embodiment, conductive layer 152 may include or may be formed of tungsten.

Referring to fig. 15, a landing pad LP, an insulating structure 155, a lower contact plug CL, a lower wiring layer LL, and an etch stop layer 160 may be formed. The barrier pattern 151 and the conductive pattern 153 may be formed by patterning the barrier layer 150 and the conductive layer 152 of fig. 14 in the cell area MCA, and may constitute the landing pad LP. The landing pad LP may be electrically connected to the first active region AR1 via the buried contact BC.

Insulating structure 155 may be formed by etching barrier layer 150 and conductive layer 152 of fig. 14 and then filling the etched portions of barrier layer 150 and conductive layer 152 with an insulating material. Insulating structure 155 may be disposed between adjacent ones of landing pads LP and may thus electrically insulate landing pads LP from each other. The upper surface of the insulating structure 155 may be coplanar with the upper surface of the landing pad LP. The insulating structure 155 may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The insulating structure 155 may also be disposed in the peripheral circuit region CPA. For example, since the insulating structure 155 is formed in the peripheral circuit region CPA, the lower contact plug CL and the lower wiring layer LL defined by the insulating structure 155 may be formed. The lower contact plug CL may contact the second active region AR2 while filling the first contact hole H1. The lower contact plug CL may include a conductive layer 152 and a barrier layer 150 covering a lower surface and a side surface of the conductive layer 152. The lower wiring layer LL may be disposed at an upper surface of the lower contact plug CL and may include a conductive layer 152 and a barrier layer 150 covering a lower surface of the conductive layer 152. The lower wiring layer LL may be continuous over the lower contact plug CL material. For example, the conductive layer 152 of the lower wiring layer LL and the conductive layer 152 of the lower contact plug CL may be materially continuous with each other, and the barrier layer 150 of the lower wiring layer LL and the barrier layer 150 of the lower contact plug CL may be materially continuous with each other. The upper surface of the lower wiring layer LL may be disposed at the same level as the upper surface of the landing pad LP and the upper surface of the insulating structure 155. Adjacent ones of the lower wiring layers LL may be electrically insulated from each other by an insulation structure 155. In an embodiment, the lower wiring layer LL may have the form of a line extending in a horizontal direction or the form of islands spaced apart from each other.

The etch stop layer 160 may be formed to extend along all of the cell area MCA, the interface area IA, and the peripheral circuit area CPA, and may cover an upper surface of the landing pad LP, the insulating structure 155, and the lower wiring layer LL. In an embodiment, the etch stop layer 160 may include or may be formed of SiBN.

Referring to fig. 16, a wiring insulating layer IL may be formed at an upper surface of the etch stop layer 160. The wiring insulating layer IL may be formed by depositing an insulating material covering the etch stop layer 160 and etching the insulating material such that a portion of the etch stop layer 160 corresponding to the landing pad LP in the cell area MCA is exposed (i.e., not covered by the wiring insulating layer IL). For example, the wiring insulating layer IL may be disposed in the interface area IA and the peripheral circuit area CPA. In one embodiment, the wiring insulating layer IL may be provided in the cell area MCA. The wiring insulating layer IL may include a material having an etch selectivity with respect to the etch stop layer 160. In an embodiment, the wiring insulating layer IL may include silicon nitride or may be formed of silicon nitride.

Referring to fig. 17, a first mold layer Ml, a first support S1, a second mold layer M2, and a second support S2 may be formed in the cell area MCA, the interface area IA, and the peripheral circuit area CPA. The first mold layer M1 may be formed by depositing an insulating material covering the etch stop layer 160 and the wiring insulating layer IL and then planarizing the insulating material. The first mold layer M1 and the second mold layer M2 may include a material having an etch selectivity with respect to the first support S1 and the second support S2. In an embodiment, the first and second mold layers M1 and M2 may include silicon oxide or may be formed of silicon oxide, and the first and second supports S1 and S2 may include silicon nitride or may be formed of silicon nitride.

Referring to fig. 18, the lower electrode 162 contacting the landing pad LP may be formed. The lower electrode 162 may be formed by forming a via hole vertically extending through the first mold layer M1, the first support S1, the second mold layer M2, and the second support S2 and then filling the via hole with a conductive material. In the case of forming the via hole, the etch stop layer 160 may be removed, and thus the landing pad LP may be exposed. The lower electrode 162 may be electrically connected to the buried contact BC via the landing pad LP.

In an embodiment, the forming of the lower electrode 162 may include forming a dummy electrode 163. The dummy electrode 163 may be defined by the outermost one of the lower electrodes 162. For example, the dummy electrode 163 may be the lower electrode 162 closest to the peripheral circuit area CPA among the lower electrodes 162. In one embodiment, the dummy electrode 163 may contact an upper surface of the wiring insulating layer IL. For example, the dummy electrode 163 may partially extend through the wiring insulating layer IL, and a lower surface of the dummy electrode 163 may be disposed at a higher level than a lower surface of the lower electrode 162. Although only one dummy electrode 163 is illustrated in fig. 18, exemplary embodiments of the present disclosure are not limited thereto. In one embodiment, a plurality of dummy electrodes 163 may be formed.

In one embodiment, the lower electrode 162 and the dummy electrode 163 may have a pillar shape, but are not limited thereto. In another embodiment, the lower electrode 162 and the dummy electrode 163 may have a cylindrical shape or a mixed shape of a columnar shape and a cylindrical shape. The lower electrode 162 may include or may be formed of a metal such as Ti, W, ni, co, or the like, or a metal nitride such as TiN, tiSiN, tiAlN, taN, taSiN, WN, or the like. In an embodiment, the lower electrode 162 may include TiN or may be formed of TiN.

Thereafter, the first and second supports S1 and S2 may be patterned. For example, a holder hole (not shown) may be formed through the first and second holders S1 and S2, and portions of the first and second holders S1 and S2 in the interface area IA and the peripheral circuit area CPA may be removed. After patterning the first and second supports S1 and S2, the first and second mold layers M1 and M2 may be removed. The first and second mold layers M1 and M2 may be removed by a wet etching process, and the first and second supports S1 and S2 having an etching selectivity with respect to the first and second mold layers M1 and M2 may not be removed. The first and second supports S1 and S2, which are not removed, may prevent collapse of the lower electrode 162.

Referring to fig. 19, a capacitor dielectric layer 164 and an upper electrode 166 may be formed. A capacitor dielectric layer 164 may be conformally formed on the resulting structure of fig. 18. For example, the capacitor dielectric layer 164 may cover the etch stop layer 160, the first and second supports S1 and S2, the wiring insulating layer IL, the lower electrode 162, and the dummy electrode 163. The capacitor dielectric layer 164 may include a metal oxide such as HfO ₂ 、ZrO ₂ 、Al ₂ O ₃ 、La ₂ O ₃ 、Ta ₂ O ₃ And TiO ₂ Dielectric material having perovskite structure such as SrTiO ₃ (STO)、BaTiO ₃ PZT and PLZT or combinations thereof, or can be made of a metal oxide such as HfO ₂ 、ZrO ₂ 、Al ₂ O ₃ 、La ₂ O ₃ 、Ta ₂ O ₃ And TiO ₂ Dielectric material having perovskite structure such as SrTiO ₃ (STO)、BaTiO ₃ PZT, PLZT or a combination thereof.

An upper electrode 166 may be formed on the capacitor dielectric layer 164. For example, the upper electrode 166 may fill the space between the lower electrodes 162. In addition, the upper electrode 166 may also be formed in the interface area IA and the peripheral circuit area CPA. The lower electrode 162, the capacitor dielectric layer 164, and the upper electrode 166 may constitute a capacitor structure of the semiconductor device. In one embodiment, the upper electrode 166 may include a silicon layer. For example, the upper electrode 166 may include a conductive material and SiGe overlying the conductive material. The conductive material may include or be formed of, for example, a metal such as Ti, W, ni, co, or the like, or a metal nitride such as TiN, tiSiN, tiAlN, taN, taSiN, WN, or the like.

Referring to fig. 20, the capacitor dielectric layer 164 and the upper electrode 166 may be partially etched. For example, portions of the capacitor dielectric layer 164 and the upper electrode 166 that cover the interface area IA and the peripheral circuit area CPA may be removed. In an embodiment, the capacitor dielectric layer 164 may not be removed.

Referring to fig. 21, a plate layer 170 may be formed on the wiring insulating layer IL and the upper electrode 166. The plate layer 170 may cover the upper electrode 166 in the cell area MCA while covering the wiring insulation layer IL in the interface area IA and the peripheral circuit area CPA. The plate layer 170 may be formed by a Physical Vapor Deposition (PVD) process. In the case of forming the plate layer 170, the barrier material forming process may be omitted, and thus, the plate layer 170 may contact the upper electrode 166 and the wiring insulating layer IL. In an embodiment, the plate layer 170 may include or may be formed of a metal such as Ti, W, ni, co, ru, etc., but is not limited thereto.

Referring to fig. 22, an upper insulating layer 172 may be formed on the board layer 170. The upper insulating layer 172 may cover the board layer 170 in the cell area MCA, the interface area IA, and the peripheral circuit area CPA. The upper insulating layer 172 may include or be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the upper insulating layer 172 may include silicon oxynitride or may be formed of silicon oxynitride.

Referring to fig. 23, the plate layer 170 and the upper insulating layer 172 may be patterned. For example, a portion of the plate layer 170 covers the upper electrode 166, and portions of the plate layer 170 extending in the horizontal direction on the wiring insulation layer IL may be separated from each other. The patterning process may include forming a hard mask such as a spin on hard mask (SOH), covering the upper insulating layer 172, patterning the hard mask using a photoresist, and performing anisotropic etching using the patterned hard mask as an etching mask. The patterned board layer 170 on the wiring insulating layer IL may be referred to as an upper wiring layer LU. The upper wiring of the upper wiring layer LU may be electrically insulated from the plate layer 170 covering the upper electrode 166. The upper wiring may have the form of a bar extending in a horizontal direction or the form of islands spaced apart from each other. In the patterning process, the wiring insulating layer IL may be partially etched, and thus, a groove may be formed at an upper surface of the wiring insulating layer IL. For example, a groove may be formed between the upper wiring layers LU.

As shown in fig. 23, the upper wiring layer LU may be formed by patterning the board layer 170, and may be used as a wiring. Since the upper wiring layer LU is used as a wiring, the degree of freedom in design can be increased, and the size of the peripheral circuit region CPA can be reduced.

Referring to fig. 24, an upper interlayer insulating layer 174 and an insulating layer 176 may be formed. The upper interlayer insulating layer 174 may be formed by depositing an insulating material covering the upper insulating layer 172 and then planarizing the insulating material such that an upper surface of the upper insulating layer 172 is exposed. The upper interlayer insulating layer 174 may cover the upper insulating layer 172 in the interface area IA and the peripheral circuit area CPA. The insulating layer 176 may cover the upper insulating layer 172 and the upper interlayer insulating layer 174. The upper interlayer insulating layer 174 and the insulating layer 176 may include or may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

Referring to fig. 25, second and third contact holes H2 and H3 extending through the upper interlayer insulating layer 174 and the insulating layer 176 may be formed. The second contact hole H2 may expose side surfaces of the upper wiring layer LU and the upper insulating layer 172 and an upper surface of the wiring insulating layer IL. The horizontal width of the second contact hole H2 at the upper wiring layer LU and the upper insulating layer 172 may be smaller than the horizontal width of the second contact hole H2 at the upper interlayer insulating layer 174. The formation of the second contact hole H2 may be performed by an anisotropic etching process using a hard mask exposing a portion of the insulating layer 176 corresponding to the second contact hole H2 as an etching mask. In an embodiment, the forming of the second contact hole H2 may further include etching the upper wiring layer LU by a wet etching process. In an embodiment, at least one of the second contact holes H2 may have a smaller horizontal width than the remaining second contact holes H2. For example, part of the second contact holes H2 may have a relatively small horizontal width, and may not extend completely through the upper wiring layer LU, as in the fourth upper contact plug CU4 shown in fig. 6.

The third contact hole H3 may expose the plate layer 170. In one embodiment, the horizontal width of the third contact hole H3 may be different from the horizontal width of the second contact hole H2. For example, the horizontal width of the third contact hole H3 may be smaller than the horizontal width of the second contact hole H2. The third contact hole H3 may be formed simultaneously with or separately from the second contact hole H2.

Referring to fig. 26, the second contact hole H2 may be further extended downward by an anisotropic etching process, and thus may extend through the wiring insulating layer IL and the etch stop layer 160, thereby exposing the lower wiring layer LL. The second contact hole H2 may expose both the lower wiring layer LL and the upper wiring layer LU, but is not limited thereto. In an embodiment, when the etching process is performed using a hard mask that prevents at least one of the second contact holes H2 from being exposed, a portion of the second contact hole H2 may not extend through the wiring insulating layer IL, as in the third upper contact plug CU3 shown in fig. 4.

Referring to fig. 27, a conductive material may fill the second and third contact holes H2 and H3, thereby forming the first upper contact plug CU1 and the capacitor contact plug 178. The conductive material may include or be formed of, for example, a metal such as Ti, W, ni, co, or the like, or a metal nitride such as TiN, tiSiN, tiAlN, taN, taSiN, WN, or the like. In an embodiment, the first upper contact plug CU1 and the capacitor contact plug 178 may include or may be formed of tungsten (W). After the first upper contact plug CU1 and the capacitor contact plug 178 are formed, the insulating layer 176 may be removed by a planarization process. An upper surface of a portion of the upper insulating layer 172 may be coplanar with an upper surface of the upper interlayer insulating layer 174.

Referring again to fig. 2, an insulating layer 180 may be formed on the upper insulating layer 172 and the upper interlayer insulating layer 174. Subsequently, the insulating layer 180 may be etched to expose the first upper contact plugs CU1 and the capacitor contact plugs 178, and then filling of a conductive material may be performed, thereby forming contact plugs 182 and 183 and

wiring patterns

184 and 185. The wiring pattern 184 may be electrically connected to the first upper contact plug CU1 via the contact plug 182. The wiring pattern 185 may be electrically connected to the upper electrode 166 and the plate layer 170 via a contact plug 183.

Referring to fig. 28, the semiconductor device 700 may include a wiring insulating layer IL between the lower wiring layer LL and the upper wiring layer LU. The wiring insulating layer IL may be disposed in the interface area IA and the peripheral circuit area CPA. In one embodiment, the wiring insulating layer IL may not contact the dummy electrode 163. For example, the wiring insulating layer IL may not overlap the dummy electrode 163 in the vertical direction and may be spaced apart from the dummy electrode 163 in the horizontal direction. The upper electrode 166 may be filled between the wiring insulating layer IL and the dummy electrode 163, and the wiring insulating layer IL may overlap the upper electrode 166 in a vertical direction. In an embodiment, the wiring insulating layer IL may not overlap the upper electrode 166 in a vertical direction and may be spaced apart from the upper electrode 166 in a horizontal direction.

Referring to fig. 29, the semiconductor device 800 may include a board layer 170, an upper wiring layer LU, and an upper interlayer insulating layer 174. In an embodiment, the upper insulating layer 172 of the semiconductor device 100 shown in fig. 2 may be omitted. The plate layer 170 and the upper wiring layer LU may contact the upper interlayer insulating layer 174.

According to the exemplary embodiments of the present disclosure, the semiconductor device may include the upper wiring layer on the lower wiring layer, and thus, a degree of freedom in designing the wiring may be enhanced and the size of the device may be reduced.

Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications may be made without departing from the scope of the present disclosure and without changing the essential features thereof. Accordingly, the above-described embodiments should be considered illustrative only and not for the purpose of limitation.

This application claims priority from korean patent application No. 10-2021-0076645, filed on korean intellectual property office at 14.6.2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising:

a substrate extending in a first direction and a second direction perpendicular to the first direction and including a cell region having a first active region and a peripheral circuit region having a second active region;

a direct contact contacting the first active region in the cell region;

a bit line structure disposed on the direct contact;

a capacitor structure electrically connected to the first active region;

a gate structure disposed on the second active region in the peripheral circuit region;

a lower wiring layer disposed adjacent to the gate structure and electrically connected to the second active region;

an upper wiring layer disposed on the lower wiring layer;

a wiring insulating layer disposed between the lower wiring layer and the upper wiring layer; and

an upper contact plug connected to at least one of the lower wiring layer and the upper wiring layer and extending through the wiring insulating layer in a third direction perpendicular to the first direction and the second direction.

2. The semiconductor device of claim 1, wherein:

the lower wiring layer comprises a first lower wiring layer;

the upper routing layer comprises a first upper routing layer; and

the upper contact plug includes a first upper contact plug connected to the first lower wiring layer and the first upper wiring layer.

3. The semiconductor device of claim 2, wherein:

the first upper contact plug includes a lower portion, a middle portion, and an upper portion;

the lower portion of the first upper contact plug contacts the first lower wiring layer; and

the middle portion of the first upper contact plug extends through the first upper wiring layer and has a width greater than the lower portion in the first direction.

4. The semiconductor device of claim 2, wherein:

the lower wiring layer comprises a second lower wiring layer;

the upper contact plug includes a second upper contact plug connected to the second lower wiring layer; and

the second upper contact plug is spaced apart from the upper wiring layer in the first direction.

5. The semiconductor device of claim 4, further comprising:

an interlayer insulating layer surrounding the upper contact plug,

wherein, between the upper wiring layers, the interlayer insulating layer contacts an upper surface of the wiring insulating layer and a side surface of the second upper contact plug.

6. The semiconductor device of claim 2, wherein:

the upper routing layer comprises a second upper routing layer;

the upper contact plug includes a second upper contact plug connected to the second upper wiring layer; and

a lower surface of the second upper contact plug is disposed at a higher level than a lower surface of the wiring insulating layer in the third direction.

7. The semiconductor device according to claim 6, wherein the lower surface of the second upper contact plug is provided at a higher level than an upper surface of the wiring insulation layer in the third direction, and a width of the second upper contact plug is smaller than a width of the first upper contact plug in the first direction.

8. The semiconductor device of claim 2, wherein:

the upper contact plug includes a second upper contact plug connected to the gate structure and extending through the wiring insulation layer,

wherein the second upper contact plug is electrically insulated from the lower wiring layer and the upper wiring layer.

9. The semiconductor device of claim 1, wherein:

the lower wiring layer comprises a first lower wiring layer;

the upper routing layer comprises a first upper routing layer; and

the upper contact plug includes a first upper contact plug connected to the first upper wiring layer and the first lower wiring layer and a second upper contact plug connected to the first upper wiring layer.

10. The semiconductor device according to claim 1, wherein the wiring insulating layer comprises a groove formed at an upper surface of the wiring insulating layer between the upper wiring layers.

11. The semiconductor device according to claim 1, wherein the upper wiring layer is provided at a level lower than an upper surface of the capacitor structure in the third direction.

12. The semiconductor device of claim 1, wherein:

the wiring insulating layer extends to the cell region; and

the capacitor structure includes a dummy electrode in contact with an upper surface of the wiring insulating layer.

13. The semiconductor device of claim 1, wherein:

the capacitor structure includes a dummy electrode; and

the dummy electrode is spaced apart from the wiring insulating layer in the first direction.

14. The semiconductor device of claim 1, further comprising:

an interlayer insulating layer surrounding the upper contact plug,

wherein the interlayer insulating layer contacts the upper wiring layer.

15. A semiconductor device, comprising:

a direct contact contacting the first active region in the cell region;

a bit line structure disposed on the direct contact;

a capacitor structure electrically connected to the first active region;

a board layer covering the capacitor structure;

an upper wiring layer disposed on the lower wiring layer;

an upper contact plug connected to at least one of the lower wiring layer and the upper wiring layer and extending through the wiring insulating layer in a third direction perpendicular to the first direction and the second direction,

wherein the board layer includes the same material as the upper wiring layer.

16. The semiconductor device of claim 15, wherein:

the plate layer includes a first portion extending in the first direction and covering an upper surface of the capacitor structure and a second portion extending in the third direction and covering a side surface of the capacitor structure; and

a lower surface of the second portion is disposed at the same level as a lower surface of the upper wiring layer in the third direction.

17. The semiconductor device of claim 16, wherein the plate layer further comprises a third portion extending from the second portion along the first direction, the third portion contacting an upper surface of the wiring insulation layer.

18. The semiconductor device of claim 15, further comprising:

an upper insulating layer covering the board layer in the cell region and covering the upper wiring layer in the peripheral circuit region.

19. A semiconductor device, comprising:

a direct contact contacting the first active region in the cell region;

a bit line structure disposed on the direct contact;

a capacitor structure electrically connected to the first active region, the capacitor structure including a lower electrode, a capacitor dielectric layer covering the lower electrode, and an upper electrode covering the capacitor dielectric layer;

a plate layer covering the upper electrode;

a capacitor contact plug connected to the plate layer;

an upper wiring layer disposed on the lower wiring layer;

20. The semiconductor device of claim 19, further comprising:

a lower contact plug interconnecting the lower wiring layer and the second active region;

an insulating structure electrically insulating the lower wiring layers from each other; and

an interlayer insulating layer surrounding the upper contact plug,

wherein the interlayer insulating layer extends between the upper wiring layers.