CN115460350A - Image processing method and system based on FPGA - Google Patents

Image processing method and system based on FPGA Download PDF

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CN115460350A
CN115460350A CN202211071486.9A CN202211071486A CN115460350A CN 115460350 A CN115460350 A CN 115460350A CN 202211071486 A CN202211071486 A CN 202211071486A CN 115460350 A CN115460350 A CN 115460350A
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data
intermediate data
image
address information
fpga
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CN115460350B (en
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刘相锋
赵鸿波
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White Rhino Zhida Beijing Technology Co ltd
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White Rhino Zhida Beijing Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses an image processing method and system based on FPGA, which is applied to an FPGA processor and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the image processing method and system based on FPGA comprise the following steps: acquiring an environment image shot by a camera in real time, and converting the environment image into image data; removing address information carried by the image data, correcting according to image defects of the image data, and generating intermediate data; judging whether the intermediate data meet a plurality of writing conditions of the address information one by one; if all the address information meets the requirements, writing the address information into intermediate data to generate target data; the image data and the target data are sent to a host computing unit. The technical problem that in the prior art, a large amount of CPU resources are consumed due to the fact that deep participation of a CPU is needed, and delay is caused in an image processing process is solved. The invention releases the basic image processing function by utilizing the parallel processing capability of the FPGA processor, thereby reducing the delay of the system.

Description

Image processing method and system based on FPGA
Technical Field
The invention relates to the technical field of image processing, in particular to an image processing method and system based on an FPGA (field programmable gate array).
Background
With the development of artificial intelligence, intelligent automobiles gradually move into the field of vision of the public. The intelligent automobile is also called an unmanned automobile, the surrounding environment of the automobile is sensed through an on-board sensor, and a central control system of the automobile comprehensively controls the steering and the speed of the automobile according to information such as roads, barriers and the like sensed by the sensor, so that the automobile can safely and reliably run on the roads. Therefore, the image-based sensing technology is a key technology of the unmanned vehicle, and has obvious advantages in the fields of environmental sensing and navigation compared with other traditional sensor sensing technologies. However, the transmission and processing of a large number of images occupy a large amount of computing resources, so that the preprocessing of large-data-volume and high-bandwidth images is increasingly important.
In the prior art, image data is usually directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, and requires deep participation of a CPU, which consumes a large amount of CPU resources and causes delay in an image processing process.
Disclosure of Invention
The invention provides an image processing method and system based on an FPGA (field programmable gate array), which solve the technical problems that in the prior art, image data are usually directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, and needs deep participation of a CPU (Central processing Unit), so that a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention provides an image processing method based on FPGA (field programmable gate array), which is applied to an FPGA processor and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the method comprises the following steps:
acquiring an environment image shot by the camera in real time, and converting the environment image into image data;
removing address information carried by the image data, correcting according to image defects of the image data, and generating intermediate data;
judging whether the intermediate data meet a plurality of writing conditions of the address information one by one;
if all the address information meets the requirement, writing the address information into the intermediate data to generate target data;
and sending the image data and the target data to the main computing unit.
Optionally, the present invention further relates to an equipment motherboard connector, where the equipment motherboard connector is connected to the camera and the FPGA processor, respectively; the step of acquiring an environment image shot by the camera in real time and converting the environment image into image data comprises the following steps:
sending the environmental image shot by the camera to the equipment mainboard connector in real time according to a GMSL2 protocol to generate GMSL2 data;
and deserializing the GMSL2 data through the connector of the equipment mainboard to generate image data.
Optionally, the step of removing the address information carried by the image data, and performing correction according to the image defect of the image data to generate intermediate data includes:
removing address information carried by the image data to generate non-address data;
converting the RAW format in the unaddressed data into the RGB format to generate RGB image data;
correcting according to the image defects of the RGB image data to generate intermediate data; wherein the correction includes gamma correction, image enhancement, image scaling, and image recognition.
Optionally, the DDR4 component is connected with the FPGA processor; the step of judging one by one whether the intermediate data satisfies a plurality of writing conditions of the address information includes:
judging whether the intermediate data meets the condition of starting writing in the address information;
if yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
if yes, acquiring the address byte length corresponding to the intermediate data, and judging whether a prepared receiving signal sent by the DDR4 component is received or not;
if so, reading burst byte length data from the intermediate data, and transmitting the burst byte length data, the address byte length and a write data valid signal to the DDR4 component;
when a feedback signal of the DDR4 component is received, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not;
and if so, judging that the intermediate data meets all writing conditions of the address information.
Optionally, the step of determining whether the intermediate data satisfies a condition for starting writing of the address information includes:
judging whether the intermediate data meets the condition of starting writing in the address information; the intermediate data further includes a frame start write signal;
if the frame start writing signal is a rising edge, judging that the intermediate data meets the start writing condition of the address information;
and if the frame start writing signal is not a rising edge, judging that the intermediate data does not meet the condition of starting writing of the address information.
Optionally, if yes, the step of obtaining a frame start address of the intermediate data, and determining whether the transmission data in the fifo queue meets the transmission condition of the intermediate data includes:
if yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
if yes, transmitting address information corresponding to the intermediate data to the DDR4 component;
and if the transmission data does not meet the transmission conditions of the intermediate data, accumulating the new transmission data to the transmission data in the first-in first-out queue until the transmission data in the first-in first-out queue meets the transmission conditions of the intermediate data.
Optionally, if yes, the step of obtaining the address byte length corresponding to the intermediate data, and determining whether a prepared received signal sent by the DDR4 component is received includes:
if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data, acquiring the address byte length corresponding to the intermediate data;
judging whether a prepared received address signal sent by the DDR4 component is received or not;
and when the prepared receiving address signal is received, acquiring a write-in data valid signal of the intermediate data, and judging whether a prepared receiving data signal sent by the DDR4 component is received or not.
Optionally, the step of determining whether the number of bytes corresponding to the burst byte length data is equal to the number of bytes corresponding to the intermediate data when the feedback signal of the DDR4 component is received further includes:
when a feedback signal of the DDR4 component is received, acquiring the byte number corresponding to the burst byte length data from the feedback signal;
judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not;
when the byte number corresponding to the burst byte length data is smaller than the byte number corresponding to the intermediate data, accumulating and writing new address data into the burst byte length data;
and skipping to execute the step of judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not until the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data.
Optionally, the method further comprises:
acquiring an environment video shot by the camera in real time;
and compressing the environment video according to a preset format and sending the environment video to the main computing unit.
The second aspect of the present invention provides an image processing system based on FPGA, which is applied to an FPGA processor, and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected to the camera and the main computing unit, and the system includes:
the image data module is used for acquiring an environment image shot by the camera in real time and converting the environment image into image data;
the intermediate data module is used for removing address information carried by the image data, correcting according to image defects of the image data and generating intermediate data;
the writing condition module is used for judging whether the intermediate data meet a plurality of writing conditions of the address information one by one;
the target data module is used for writing the address information into the intermediate data to generate target data if all the address information is met;
a sending module for sending the image data and the target data to the main computing unit.
According to the technical scheme, the invention has the following advantages:
according to the invention, the environment image shot by the camera is obtained in real time, the environment image is converted into the image data, the address information carried in the image data is removed, and the data transmission is convenient, so that the efficiency is high, the delay is low, and the intermediate data is generated by correspondingly correcting according to the image defects in the image data; and judging whether the intermediate data meet a plurality of writing conditions of the address information one by one, and writing the address information into the intermediate data to generate target data when all the intermediate data meet the plurality of writing conditions of the address information. The image data and the target data are sent to the main computing unit together. The method solves the technical problems that image data are generally directly sent to a main computing unit for processing in the prior art, but the main computing unit is generally based on an X86 architecture or an ARM architecture and needs deep participation of a CPU, so that a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention releases the basic image processing function in the main computing unit by utilizing the parallel processing capability of the FPGA processor, reduces the delay of the system, realizes a large amount of image processing algorithms in the early stage by directly utilizing the technical means of parallel and data flow of the FPGA, releases a large amount of computing resources and can be used for deploying more algorithm models.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive labor.
Fig. 1 is a flowchart illustrating steps of an FPGA-based image processing method according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating steps of an image processing method based on an FPGA according to a second embodiment of the present invention;
fig. 3 is a schematic view of structural connection of a vehicle-mounted camera (camera), an apparatus motherboard connector, and an FPGA processor according to a second embodiment of the present disclosure;
fig. 4 is a schematic diagram of an internal structure of an FPGA processor according to a second embodiment of the present invention;
fig. 5 is a schematic flowchart of an internal state machine of an image processing method based on an FPGA according to a third embodiment of the present invention;
fig. 6 is a schematic diagram of an external interface of a Writepath module of an FPGA-based image processing method according to a third embodiment of the present invention;
fig. 7 is a block diagram of an image processing system based on an FPGA according to a fourth embodiment of the present invention.
Detailed Description
The embodiment of the invention provides an image processing method and system based on an FPGA (field programmable gate array), which are used for solving the technical problems that in the prior art, image data are generally directly sent to a main computing unit for processing, but the main computing unit is generally based on an X86 architecture or an ARM architecture, and needs deep participation of a CPU (Central processing Unit), so that a large amount of CPU resources are consumed, and delay is generated in the image processing process.
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating steps of an image processing method based on an FPGA according to an embodiment of the present invention.
The invention provides an image processing method based on FPGA, which is applied to an FPGA processor and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the method comprises the following steps:
step 101, acquiring an environment image shot by a camera in real time, and converting the environment image into image data.
It should be noted that, an FPGA (Field Programmable Gate Array), a Field Programmable Gate Array, and an FPGA contain resources such as a flip-flop, a lookup table, and a multiplier, and the programmed FPGA processor connects the resources according to a certain logic. The IO resources of the FPGA are rich, data can be processed in parallel inside the chip, the FPGA can be externally connected with a DDR chip, and the data can be processed when large data amount caching is needed. The data processing and transmission of the FPGA almost does not need the participation of a CPU, the CPU needs to participate deeply when the CPU calculates, the number of cores passing through the CPU is limited, and the switching task is delayed. The FPGA is different, for example three lines of formulas for calculating Y, B, CR can be processed in parallel, one step for each clock. R0.299, G0.587, B0.114 may be calculated simultaneously and then the next clock added. The calculation of the section is independently completed by the multiplier, the lookup table and other resources in the method, and does not need the participation of a CPU or other equipment, so that the FPGA can perform parallel processing on data by using any collocation of logic resources, a large amount of calculation resources can be saved, and more algorithm models can be conveniently deployed by a main calculation unit.
In the embodiment of the invention, the environment image shot by the camera is acquired in real time, the environment image can be conveniently and timely processed, and the environment image is converted into the image data for convenient transmission, thereby facilitating the subsequent processing.
And 102, removing address information carried by the image data, correcting according to image defects of the image data, and generating intermediate data.
The intermediate data refers to new data generated by removing address information and performing operations such as image correction on the image data.
In a specific embodiment, address information carried by image data is removed to generate unaddressed data, the unaddressed data is a data format inside the AMD FPGA, data transmission is performed in a data stream mode, and no address operation is performed, so that transmission efficiency is high and delay is low. The corresponding correction is carried out according to each image defect in the image data, the correction can comprise gamma correction, image enhancement, image scaling, image identification and the like, and if the image defect is not existed, the correction operation is not needed.
Step 103, judging whether the intermediate data meet a plurality of writing conditions of the address information one by one.
The writing conditions refer to a series of conditions set in accordance with a request for writing address information.
In a specific embodiment, before writing the address information into the intermediate data, the intermediate data simultaneously satisfies a plurality of writing conditions according to a predetermined sequence. If the intermediate data is needed to be judged firstly, whether the starting writing condition of the address information can be met or not is judged; secondly, judging that the transmission data in the first-in first-out queue can not meet the transmission condition of the intermediate data; thirdly, whether a prepared receiving signal sent by the DDR4 component is received or not is judged; and fourthly, judging whether the number of bytes corresponding to the burst byte length data is equal to the number of bytes corresponding to the intermediate data, wherein the writing conditions include but are not limited to the above conditions, and the writing conditions can be increased, modified or deleted according to actual conditions.
And 104, if all the address information is satisfied, writing the address information into the intermediate data to generate target data.
The target data refers to data obtained by performing a series of processes such as address removal, format conversion, image correction, and address rewriting on image data.
In a specific embodiment, the address information may be written into the intermediate data if the intermediate data satisfies all writing conditions of the address information. If one item of the intermediate data does not meet the writing condition of the address information, corresponding execution of relevant operation is carried out according to the writing condition, and the target data cannot be generated until all writing conditions are met.
Step 105, sending the image data and the target data to the main computing unit.
It should be noted that, the processed target data and the image data (original data) are sent to the main computing unit through the PCIE interface, and are used for data dropping in the later period.
According to the invention, the environment image shot by the camera is obtained in real time, the environment image is converted into the image data, the address information carried in the image data is removed, and the data transmission is convenient, so that the efficiency is high, the delay is low, and the intermediate data is generated by correspondingly correcting according to the image defects in the image data; and judging whether the intermediate data meet a plurality of writing conditions of the address information one by one, and writing the address information into the intermediate data to generate target data when all the intermediate data meet the plurality of writing conditions of the address information. The image data and the target data are sent to the main computing unit together. The method solves the technical problems that image data are generally directly sent to a main computing unit for processing in the prior art, but the main computing unit is generally based on an X86 architecture or an ARM architecture and needs deep participation of a CPU, so that a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention releases the basic image processing function in the main computing unit by utilizing the parallel processing capability of the FPGA processor, reduces the delay of the system, realizes a large amount of image processing algorithms in the early stage by directly utilizing the technical means of parallel and data flow of the FPGA, releases a large amount of computing resources and can be used for deploying more algorithm models.
Referring to fig. 2-4, fig. 2 is a flowchart illustrating steps of an FPGA-based image processing method according to a second embodiment of the present invention.
The invention provides an image processing method based on FPGA, which is applied to an FPGA processor and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the method comprises the following steps:
step 201, sending the environmental image shot by the camera to the equipment mainboard connector in real time according to the GMSL2 protocol to generate GMSL2 data.
It should be noted that GMSL (Gigabit Multimedia Serial Links) is a Gigabit Multimedia Serial link.
In a specific embodiment, as shown in fig. 3, the car-size camera (camera) is connected to the FAKRA connector of the equipment motherboard via a coaxial cable, and the protocol of the inside route is GMSL2, so that the environmental image captured by the camera is transmitted to the connector of the equipment motherboard via the coaxial cable to generate GMSL2 data.
And step 202, deserializing the GMSL2 data through a connector of the equipment mainboard to generate image data.
In a specific embodiment, the FAKRA connector of the device motherboard outputs the received GMSL2 signal to the deserializing chip, converts the GMSL2 data into image data (MIPI data), and sends the image data (MIPI data) to the FPGA.
Note that the MIPI (Mobile Industry Processor Interface) is a Mobile Industry Processor Interface.
And step 203, removing the address information carried by the image data, correcting according to the image defects of the image data, and generating intermediate data.
Optionally, step 203 further comprises the following steps S11-S13:
s11, removing address information carried by the image data to generate no-address data;
s12, converting the RAW format in the unaddressed data into an RGB format to generate RGB image data;
s13, correcting according to the image defects of the RGB image data to generate intermediate data; wherein the correction comprises gamma correction, image enhancement, image scaling and image recognition.
In a specific embodiment, as shown in fig. 4, image data (MIPI data) is transmitted to the inside of the FPGA through IO, and first enters the MIPI _ RX component and is converted into unaddressed data (AXI 4_ stream data).
And secondly, entering a Bayer _ RGB component to convert a RAW format transmitted by the camera into an RGB format, wherein each pixel of the RAW format is represented by one color, and the other two colors can be obtained by calculating a difference value when surrounding points contain the pixel of the color. For example, a pixel has only the color green, green has no difference, and red is the average of the upper and lower or left and right pixels. The operation at this time is also realized by the data flow mode and the parallel cache technology. The implementation algorithm is a high-resolution difference algorithm, can provide finer image edge characteristics, is particularly suitable for unmanned vehicle identification scenes, and can perform multipoint parallel computation compared with an original CPU.
Finally, entering the Image processing component realizes the functions of gamma correction, image enhancement, image scaling and the like of the Image through a data stream mode, and the correction can be specifically carried out according to the Image defect correspondence.
It should be noted that, in the data stream mode, the back-end component prepares to feed back the ready signal upwards, and the upper component continues to transmit data downwards when receiving the ready signal.
And step 204, judging whether the intermediate data meet a plurality of writing conditions of the address information one by one.
Optionally, the system also relates to a DDR4 component, wherein the DDR4 component is connected with the FPGA processor; step 204 also includes the following steps S21-S26:
s21, judging whether the intermediate data meet the condition of starting writing in the address information;
s22, if yes, obtaining a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
s23, if yes, obtaining the address byte length corresponding to the intermediate data, and judging whether a prepared receiving signal sent by the DDR4 component is received or not;
s24, if the data are received, reading burst byte length data from the intermediate data, and transmitting the burst byte length data, the address byte length and the write data effective signals to the DDR4 component;
s25, when a feedback signal of the DDR4 assembly is received, judging whether the number of bytes corresponding to the burst byte length data is equal to the number of bytes corresponding to the intermediate data or not;
and S26, if the address information is equal to the intermediate data, judging that the intermediate data meets all writing conditions of the address information.
It should be noted that a DDR4 component (DDR 4 chip) refers to a data cache used for image processing; the write start condition refers to a condition set for starting writing address information; the frame start address refers to the start address of the first frame of intermediate data; first-in First-out (FIFO) refers to a conventional in-sequence execution method, in which an instruction that enters First is completed and retired First, and then a second instruction is executed.
In a specific embodiment, as shown in fig. 4, when the image data is processed in a series of processes to obtain intermediate data, and the intermediate data enters the Writepath module, the address information may be written into the intermediate data only when a plurality of writing conditions are satisfied in a predetermined order.
Specifically, it is first determined whether the intermediate data can satisfy the condition for starting writing of the address information, and when the intermediate data satisfies the condition for starting writing of the address information, the address information can be started to be written, and the frame start address of the intermediate data is acquired, and the address information can be written from the frame start address. When the intermediate data does not satisfy the condition for starting writing of the address information, the writing of the address information cannot be started.
Secondly, judging that the transmission data in the first-in first-out queue can not meet the transmission condition of the intermediate data, when the transmission data is enough to transmit the address information corresponding to the intermediate data, acquiring the address byte length corresponding to the intermediate data, and transmitting the address information corresponding to the intermediate data to the DDR4 component; when the transmission data is not enough to transmit the address information corresponding to the intermediate data, the new transmission data is continuously accumulated until the transmission data is enough to transmit the address information corresponding to the intermediate data.
And thirdly, judging whether a prepared receiving signal sent by the DDR4 component is received or not, reading the burst byte length data from the intermediate data when the prepared receiving signal is received, and transmitting the burst byte length data, the address byte length and the writing data effective signal to the DDR4 component.
And when a feedback signal of the DDR4 assembly is received, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not, and if so, judging that the intermediate data meets all writing conditions of the address information. The address information may be written to the intermediate data.
Optionally, step S21 further comprises the following steps S31-S33:
s31, judging whether the intermediate data meet the condition of starting writing in the address information; the intermediate data further includes a frame start write signal;
s32, if the frame start writing signal is a rising edge, judging that the intermediate data meets the start writing condition of the address information;
and S33, if the frame start writing signal is not a rising edge, judging that the intermediate data does not meet the start writing condition of the address information.
It should be noted that the frame start write signal refers to a signal for starting writing of the first frame.
In an embodiment, the determination that the intermediate data cannot satisfy the condition for starting writing of the address information is determined by whether the frame start write signal is a rising edge. If the frame start writing signal is a rising edge, it can be determined that the intermediate data satisfies the start writing condition of the address information. If the frame start writing signal is not a rising edge, the intermediate data is judged not to meet the start writing condition of the address information.
Optionally, step S22 further comprises the following steps S41-S43:
s41, if yes, obtaining a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
s42, if yes, transmitting address information corresponding to the intermediate data to the DDR4 component;
and S43, if the transmission data does not meet the requirements, accumulating the new transmission data to the transmission data in the first-in first-out queue until the transmission data in the first-in first-out queue meets the transmission conditions of the intermediate data.
In a specific embodiment, if the intermediate data meets the condition for starting writing in the address information, the frame start address of the intermediate data can be obtained, then it is judged that the transmission data in the first-in first-out queue cannot meet the transmission condition of the intermediate data, when the transmission data is enough to transmit the address information corresponding to the intermediate data, the address byte length corresponding to the intermediate data is obtained, and the address information corresponding to the intermediate data is transmitted to the DDR4 component; when the transmission data is not enough to transmit the address information corresponding to the intermediate data, the new transmission data is continuously accumulated until the transmission data is enough to transmit the address information corresponding to the intermediate data.
Optionally, step S23 further comprises the following steps S51-S53:
s51, if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data, acquiring the address byte length corresponding to the intermediate data;
s52, judging whether a prepared received address signal sent by the DDR4 component is received or not;
and S53, when the prepared received address signal is received, acquiring a write data valid signal of the intermediate data, and judging whether the prepared received data signal sent by the DDR4 component is received.
In the embodiment of the invention, if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data, the address byte length corresponding to the intermediate data is obtained, and whether a prepared receiving address signal and a prepared receiving data signal sent by a DDR4 component are received or not is sequentially judged; when the prepared received address signal is received, the write-in data effective signal of the intermediate data is obtained, so that the write-in data effective signal can be known, when the prepared received data signal is received, the burst byte length data is read from the intermediate data, and the burst byte length data, the address byte length and the write-in data effective signal are transmitted to the DDR4 component.
Optionally, step S25 further comprises the following steps S61-S64:
s61, when a feedback signal of the DDR4 assembly is received, acquiring the number of bytes corresponding to burst byte length data from the feedback signal;
s62, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not;
s63, when the number of bytes corresponding to the burst byte length data is smaller than that of the intermediate data, accumulating and writing the new address data into the burst byte length data;
and S64, skipping to execute a step of judging whether the number of bytes corresponding to the burst byte length data is equal to the number of bytes corresponding to the intermediate data or not until the number of bytes corresponding to the burst byte length data is equal to the number of bytes corresponding to the intermediate data.
In a specific embodiment, when a feedback signal of the DDR4 component is received, the feedback signal carries burst byte length data, where the burst byte length data includes a number of bytes, and the number of bytes corresponding to the burst byte length data is compared with the number of bytes corresponding to the intermediate data to determine whether the intermediate data satisfies all write-in conditions of the address information, that is, the address information can be written in the intermediate data; when the number of bytes corresponding to the burst byte length data is smaller than that of the intermediate data, the new address data is accumulated and written into the burst byte length data, and the operation of comparing whether the number of bytes corresponding to the burst byte length data is equal to that of the intermediate data is repeatedly executed until the number of bytes is equal to that of the intermediate data.
And step 205, if all the address information is satisfied, writing the address information into the intermediate data to generate target data.
In the embodiment of the present invention, the specific implementation process of step 205 is similar to that of step 104, and is not described herein again.
Step 206, sending the image data and the target data to the main computing unit.
In a specific embodiment, the FPGA sends the processed image data (raw data) to the main computing unit for later data destaging and the like. As shown in fig. 4, the PCIE _ DMA component packages the target data that has been processed in the DDR4 component into a PCIE protocol data packet, and sends the PCIE protocol data packet to the main computing unit, so as to perform the functions of protocol conversion and data transfer.
It should be noted that the DMA (Direct Memory Access) is a Direct Memory Access and can Access the DDR4 component in real time.
The method further comprises the following steps S71-S72:
s71, acquiring an environment video shot by a camera in real time;
and S72, compressing the environment video according to a preset format, and sending the environment video to the main computing unit.
It should be noted that the CU _ H264/H265 component shown in fig. 4 is a video codec module of an FPGA.
In a specific embodiment, the environmental video data shot by the camera is acquired in real time, and the VCU _ H264/H265 module compresses the environmental video data according to the H265 format. And transmits the compressed video to the main computing unit for later data drop, etc.
According to the invention, the environment image shot by the camera is obtained in real time, the environment image is converted into the image data, the address information carried in the image data is removed, and the data transmission is convenient, so that the efficiency is high, the delay is low, and the intermediate data is generated by correspondingly correcting according to the image defects in the image data; and judging whether the intermediate data meet a plurality of writing conditions of the address information one by one, and writing the address information into the intermediate data to generate target data when all the intermediate data meet the plurality of writing conditions of the address information. The image data and the target data are sent to the main computing unit together. The method solves the technical problems that image data are generally directly sent to a main computing unit for processing in the prior art, but the main computing unit is generally based on an X86 architecture or an ARM architecture and needs deep participation of a CPU, so that a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention releases the basic image processing function in the main computing unit by utilizing the parallel processing capability of the FPGA processor, reduces the delay of the system, realizes a large amount of image processing algorithms in the early stage by directly utilizing the technical means of parallel and data flow of the FPGA, releases a large amount of computing resources and can be used for deploying more algorithm models.
Referring to fig. 5 to 6, fig. 5 is a schematic flowchart of an internal state machine of an image processing method based on an FPGA according to a third embodiment of the present invention.
The internal state machine execution flow of the image processing method based on the FPGA provided by the invention is shown in a combined manner in fig. 5 and 6, and the specific flow is as follows:
when axis _ tvs _ i is a rising edge, the state machine is transferred to W _ WRADDR _ CMD from W _ IDLE; meanwhile, assigning a frame starting address to axi _ awaddr _ o; pulling down the dma _ done signal, representing the start of writing data;
waiting for the data input into the FIFO by the module interface axis in the W _ WRADDR _ CMD state machine to send a burst data; when it is sufficient to send a burst of data: w _ WRADDR _ CMD _ WAIT state machine, and simultaneously pulling up the axi _ awvalid _ o signal and pulling down the axi _ wvalid _ o signal, because the data is not transmitted at the moment, but the address of the data is transmitted; assigning the byte length axi _ awlen _ o of the write; raising feedback axi _ break _ o to the DDR4 module;
waiting in the W _ WRADDR _ CMD _ WAIT state machine for DDR4 to transfer a ready to receive address signal: xi _ awready _ i, toggles to the W _ WRDATA state machine when the xi _ awready _ i signal is high, pulling the write data valid signal high: axi _ wvalid _ o; the axi _ awvalid _ o signal is pulled low because the address signal was already received by DDR4 when the axi _ awready _ i signal is high.
Receiving a received data ready signal from DDR4 at the W _ WRDATA state machine: and when axi _ ready _ i is carried out, reading out the data in the FIFO at the same time until the data with one burst length is read out, and sending the read-out data to the DDR4 together with an axi _ wvalid _ o signal, axi _ awlen _ o and the like.
When the data transmission of a burst is completed, the state machine of W _ WRDATA _ CMD _ LAST is switched to, and the signal of axi _ wlast _ o is pulled up to represent that the data transmission of a burst is completed,
waiting for a feedback signal axi _ bvalid _ i of DDR4 in a W _ WRDATA _ CMD _ LAST state machine, and judging that the written burst bytes are not enough bytes of axi _ width _ i x axis _ height _ i input by a module after receiving the feedback signal of DDR4. If not enough to switch to the state machine: w _ WRADDR _ CMD loop. And meanwhile, accumulating the address of the write according to the number of bytes of the LAST sudden write in a W _ WRDATA _ CMD _ LAST state machine: axi _ awaddr _ o. And repeating the cycle until all the data of one frame is written. The state then switches to the idle state machine: w _ IDLE, while pulling the dma _ done signal high, waits for the next write.
Specifically, each signal represents the following meaning:
axis _ linear _ o: judging whether the FIFO is full, if the FIFO is full, pulling down the signal to tell the upstream that the data can not be sent;
axis _ tdata _ i: waiting for data written into the FIFO;
axis _ tlast _ i: waiting for writing the last data zone bit of a line of FIFO data;
axis _ width _ i: the row byte number is used for calculating whether the sudden writing is finished or not;
axis _ height _ i: how many lines of a frame are used for calculating whether the frame data is finished;
start _ addr _ i: one frame is at the initial write address of DDR4.
As shown in fig. 6, each interface has the following meanings:
axis is data stream data;
axis _ tclk _ i: data stream clock;
axis _ tvs _ i, module starts writing signal;
axis _ width _ i: a frame width to be transmitted;
axis _ height _ i: the height of the frame to be transmitted;
start _ addr _ i: starting to write in the memory;
axis _ tddr _ sel _ i: a plurality of address selection signals;
rd _ dma _ done: the reading module finishes reading a frame of indication signal;
m00_ AXI: an address mapping data interface;
dma _ done: writing a frame indication signal;
write _ addr: the frame address being written;
axis _ tddr _ sel _ o: one frame, frame number being written.
Referring to fig. 7, fig. 7 is a block diagram of an image processing system based on an FPGA according to a fourth embodiment of the present invention.
The invention provides an image processing system based on FPGA, which is applied to an FPGA processor and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the system comprises:
an image data module 701, configured to obtain an environment image captured by a camera in real time, and convert the environment image into image data;
an intermediate data module 702, configured to remove address information carried by the image data, and correct the address information according to an image defect of the image data to generate intermediate data;
a writing condition module 703, configured to determine whether the intermediate data satisfies a plurality of writing conditions of the address information one by one;
a target data module 704, configured to write the address information into the intermediate data if all the address information is satisfied, and generate target data;
a sending module 705 for sending the image data and the target data to the host computing unit.
Optionally, the image data module 701 comprises:
the image data submodule is used for acquiring an environment image shot by the camera in real time and converting the environment image into image data;
and the intermediate data submodule is used for removing the address information carried by the image data, correcting according to the image defects of the image data and generating intermediate data.
Optionally, the intermediate data module 702 further comprises:
the non-address data submodule is used for removing address information carried by the image data and generating non-address data;
the RGB image data submodule is used for converting the RAW format in the unaddressed data into the RGB format to generate RGB image data;
the intermediate data submodule is used for correcting according to the image defects of the RGB image data to generate intermediate data; wherein the correction comprises gamma correction, image enhancement, image scaling and image recognition.
Optionally, the system also relates to a DDR4 component, wherein the DDR4 component is connected with the FPGA processor; the write condition module 703 further includes:
the writing condition submodule is used for judging whether the intermediate data meet the starting writing condition of the address information or not;
the transmission condition submodule is used for acquiring a frame start address of the intermediate data if the frame start address meets the requirement, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data or not;
the prepared received signal submodule is used for acquiring the address byte length corresponding to the intermediate data if the address byte length is met, and judging whether a prepared received signal sent by the DDR4 component is received or not;
the DDR4 component submodule is used for reading burst byte length data from the intermediate data if the intermediate data is received, and transmitting the burst byte length data, the address byte length and the write data effective signal to the DDR4 component;
the byte number judging submodule is used for judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not when a feedback signal of the DDR4 assembly is received;
and the all-write-condition submodule is used for judging that the intermediate data meets all write-conditions of the address information if the intermediate data is equal to the address information.
Optionally, the write condition submodule further includes:
a write start condition submodule for judging whether the intermediate data satisfies a write start condition of the address information; the intermediate data further includes a frame start write signal;
the sub-module for writing the frame start writing signal as a rising edge is used for judging that the intermediate data meets the condition of starting writing the address information if the frame start writing signal is the rising edge;
the sub-module for frame start writing signal is not rising edge, which is used to determine that the intermediate data does not satisfy the condition of starting writing address information if the frame start writing signal is not rising edge.
Optionally, the delivery condition submodule further includes:
a sub-module for judging the transmission condition, which is used for obtaining the frame start address of the intermediate data if the frame start address meets the requirement, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
the sub-module meeting the conveying condition is used for transmitting the address information corresponding to the intermediate data to the DDR4 component if the sub-module meets the conveying condition;
and the substandard transport condition submodule is used for accumulating the new transport data to the transport data in the first-in first-out queue until the transport data in the first-in first-out queue meets the transport condition of the intermediate data if the substandard transport condition submodule is not satisfied.
Optionally, the prepared received signal sub-module further comprises:
the address byte length submodule is used for acquiring the address byte length corresponding to the intermediate data if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
the prepared received address signal submodule is used for judging whether a prepared received address signal sent by the DDR4 component is received or not;
and the prepared received data signal submodule is used for acquiring a write data valid signal of the intermediate data when the prepared received address signal is received, and judging whether the prepared received data signal sent by the DDR4 component is received or not.
Optionally, the byte count determining submodule further includes:
the byte number acquisition submodule is used for acquiring the byte number corresponding to the burst byte length data from the feedback signal when the feedback signal of the DDR4 component is received;
a submodule for judging whether the byte number is equal or not, which is used for judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not;
the byte number is less than the submodule and is used for writing the new address data into the burst byte length data in an accumulated manner when the byte number corresponding to the burst byte length data is less than the byte number corresponding to the intermediate data;
and the skip execution submodule is used for skipping and executing the step of judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not until the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data.
This system, still include:
the environment video submodule is used for acquiring an environment video shot by the camera in real time;
and the compressed environment video submodule is used for compressing the environment video according to a preset format and sending the environment video to the main computing unit.
According to the invention, the environment image shot by the camera is acquired in real time, the environment image is converted into the image data, the address information carried in the image data is removed, and the data transmission is convenient, so that the method is efficient and low in delay, and the intermediate data is generated by correspondingly correcting according to the image defects in the image data; and judging whether the intermediate data meet a plurality of writing conditions of the address information one by one, and writing the address information into the intermediate data to generate target data when all the intermediate data meet the plurality of writing conditions of the address information. The image data and the target data are sent to the main computing unit together. The method solves the technical problems that image data are generally directly sent to a main computing unit for processing in the prior art, but the main computing unit is generally based on an X86 architecture or an ARM architecture and needs deep participation of a CPU, so that a large amount of CPU resources are consumed, and delay is generated in the image processing process.
The invention releases the basic image processing function in the main computing unit by utilizing the parallel processing capability of the FPGA processor, reduces the delay of the system, realizes a large amount of image processing algorithms in the early stage by directly utilizing the technical means of parallel and data flow of the FPGA, releases a large amount of computing resources and can be used for deploying more algorithm models.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention, which is substantially or partly contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. An image processing method based on FPGA is characterized in that the image processing method is applied to an FPGA processor, and relates to a camera and a main computing unit, wherein the FPGA processor is respectively connected with the camera and the main computing unit, and the method comprises the following steps:
acquiring an environment image shot by the camera in real time, and converting the environment image into image data;
removing address information carried by the image data, correcting according to image defects of the image data, and generating intermediate data;
judging whether the intermediate data meet a plurality of writing conditions of the address information one by one;
if all the address information meets the requirement, writing the address information into the intermediate data to generate target data;
sending the image data and the target data to the host computing unit.
2. The FPGA-based image processing method of claim 1, further comprising an equipment motherboard connector, wherein the equipment motherboard connector is respectively connected with the camera and the FPGA processor; the step of acquiring an environment image shot by the camera in real time and converting the environment image into image data comprises the following steps:
sending an environment image shot by the camera to the equipment mainboard connector in real time according to a GMSL2 protocol to generate GMSL2 data;
and deserializing the GMSL2 data through the connector of the equipment mainboard to generate image data.
3. The FPGA-based image processing method according to claim 1, wherein the step of removing address information carried by the image data, performing correction according to image defects of the image data, and generating intermediate data comprises:
removing address information carried by the image data to generate address-free data;
converting the RAW format in the unaddressed data into the RGB format to generate RGB image data;
correcting according to the image defects of the RGB image data to generate intermediate data; wherein the correction includes gamma correction, image enhancement, image scaling, and image recognition.
4. The FPGA-based image processing method of claim 1, further comprising a DDR4 component, wherein the DDR4 component is connected to the FPGA processor; the step of judging one by one whether the intermediate data satisfies a plurality of writing conditions of the address information includes:
judging whether the intermediate data meets the condition of starting writing in the address information or not;
if yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
if yes, acquiring the address byte length corresponding to the intermediate data, and judging whether a prepared receiving signal sent by the DDR4 component is received or not;
if so, reading burst byte length data from the intermediate data, and transmitting the burst byte length data, the address byte length and a write data valid signal to the DDR4 component;
when a feedback signal of the DDR4 component is received, judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not;
and if so, judging that the intermediate data meets all writing conditions of the address information.
5. The FPGA-based image processing method of claim 4, wherein the step of determining whether the intermediate data satisfies a condition for starting writing of the address information comprises:
judging whether the intermediate data meets the condition of starting writing in the address information or not; the intermediate data further includes a frame start write signal;
if the frame start writing signal is a rising edge, judging that the intermediate data meets the start writing condition of the address information;
and if the frame starting writing signal is not a rising edge, judging that the intermediate data does not meet the starting writing condition of the address information.
6. The FPGA-based image processing method according to claim 4, wherein the step of obtaining a frame start address of the intermediate data and determining whether the transmission data in the FIFO queue satisfies the transmission condition of the intermediate data if the frame start address of the intermediate data satisfies the transmission condition of the intermediate data comprises:
if yes, acquiring a frame start address of the intermediate data, and judging whether the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data;
if yes, transmitting address information corresponding to the intermediate data to the DDR4 component;
and if the transmission data does not meet the transmission conditions of the intermediate data, accumulating the new transmission data to the transmission data in the first-in first-out queue until the transmission data in the first-in first-out queue meets the transmission conditions of the intermediate data.
7. The FPGA-based image processing method according to claim 4, wherein if the address byte length is satisfied, the step of obtaining the address byte length corresponding to the intermediate data and determining whether a prepared received signal sent by the DDR4 component is received comprises:
if the transmission data in the first-in first-out queue meets the transmission condition of the intermediate data, acquiring the address byte length corresponding to the intermediate data;
judging whether a prepared received address signal sent by the DDR4 component is received or not;
and when the prepared receiving address signal is received, acquiring a write-in data valid signal of the intermediate data, and judging whether a prepared receiving data signal sent by the DDR4 component is received or not.
8. The FPGA-based image processing method of claim 4, wherein the step of determining whether the number of bytes corresponding to the burst byte length data is equal to the number of bytes corresponding to the intermediate data when the feedback signal of the DDR4 component is received further comprises:
when a feedback signal of the DDR4 component is received, acquiring the byte number corresponding to the burst byte length data from the feedback signal;
judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not;
when the byte number corresponding to the burst byte length data is smaller than the byte number corresponding to the intermediate data, accumulating and writing new address data into the burst byte length data;
and skipping to execute the step of judging whether the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data or not until the byte number corresponding to the burst byte length data is equal to the byte number corresponding to the intermediate data.
9. The FPGA-based image processing method of claim 1, further comprising:
acquiring an environment video shot by the camera in real time;
and compressing the environment video according to a preset format and sending the environment video to the main computing unit.
10. The utility model provides an image processing system based on FPGA which characterized in that is applied to the FPGA treater, relates to camera and main computational element, the FPGA treater respectively with the camera with main computational element connects, the system includes:
the image data module is used for acquiring an environment image shot by the camera in real time and converting the environment image into image data;
the intermediate data module is used for removing address information carried by the image data, correcting according to image defects of the image data and generating intermediate data;
the writing condition module is used for judging whether the intermediate data meet a plurality of writing conditions of the address information one by one;
the target data module is used for writing the address information into the intermediate data to generate target data if all the address information is met;
a sending module for sending the image data and the target data to the main computing unit.
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