CN113630586A - Single-light-source full-color camera - Google Patents
Single-light-source full-color camera Download PDFInfo
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- CN113630586A CN113630586A CN202110856635.1A CN202110856635A CN113630586A CN 113630586 A CN113630586 A CN 113630586A CN 202110856635 A CN202110856635 A CN 202110856635A CN 113630586 A CN113630586 A CN 113630586A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/10—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/50—Constructional details
- H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
- H04N23/74—Circuitry for compensating brightness variation in the scene by influencing the scene brightness using illuminating means
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
- H04N23/84—Camera processing pipelines; Components thereof for processing colour signals
- H04N23/843—Demosaicing, e.g. interpolating colour pixel values
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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Abstract
The invention relates to a single light source full-color camera, comprising: the system comprises a visible light sensor, a low-light-level algorithm FPGA processor, an image signal processing chip and a main control chip; the visible light sensor is connected with one end of the shimmer algorithm FPGA processor; the image signal processing chip and the main control chip are respectively connected with the other end of the low-light-level algorithm FPGA processor; the visible light sensor is used for acquiring an original image and inputting the original image to the low-light-level algorithm FPGA processor; the low-light-level algorithm FPGA processor is used for denoising the original image and inputting the denoised image into the image signal processing chip; the image signal processing chip is used for processing the denoised image to obtain an sRGB image; the main control chip is used for carrying out parameter configuration on the low-light-level algorithm FPGA processor and generating a cache address. The single-light-source full-color camera improves the quality of picture output.
Description
Technical Field
The invention relates to the field of cameras, in particular to a single-light-source full-color camera.
Background
In the field of cameras, due to the requirement of all-weather monitoring, the camera can be set functionally according to the illumination environment, such as wide dynamic, strong light inhibition, starlight level ultralow illumination and the like. When the illumination is sufficient in the daytime, the ISP system of the camera can restore the original image input by the SENSOR to an sRGB image with high definition and vivid color. However, under the condition of dim light at night, the signal-to-noise ratio of the original image input by the SENSOR is sharply reduced due to weak light intensity, most of effective information of the image is submerged in various noises, and if the method only depends on simple ISP processing, the restored sRGB image is blurred and monotonous in color.
Therefore, a full-color black-light camera is proposed in the industry, for example, the invention of "black-light full-color implementation method and black-light full-color camera" by hangzhou fluorite software ltd, the invention adopts two starlight-level image sensors, wherein one starlight-level image sensor acquires image brightness information and object outline through infrared supplementary lighting, and the other starlight-level image sensor acquires color information. And then fusing image information acquired by the two starlight level image sensors through an image fusion algorithm, and outputting a bright full-color image. Under the dim light environment at night, the black light camera also needs to be supplemented with light by an infrared light supplementing lamp. In some low-light scenes which cannot be supplemented with light, the black-light camera cannot work effectively due to the imaging principle, and the quality of output images is not satisfactory.
Disclosure of Invention
The invention aims to provide a single-light-source full-color camera to solve the problem that the quality of an output image of the existing camera is low in a dim light environment at night.
In order to achieve the purpose, the invention provides the following scheme:
a single light source full color camera comprising: the system comprises a visible light sensor, a low-light-level algorithm FPGA processor, an image signal processing chip and a main control chip;
the visible light sensor is connected with one end of the shimmer algorithm FPGA processor; the image signal processing chip and the main control chip are respectively connected with the other end of the micro-optical algorithm FPGA processor;
the visible light sensor is used for acquiring an original image and inputting the original image to the micro-optic algorithm FPGA processor; the micro-optical algorithm FPGA processor is used for denoising the original image and inputting the denoised image into the image signal processing chip; the image signal processing chip is used for processing the denoised image to obtain an sRGB image; the main control chip is used for carrying out parameter configuration on the micro-optical algorithm FPGA processor and generating a cache address.
Optionally, the shimmer algorithm FPGA processor is further configured to perform demosaicing processing on the denoised image to obtain an sRGB image.
Optionally, the system further comprises a double-rate synchronous dynamic random access memory;
the double-rate synchronous dynamic random access memory is connected with the micro-optical algorithm FPGA processor; the double-rate synchronous dynamic random access memory is used for storing the original image, the denoised image and the sRGB image.
Optionally, the shimmer algorithm FPGA processor specifically includes: the system comprises an image interface module, an algorithm processing module and an internal bus;
the image interface module is connected with the visible light sensor and used for receiving the original image and transmitting the original image to the double-rate synchronous dynamic random access memory;
the algorithm processing module is connected with the double-rate synchronous dynamic random access memory and is used for carrying out noise estimation, denoising and demosaicing on the original image and transmitting the denoised image and the sRGB image to the double-rate synchronous dynamic random access memory.
Optionally, the shimmer algorithm FPGA processor further includes: an internal bus;
the image interface module, the algorithm processing module and the double-rate synchronous dynamic random access memory are communicated through the internal bus.
Optionally, the image interface module specifically includes: an MIPI-CSI interface, an MIPI-ISP interface and an HDMI interface;
one end of the MIPI-CSI interface is connected with the visible light sensor, and the other end of the MIPI-CSI interface is connected with the double-rate synchronous dynamic random access memory through the internal bus; the MIPI-CSI interface is used for receiving the original image and inputting the original image into the double-rate synchronous dynamic random access memory;
one end of the MIPI-ISP interface is connected with the image signal processing chip; the other end of the MIPI-ISP interface is connected with the double-rate synchronous dynamic random access memory through the internal bus; the MIPI-ISP interface is used for extracting the denoised image according to the cache address and inputting the denoised image data to the image signal processing chip;
one end of the HDMI is respectively connected with the algorithm processing module and the double-rate synchronous dynamic random access memory through the internal bus; the other end of the HDMI is connected with a display device; the HDMI is used for outputting the sRGB image.
Optionally, the processing, by the image signal processing chip, of the denoised image specifically includes: automatic exposure control, automatic gain control, automatic white balance, color correction, lens shading, Gamma correction and dead pixel removal.
Optionally, the algorithm processing module specifically includes: a NoiseES submodule, a DeNoise submodule and a DeMosic submodule; the NoiseES submodule, the DeNoise submodule and the DeMosic submodule are connected in sequence;
the NoiseES submodule is connected with the double-rate synchronous dynamic random access memory; the NoiseES submodule is used for extracting the original image according to the cache address, carrying out noise estimation on the original image and determining the noise degree of the original image;
the DeNoise submodule is used for carrying out denoising processing on the original image according to the noise degree;
and the DeMosic submodule is used for demosaicing the de-noised image and outputting an sRGB image.
Optionally, the noise level includes: slight, moderate, and severe noise.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
according to the invention, an original image is acquired through a visible light sensor, a low-light-level algorithm FPGA processor performs denoising processing on the original image, an image signal processing chip performs image processing on the denoised image, and an sRGB image is output. Under the weak environment of light night, just can accomplish the collection to the luminance information of image, object profile and color information through visible light sensor, the bright full-color image of output does not need extra light filling lamp to carry out the light filling, has improved the quality of picture output.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a block diagram of a single light source full-color camera according to the present invention;
fig. 2 is a logic block diagram inside a low-light-level algorithm FPGA processor of the single-light-source full-color camera provided by the invention.
Description of the symbols: 1-a visible light sensor; 2-a low-light-level algorithm FPGA processor; 3-an image signal processing chip; 4-a main control chip; 5-an image interface module; 6-an algorithm processing module; 7-double rate synchronous dynamic random access memory; 8-internal bus.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a single-light-source full-color camera to solve the problem that the quality of an output image of the existing camera is low in a dim light environment at night. The full-color video camera is suitable for various illumination conditions (including an environment with sufficient daytime illumination and dim light at night), only one visible light sensor is needed, an infrared sensor is not needed, and in a dim light scene, an additional light supplement lamp is not needed, so that the camera can output clear full-color video images, and the full-color video camera is more suitable for some scenes which cannot supplement light.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a structural diagram of a single-light-source full-color camera provided by the present invention, and as shown in fig. 1, the single-light-source full-color camera includes: the device comprises a visible light sensor 1, a low-light-level algorithm FPGA processor 2, an image signal processing chip 3 and a main control chip 4.
The visible light sensor 1 is connected with one end of the micro-optic algorithm FPGA processor 2; the image signal processing chip 3 and the main control chip 4 are respectively connected with the other end of the micro-optical algorithm FPGA processor 2.
The visible light sensor 1 is used for acquiring an original image and inputting the original image into the micro-optic algorithm FPGA processor 2; the micro-optical algorithm FPGA processor 2 is used for denoising the original image and inputting the denoised image into the image signal processing chip 3; the image signal processing chip 3 is used for processing the denoised image to obtain an sRGB image; the main control chip 4 is used for performing parameter configuration on the micro-optical algorithm FPGA processor 2 and generating a cache address.
In a specific embodiment, the shimmer algorithm FPGA processor 2 is further configured to perform demosaicing processing on the denoised image to obtain an sRGB image.
The visible light sensor module outputs an original image (RAW image) generated by the visible light sensor 1 in real time to the low-light-level algorithm FPGA processor 2 through the MIPI interface. The low-light-level algorithm FPGA processor 2 receives the RAW image through an MIPI interface of the visible light sensor 1. And estimating the noise level of the RAW image, and completing the denoising processing of the RAW image in the low-light-level algorithm FPGA processor 2 according to different noise levels. After the denoising process is completed, the image signal can be output to the image signal processing chip 3(ISP chip) through the MIPI interface, the demosaicing process of the denoised RAW image can be completed in the low-light-level algorithm FPGA processor 2, and the sRGB image is directly output through the HDMI interface. The main control chip 4 configures various parameters for the low-light-level algorithm FPGA processor 2 through the PCIE interface. The ISP chip receives the denoised RAW image through the MIPI interface, processes the RAW image, specifically comprises AEC (automatic exposure control), AGC (automatic gain control), AWB (automatic white balance), color correction, Lens Shading, Gamma correction and dead pixel removal, and recovers a corresponding sRGB image.
In one embodiment, the single light source full color camera further comprises a double rate synchronous dynamic random access memory 7; the double-rate synchronous dynamic random access memory 7 is connected with the micro-optical algorithm FPGA processor 2; the double-rate synchronous dynamic random access memory 7 is used for storing the original image, the denoised image and the sRGB image.
Fig. 2 is an internal logic block diagram of the low-light-level algorithm FPGA processor provided in the present invention, as shown in fig. 2, in a specific embodiment, the low-light-level algorithm FPGA processor 2 specifically includes: an image interface module 5, an algorithm processing module 6 and an internal bus 8; the image interface module 5 is connected to the visible light sensor 1, and is configured to receive the original image and transmit the original image to the double-rate synchronous dynamic random access memory 7; the algorithm processing module 6 is connected to the double-rate synchronous dynamic random access memory 7, and is configured to perform noise estimation, denoising and demosaicing on the original image, and transmit the denoised image and sRGB image to the double-rate synchronous dynamic random access memory 7.
In one embodiment, the image interface module 5, the algorithm processing module 6 and the double rate synchronous dynamic random access memory 7 communicate with each other through the internal bus 8.
In a specific embodiment, the image interface module 5 specifically includes: the image interface module 5 completes input of a RAW image of the visible light sensor 1, output of a denoised RAW image and output of an sRGB image.
One end of the MIPI-CSI interface is connected with the visible light sensor 1, and the other end of the MIPI-CSI interface is connected with the double-rate synchronous dynamic random access memory 7 through the internal bus 8; the MIPI-CSI interface is configured to receive a RAW image and input the RAW image to the double rate synchronous dynamic random access memory 7.
The FPGA is connected with the visible light sensor 1 through an MIPI CSI interface and comprises an MIPI D-PHY module, MIPI Receive logic and original image cache logic, and the working process is as follows:
step 1: the MIPI D-PHY module adopts 1 pair of source synchronous differential clocks and 4 pairs of differential data lines to carry out data transmission, and conversion from differential signals of RAW images input by the visible light sensor 1 to serial digital signals is completed.
Step 2: the MIPI Receive logic completes the frame synchronization of the serial digital signals and extracts complete image frame data. Firstly, the initial position of a frame of data is searched in the serial digital signal, then the alignment processing of the serial digital signal is completed according to the initial position, and the serial digital signal is converted into a complete original image of a frame.
And step 3: the original image caching logic writes the extracted RAW image into a Double Data Rate (DDR) memory 7 through an internal bus 8 according to a caching address allocated by the main control chip 4 for caching, and notifies the algorithm processing module 6 of subsequent processing through an interrupt signal.
One end of the MIPI-ISP interface is connected with the image signal processing chip 3; the other end of the MIPI-ISP interface is connected with the double-rate synchronous dynamic random access memory 7 through the internal bus 8; the MIPI-ISP interface is used for extracting the denoised image according to the cache address and inputting the denoised image data to the image signal processing chip 3.
The FPGA is connected with an ISP chip through an MIPI CSI interface and comprises an MIPI D-PHY module, an MIPI Transmit logic and a denoising original image reading logic, and the working process is as follows:
step 1: and (3) denoising original image reading logic, wherein after the algorithm processing module 6 finishes denoising processing of a frame of RAW image, the logic informs the denoising original image reading logic of the MIPI-ISP interface through an interrupt signal. The denoising original image reading logic reads the denoised original image from the DDR into the FPGA through the internal bus 8 according to the frame buffer address carried in the interrupt signal.
Step 2: the MIPI Transmit logic completes serialization processing of the denoised original image. Firstly, inserting frame synchronization information into the header of the denoised original image, and then serializing the denoised original image.
And step 3: the MIPI D-PHY module adopts 1 pair of source synchronous differential clocks and 4 pairs of differential data lines to carry out data transmission, and conversion from serial digital signals of the denoised original image to differential signals is completed.
One end of the HDMI is respectively connected with the algorithm processing module 6 and the double-rate synchronous dynamic random access memory 7 through the internal bus 8; the other end of the HDMI is connected with a display device; the HDMI is used for outputting the sRGB image.
The FPGA is connected with the display equipment through an HDMI interface and comprises an HDMI TX PHY module, HDMI TX control logic and sRGB image reading logic, and the working flow is as follows:
step 1: sRGB image reading logic, after the demosaic (Demosic) processing of one frame of RAW image is completed by the algorithm processing module 6, the sRGB image reading logic of the HDMI interface is notified by an interrupt signal. The sRGB image reading logic reads the sRGB image from the DDR into the FPGA through the internal bus 8 according to the cache address carried in the interrupt signal.
Step 2: the HDMI TX control logic completes serialization processing of the sRGB image. Frame synchronization information is inserted into the header of the sRGB image, and then the sRGB image is serialized.
And step 3: the HDMI TX PHY module adopts 1 pair of source synchronous differential clocks and 3 pairs of differential data lines to carry out data transmission, completes conversion from serial digital signals of sRGB images to differential signals, and outputs the signals to display equipment.
In a specific embodiment, the processing, by the image signal processing chip 3, of the denoised image specifically includes: automatic exposure control, automatic gain control, automatic white balance, color correction, lens shading, Gamma correction and dead pixel removal.
In a specific embodiment, the algorithm processing module 6 specifically includes: a NoiseES submodule, a DeNoise submodule and a DeMosic submodule; the NoiseES submodule, the DeNoise submodule and the DeMosic submodule are connected in sequence. The algorithm processing module 6 completes noise estimation of the RAW image, de-noising processing of the RAW image and de-mosaicing processing of the de-noised RAW image.
The NoiseES submodule is connected with the double-rate synchronous dynamic random access memory 7; the NoiseES submodule is used for extracting the original image according to the cache address, carrying out noise estimation on the original image and determining the noise degree of the original image.
The NoiseES module includes an original image reading logic and an original image noise estimation logic, completes noise estimation of an original RAW image, and classifies the RAW image into 3 classes according to the noise degree, as follows:
noisleak, the degree of noise is slight.
Noisenorm, moderate in noise level.
Noissestrong, the degree of noise is severe.
The process flow of the NoiseES module is as follows:
step 1: the original image reading logic, the image interface module 5 receives a frame RAW image and then notifies the NoiseES module through an interrupt signal. And the original image reading logic reads the RAW image from the DDR to the FPGA through the internal bus 8 according to the cache address carried in the interrupt signal.
Step 2: the invention relates to an original image noise estimation logic, which adopts a method based on a filter. Firstly, smoothing the RAW image by using a median filter, then calculating the pixel difference average value of the RAW image and the smoothed image, finally judging the severity of image noise according to the pixel difference average value, and setting 2 noise thresholds as follows:
a WEAK noise threshold, which represents a slight degree of noise;
and if the estimated noise of the RAW image is smaller than a WEAK noise threshold value, judging that the noise of the RAW image belongs to NoiseWeak.
NORMAL noise threshold, indicating moderate noise.
And if the estimated noise of the RAW image is greater than or equal to a WEAK noise threshold and is less than a NORMAL noise threshold, judging that the noise of the RAW image belongs to the NoiseOrmal degree.
And if the estimated noise of the RAW image is greater than or equal to the NORMAL noise threshold value, judging that the noise of the RAW image belongs to the NoiseStrong degree.
And step 3: after the noise estimation of the RAW image is completed, the DeNoise module is informed to perform the subsequent processing by an interrupt signal.
And the DeNoise submodule is used for carrying out denoising processing on the original image according to the noise degree.
And the DeNoise module adopts denoising models of different levels to complete the denoising processing of the RAW image according to the noise level of the RAW image. The method supports different denoising models of 3 grades, each denoising model is firstly trained by adopting a deep learning method, then the trained models are respectively subjected to INT8 quantization processing, and finally the denoising quantization model is obtained. The forward derivation function of the denoising quantization model is realized by a DeNoise module in the FPGA.
The three denoising models are as follows:
denoiser peak model:
the DeNoiseWeak model processes RAW images of noise levels of the DeNoiseWeak. The DeNoiseWeak model only inputs one frame of RAW image each time, and when the images are input, normalization processing is firstly carried out, and after model processing, one frame of denoised RAW image is output.
Denoise normal model:
the denoiser normal model processes RAW images at the noise level of the denoiser normal. The denoise normal model inputs two frames of RAW images each time, including a current frame and a previous frame of RAW image on a time sequence, and when the images are input, normalization processing is firstly carried out, and after model processing, a denoised RAW image corresponding to the current frame is output.
Denoiser strong model:
the denoisestong model processes RAW images at the noise level of noiisestong. The denoisestong model inputs four frames of RAW images at a time, including the current frame and the first three frames of RAW images in time series. When an image is input, firstly normalization processing is carried out, and after model processing, a denoised RAW image corresponding to a current frame is output.
The process flow of the DeNoise module is as follows (taking the DeNoise week module as an example):
step 1: and original image reading logic, wherein after the noise estimation of one frame of data is completed by the NoiseES module, the NoiseES module notifies the original image reading logic of the DeNoise module through an interrupt signal. And the original image reading logic reads the RAW image from the DDR to the FPGA through the internal bus 8 according to the cache address carried in the interrupt signal.
Step 2: and selecting a corresponding noise processing model according to the type of the noise carried in the interrupt signal. And if the noise of the RAW image belongs to the NoiseWeak grade, loading the parameters of the DeNoiseWeak model into a DeNoise module inside the FPGA from the DDR.
And step 3: after the normalization processing is performed on the current RAW image, the current RAW image is input into a denoiser peak model for denoising processing, and after one frame of data processing is completed, the denoised RAW image is written into a DDR for caching through an internal bus 8 according to a cache address distributed by a main control chip 4.
And 4, step 4: and meanwhile, a completion interrupt of the DeNoise processing is generated, and the DeMosic module and the image interface module 5 are informed to perform subsequent processing.
And the DeMosic submodule is used for demosaicing the de-noised image and outputting an sRGB image.
The DeMosic module converts the denoised RAW image into an sRGB image, and can output and display the sRGB image through an HDMI interface. The RAW2sRGB model in the DeMosic module is trained by adopting a deep learning method, and the trained model is subjected to INT8 quantization processing to obtain a DeMosic quantization model, wherein the forward derivation function of the DeMosic quantization model is realized by an FPGA.
Step 1: and the DeNoise original image reading logic informs the DeNoise original image reading logic of the DeMosic module through an interrupt signal after the DeNoise module finishes denoising of one frame of data. And the denoising original image reading logic reads the denoising RAW image from the DDR to the DeMosic module in the FPGA through the internal bus 8 according to the cache address carried in the interrupt signal.
Step 2: and loading the parameters of the DeMosic model into a DeMosic module in the FPGA from the DDR.
And step 3: and after the denoising RAW image is subjected to normalization processing, inputting the image into a DeMosic model for demosaicing processing, and after one frame of RAW image is processed, writing the obtained sRGB image into a DDR (double data rate) through an internal bus 8 for caching according to a cache address distributed by a main control chip 4.
And 4, step 4: at the same time, a completion interrupt of the DeMosic process is generated and the image interface module 5 is notified.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (9)
1. A single light source full color camera, comprising: the system comprises a visible light sensor, a low-light-level algorithm FPGA processor, an image signal processing chip and a main control chip;
the visible light sensor is connected with one end of the shimmer algorithm FPGA processor; the image signal processing chip and the main control chip are respectively connected with the other end of the micro-optical algorithm FPGA processor;
the visible light sensor is used for acquiring an original image and inputting the original image to the micro-optic algorithm FPGA processor; the micro-optical algorithm FPGA processor is used for denoising the original image and inputting the denoised image into the image signal processing chip; the image signal processing chip is used for processing the denoised image to obtain an sRGB image; the main control chip is used for carrying out parameter configuration on the micro-optical algorithm FPGA processor and generating a cache address.
2. The single-light-source full-color camera according to claim 1, wherein the micro-optical-algorithm FPGA processor is further configured to demosaic the de-noised image to obtain an sRGB image.
3. The single light source full-color camera according to claim 2, further comprising a double rate synchronous dynamic random access memory;
the double-rate synchronous dynamic random access memory is connected with the micro-optical algorithm FPGA processor; the double-rate synchronous dynamic random access memory is used for storing the original image, the denoised image and the sRGB image.
4. The single-light-source full-color camera according to claim 3, wherein the micro-optic algorithm FPGA processor specifically comprises: the system comprises an image interface module and an algorithm processing module;
the image interface module is connected with the visible light sensor and used for receiving the original image and transmitting the original image to the double-rate synchronous dynamic random access memory;
the algorithm processing module is connected with the double-rate synchronous dynamic random access memory and is used for carrying out noise estimation, denoising and demosaicing on the original image and transmitting the denoised image and the sRGB image to the double-rate synchronous dynamic random access memory.
5. The single-light-source full-color camera according to claim 4, wherein the micro-optic algorithm FPGA processor further comprises: an internal bus;
the image interface module, the algorithm processing module and the double-rate synchronous dynamic random access memory are communicated through the internal bus.
6. The single-light-source full-color camera according to claim 5, wherein the image interface module specifically comprises: an MIPI-CSI interface, an MIPI-ISP interface and an HDMI interface;
one end of the MIPI-CSI interface is connected with the visible light sensor, and the other end of the MIPI-CSI interface is connected with the double-rate synchronous dynamic random access memory through the internal bus; the MIPI-CSI interface is used for receiving the original image and inputting the original image into the double-rate synchronous dynamic random access memory;
one end of the MIPI-ISP interface is connected with the image signal processing chip; the other end of the MIPI-ISP interface is connected with the double-rate synchronous dynamic random access memory through the internal bus; the MIPI-ISP interface is used for extracting the denoised image according to the cache address and inputting the denoised image data to the image signal processing chip;
one end of the HDMI is respectively connected with the algorithm processing module and the double-rate synchronous dynamic random access memory through the internal bus; the other end of the HDMI is connected with a display device; the HDMI is used for outputting the sRGB image.
7. The single-light-source full-color camera according to claim 1, wherein the image signal processing chip is configured to process the de-noised image, and specifically comprises: automatic exposure control, automatic gain control, automatic white balance, color correction, lens shading, Gamma correction and dead pixel removal.
8. The single-light-source full-color camera according to claim 6, wherein the algorithm processing module specifically comprises: a NoiseES submodule, a DeNoise submodule and a DeMosic submodule; the NoiseES submodule, the DeNoise submodule and the DeMosic submodule are connected in sequence;
the NoiseES submodule is connected with the double-rate synchronous dynamic random access memory; the NoiseES submodule is used for extracting the original image according to the cache address, carrying out noise estimation on the original image and determining the noise degree of the original image;
the DeNoise submodule is used for carrying out denoising processing on the original image according to the noise degree;
and the DeMosic submodule is used for demosaicing the de-noised image and outputting an sRGB image.
9. The single light source full color camera according to claim 8, wherein the noise level comprises: slight, moderate, and severe noise.
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