CN115360231B - Reverse conducting insulated gate bipolar transistor with low hysteresis voltage and preparation process thereof - Google Patents

Reverse conducting insulated gate bipolar transistor with low hysteresis voltage and preparation process thereof Download PDF

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CN115360231B
CN115360231B CN202211039857.5A CN202211039857A CN115360231B CN 115360231 B CN115360231 B CN 115360231B CN 202211039857 A CN202211039857 A CN 202211039857A CN 115360231 B CN115360231 B CN 115360231B
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collector
field stop
stop layer
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CN115360231A (en
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刘斯扬
李仁伟
吴团庄
魏家行
孙伟锋
时龙兴
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Southeast University-Wuxi Institute Of Integrated Circuit Technology
Southeast University
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Southeast University
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

A reverse-conduction insulated gate bipolar transistor with low hysteresis voltage and a preparation process thereof, wherein the transistor comprises: the collector is arranged at the bottom of the device, the collector region comprises P+ collector regions and N+ short-circuit regions which are alternately arranged, an N-type field stop layer is arranged above the collector region, an N-type drift region is arranged above the field stop layer, grooves which are arranged in a one-dimensional array are formed in the upper surface of the drift region, a gate oxide layer and a polysilicon gate are arranged in the grooves, the gate oxide layer is arranged between the polysilicon gate and the inner wall of the grooves, a P-type body region is arranged above the drift region, and the P-type body region is arranged between two adjacent grooves and is in contact with the side walls of the grooves; an N+ emission region and a P+ contact region are arranged on the P-type body region, an emitter is connected to the contact region, and insulating medium layers are arranged on two sides of the emitter. The preparation process is characterized in that the field stop layer is formed by back hydrogen injection, and the back structures are all made by adopting a laser annealing process.

Description

Reverse conducting insulated gate bipolar transistor with low hysteresis voltage and preparation process thereof
Technical Field
The invention mainly relates to the technical field of power semiconductor devices, in particular to a reverse conducting insulated gate bipolar transistor with low hysteresis voltage and a preparation process thereof.
Background
Along with the increasing demands of application fields such as traffic, power generation, power transmission, household appliances and the like in the modern society on power semiconductor devices, an Insulated Gate Bipolar Transistor (IGBT) combining the voltage control characteristic of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with the high current gain of a bipolar transistor (BJT) has the advantages of small conduction voltage drop, simple driving circuit, easiness in control and the like, and plays an important role in the middle-high power electric field. The traditional IGBT does not have reverse conduction capability, so that the IGBT and the freewheeling diode are often required to be connected in reverse parallel for use in practical application, thereby realizing bidirectional conduction and freewheeling protection of current, but the proposal causes large device volume, high packaging cost and very limited application.
To address this problem, researchers have proposed reverse-conducting IGBTs. As shown in fig. 1, compared with the conventional IGBT, the reverse conducting IGBT has an N-type short circuit region embedded in the emitter (E) of the IGBT as the cathode of the freewheeling diode, and a P-type body region of the collector (C) as the anode of the freewheeling diode, integrating the body diode, thereby achieving the capability of reverse conduction. And the IGBT and the freewheeling diode are integrated and packaged on the same chip, so that the chip area and the packaging cost are greatly saved, and meanwhile, the wiring process and the manufacturing difficulty are reduced. Compared with the traditional IGBT, the reverse-conduction type IGBT has the advantages that due to the existence of an N-type short circuit region of the structure, the phenomenon of turn-on voltage turn-back (snapback) can occur in the initial stage of conduction, as shown in fig. 2, a dotted line in the diagram is a traditional forward conduction curve of the IGBT, and a solid line in the diagram is a forward conduction curve of the phenomenon of turn-on voltage turn-back (snapback) generated by the traditional reverse-conduction type IGBT. The reason for this phenomenon is explained as follows, as shown in fig. 3, when the forward conduction is just turned on, the forward bias of the gate promotes the inversion of electrons to form a channel, the electron current of the n+ emission region reaches the N-type drift region through the electron channel, and when the electron current is small, the lateral voltage drop generated by the electrons flowing through the N-type field stop layer is smaller than the PN junction barrier between the p+ collection region and the N-type field stop layer due to the built-in barrier of the PN junction between the back p+ collection region and the N-type field stop layer, and therefore, the electrons all flow to the collector metal layer through the n+ short-circuit region of the back. On the other hand, because the PN junction between the P+ collector region and the N-type field stop layer cannot be opened, hole carriers of the P+ collector region cannot enter the N-type drift region, and the device works in a MOS mode of unipolar (electron) conduction. As shown in fig. 2, the conventional reverse conducting IGBT may exhibit a large on-resistance and on-voltage drop at the initial stage of the turn-on.
Because electrons flow through the N-type field stop layer to generate a certain voltage drop, a certain potential difference is generated between the P+ collector region and the N-type field stop layer, when the electron current is gradually increased, the potential difference is also gradually increased and finally exceeds the starting voltage of 0.7V of the PN junction, so that the PN junction between the P+ collector region and the N-type field stop layer is started. Meanwhile, holes in the P+ collector region are injected into the N-type drift region, when a large number of electrons and hole carriers occur in the N-type drift region, the BJT is turned on to generate a conductivity modulation effect, so that the resistance in the N-type drift region is greatly reduced, and further the on-resistance and the on-voltage drop of the reverse conducting IGBT are reduced, as shown in fig. 2, the result is reflected on a forward conducting curve, so that a voltage folding (snapback) phenomenon that the voltage is continuously reduced along with the increase of current can occur, at the moment, bipolar carriers (electrons and holes) are all involved in conduction, the device is similar to an IGBT in working mode, compared with an MOS mode, the on-resistance is smaller, and the device starts to enter the IGBT mode.
The snapback phenomenon seriously affects the reliability of the reverse-conduction IGBT in actual use, and for the reverse-conduction IGBT with a large chip area or a plurality of parallel reverse-conduction IGBTs, the PN junction between the P+ collector region on the back of the chip and the N-type field stop layer is inconsistent in opening position, so that the device can generate local current concentration in the use process, and further the device is thermally broken down due to overlarge current, and even the device cannot enter an IGBT mode in severe cases.
As shown in fig. 4, according to the equivalent circuit model of the conventional reverse conducting IGBT, a physical expression of the hysteresis voltage V sb can be obtained:
Wherein Rch, rdrift, rn respectively represents the channel resistance, the drift region resistance and the N-type field stop layer transverse resistance of the device, and V PN is the built-in potential of a PN junction formed by the P+ collector region and the N+ short circuit region on the back of the device. It should be noted that, for the conventional reverse conducting IGBT, the N-type field stop layer lateral resistance Rn is the collector short-circuit resistance.
According to the physical expression of the hysteresis voltage V sb, it is not difficult to find that the hysteresis voltage V sb can be reduced by reducing Rch, rdrift, V PN or increasing Rn, so that the snapback phenomenon of the conventional reverse conducting IGBT can be suppressed. In general, V PN is difficult to change, and to reduce Rch or Rdrift, the structure of the device needs to be improved, and the value of the device is closely related to the structural parameters, and certain requirements are also required for the actual manufacturing process. In comparison, the method for increasing Rn is simpler. Rn can be expressed approximately as:
where ρ is the resistivity, l P+ is the length of the p+ collector region, w is the width of the device, and d is the thickness of the field stop layer.
The device width is generally determined by the rated current; the thickness of the field stop layer is relatively limited by the actual manufacturing process; one common scheme in the prior art is to increase l P+ to prolong the electron current path of electrons in an N-type field stop layer, so as to increase the transverse resistance Rn of the electron current in the field stop layer, but an overlong P+ collector region not only can influence the turn-off characteristic of a device, but also can influence the uniformity of current distribution in the device, thereby increasing the local aggregation of current and reducing the reliability of the device; so it is relatively easy to change the resistivity ρ, which can be expressed as n-type semiconductor:
Where n is the carrier concentration, q is the charge amount, and μ n is the electron mobility. When the doping concentration N D of the field stop layer is less than 10 17cm-3 (lightly doped), μ n can be considered temperature dependent only, whereas the carrier concentration n≡n D. Therefore, under the condition of unchanged temperature, the resistivity rho can be effectively improved by reducing N D, so that the transverse resistance Rn of the N-type field stop layer is increased, namely the collector short-circuit resistance is increased, and finally the purpose of reducing the hysteresis voltage V sb is achieved.
For a vertical power device, the introduction of the N-type field stop layer ensures that the thickness cost and the turn-off loss are reduced while the original voltage endurance capability of the device is maintained. Therefore, the design of the reverse conducting IGBT should consider the voltage withstanding requirement, and N D is not easy to be excessively reduced to optimize the hysteresis voltage.
Therefore, an improved technical scheme for balancing performances in various aspects in the prior art is needed, and on the basis of guaranteeing the voltage endurance capability and the reverse conduction capability of the device, the snapback phenomenon in the forward conduction process of the reverse conduction type IGBT can be effectively inhibited.
Disclosure of Invention
The invention provides a reverse conducting insulated gate bipolar transistor with low hysteresis voltage and a preparation process thereof aiming at the problems. Compared with the traditional reverse conducting IGBT, the invention effectively inhibits the phenomenon of voltage folding (snapback), improves the uniformity of current distribution in the device, and improves the reliability of the device.
The invention provides the following structural technical scheme:
the invention relates to a reverse conducting insulated gate bipolar transistor with low hysteresis voltage, which comprises: the collector metal layer is positioned at the bottom of the device, the collector metal layer is provided with a collector region, the collector region comprises P+ collector regions and N+ short-circuit regions which are alternately arranged, an N-type field stop layer is arranged above the collector region, an N-type drift region is arranged above the N-type field stop layer, grooves which are arranged according to a one-dimensional array are arranged on the upper surface of the N-type drift region, a gate oxide layer and a polysilicon gate are arranged in the grooves, the gate oxide layer is positioned between the polysilicon gate and the inner wall of the grooves, a P-type body region is arranged above the N-type drift region, and the P-type body region is positioned between two adjacent grooves and is in contact with the side walls of the grooves; an N+ emission region and a P+ type contact region are arranged on the P type body region, an emitter metal layer is connected to the P+ type contact region, insulating medium layers are arranged on two sides of the emitter metal layer, and an N-high resistance region is arranged between the N type field stop layer and the collector region.
The invention relates to a preparation process of a reverse conducting insulated gate bipolar transistor with low hysteresis voltage,
The first step: selecting an N-type silicon material as a substrate silicon wafer, and forming an N-type drift region by using the N-type silicon material;
And a second step of: etching a groove on the upper surface of the N-type drift region;
and a third step of: growing a gate oxide layer on the inner side of the groove etched on the upper surface of the N-type drift region, and then depositing heavily doped polysilicon to form a polysilicon gate;
fourth step: an ion implantation or diffusion method is used for annealing on the upper surface of the N-type drift region, and a P-type body region, an N+ emission region and a P+ type contact region are formed in sequence;
fifth step: depositing an insulating dielectric layer on the upper surface of the device, wherein the insulating dielectric layer can be boron-phosphorus-silicon glass, etching a contact hole on the insulating dielectric layer, and depositing to form an emitter metal layer;
sixth step: turning over the device, carrying out hydrogen ion implantation on the back surface and carrying out laser annealing to form an N-type field stop layer with the distance between the lower surface and the bottom of the device of 4-6 mu m and the thickness of 2-3 mu m;
seventh step: carrying out local P-type ion implantation with the ion implantation depth of 2-3 mu m on the back of the device by utilizing a photoetching plate, and forming a P+ collector region after activation and annealing by adopting a laser annealing process;
eighth step: carrying out local N-type ion implantation on the back of the device by utilizing a photoetching plate, wherein the junction depth is 0.5-1 mu m, and carrying out activation and annealing by adopting a laser annealing process to form an N+ short-circuit region;
Ninth step: and depositing a collector metal layer on the back of the device, and forming ohmic contact with the collector region comprising the P+ collector region and the N+ short-circuit region.
The invention relates to a preparation process of a reverse conducting insulated gate bipolar transistor with low hysteresis voltage,
The first step: selecting an N-type silicon material as a substrate silicon wafer, and forming an N-type drift region by using the N-type silicon material;
And a second step of: etching a groove on the upper surface of the N-type drift region;
and a third step of: growing a gate oxide layer on the inner side of the groove etched on the upper surface of the N-type drift region, and then depositing heavily doped polysilicon to form a polysilicon gate;
fourth step: an ion implantation or diffusion method is used for annealing on the upper surface of the N-type drift region, and a P-type body region, an N+ emission region and a P+ type contact region are formed in sequence;
fifth step: depositing an insulating dielectric layer on the upper surface of the device, wherein the insulating dielectric layer can be boron-phosphorus-silicon glass, etching a contact hole on the insulating dielectric layer, and depositing to form an emitter metal layer;
sixth step: turning over the device, carrying out hydrogen ion implantation on the back surface and carrying out laser annealing to form an N-type field stop layer with the distance between the lower surface and the bottom of the device of 4-6 mu m and the thickness of 2-3 mu m;
Seventh step: carrying out local P-type ion implantation with the ion implantation depth of 2-3 mu m on the back of the device by utilizing a photoetching plate, carrying out local P-type ion implantation with the junction depth of 1-2 mu m on the back of the device by utilizing the photoetching plate, and carrying out activation and annealing by adopting a laser annealing process to form an L-shaped P+ collector region;
eighth step: carrying out local N-type ion implantation on the back of the device by utilizing a photoetching plate, wherein the junction depth is 0.5-1 mu m, and carrying out activation and annealing by adopting a laser annealing process to form an N+ short-circuit region;
Ninth step: and depositing a collector metal layer on the back of the device, and forming ohmic contact with the collector region comprising the P+ collector region and the N+ short-circuit region.
Compared with the prior art, the invention has the following advantages:
1. As shown in fig. 5, the reverse conducting IGBT device 002 according to the present invention has a deeper N-type field stop layer 3 provided on the back surface of the device, and an N-high resistance region 13 is introduced between the N-type field stop layer 3 and the collector region 2, so as to obtain a high-resistance electron current path flowing to the n+ short circuit region 22, further increase the collector short circuit resistance, and effectively inhibit the snapback phenomenon.
As shown in fig. 6, when the forward conduction is just on, the forward bias of the device front MOS gate 7 promotes the inversion of electrons in the P-type body region 8 to form a conductive channel on the outer sidewall of the trench 5, and the electron current in the n+ emission region 9 passes through the conductive channel on both sides of the P-type body region 8 to reach the N-type drift region 4, and since the doping concentration of the N-type field stop layer 3 is greater than that of the N-type high resistance region 13, i.e. the on-resistance of the N-type field stop layer 3 is smaller than that of the N-type high resistance region 13, most of the electron current in the N-type drift region 4 passes through the N-type field stop layer 3 transversely, then flows through the N-high resistance region 13 longitudinally, and finally reaches the n+ short circuit region 22 (as indicated by the dotted arrow in fig. 6).
Compared with the traditional reverse-conduction IGBT device 001, the reverse-conduction IGBT device 002 provided by the invention has the advantages that electron current injected into the drift region 4 from the front MOS channel can reach the N+ short-circuit region 22 only after passing through the N-type field stop layer 3 and flowing through the N-high resistance region 13, so that a larger collector short-circuit resistance is obtained, the hysteresis voltage is effectively reduced, and the forward-opening voltage folding problem is greatly improved. On the other hand, part of the electron current longitudinally passes through the N-type field stop layer 3 and then transversely flows through the N-high resistance region 13 to finally reach the N+ short circuit region 22, and as the on-resistance of the N-high resistance region 13 is larger than that of the N-type field stop layer 3, the electron current in the N-high resistance region 13 generates larger transverse voltage drop and more easily exceeds the PN junction barrier between the N-high resistance region 13 and the P+ collector region 21, so that a PN junction formed between the N-high resistance region 13 and the P+ collector region 21 can be opened when the electron current is smaller, the device enters an IGBT mode earlier, and the snapback phenomenon in the forward conduction process of the traditional reverse conduction type IGBT is effectively inhibited.
2. As shown in fig. 7, the reverse conducting IGBT device 003 according to the present invention adopts the T-shaped N-high resistance region 13, and forms a self-adjusting depletion region in the narrow N-high resistance region between two adjacent p+ collector regions 21, and the on-resistance (Rep) of the self-adjusting depletion region increases during forward conduction, and the on-resistance (Rep) of the self-adjusting depletion region decreases during reverse conduction, so that the forward and reverse conduction performances of the device can be optimized simultaneously.
In the initial forward conduction stage, as shown in fig. 8, the forward bias of the device front MOS gate 7 promotes the inversion of electrons in the P-type body region 8 to form a conductive channel at the outer side wall of the trench 5, and the electron current in the n+ emitter region 9 reaches the N-type drift region 4 through the conductive channel at both sides of the P-type body region 8, and the N-type field stop layer 3 has a doping concentration greater than that of the N-high resistance region 13, i.e., the on-resistance of the N-type field stop layer 3 is smaller than that of the N-high resistance region 13, so that most of the electron current in the N-type drift region 4 will pass through the N-type field stop layer 3 transversely, then flow longitudinally through the T-shaped N-high resistance region 13 and its self-regulating depletion region, and finally reach the n+ short circuit region 22. At this time, since the p+ collector region 21 is forward biased, the PN junction formed between the p+ collector region 21 and the N-high resistance region 13 is forward biased, in which the diffusion current plays a dominant role, the depletion layer narrows, and the PN junction exhibits low resistance, so electrons in the narrow self-adjusting depletion region are rapidly depleted, thereby reducing the doping concentration of the self-adjusting depletion region, further increasing the on-resistance (Rep) of the self-adjusting depletion region, providing a high-resistance electron current path, and obtaining a larger collector short-circuit resistance, which helps to reduce the hysteresis voltage and improve the voltage turn-back problem of forward opening. When the diode is reversely conducted, the p+ type contact region 10 is used as an anode of the freewheeling diode, the n+ short-circuit region 22 is used as a cathode of the freewheeling diode, the p+ collecting region 21 is added with negative bias voltage, PN junction formed between the p+ collecting region 21 and the N-high resistance region 13 is reversely biased, drift current therein plays a leading role, the depletion layer is widened, the PN junction presents high resistance, holes in the narrow self-regulating depletion region are rapidly depleted, holes injected into the N-type drift region 4 from the P type body region 8 pass through the N-type field stop layer 3 and the N-high resistance region 13, the holes are adsorbed on the interface between the N-high resistance region 13 and the p+ collecting region 21, and the product of doping concentration of the electrons and the holes is fixed, which is equivalent to improving the electron doping concentration of the self-regulating depletion region, thereby reducing the on-resistance (Rep) of the self-regulating depletion region, providing a low-resistance electron current path, which is helpful for reducing forward conduction voltage drop of the diode, and improving reverse conduction performance of the diode.
Meanwhile, the forward and reverse conduction performance of the device 003 has a large correlation with the pitch between two adjacent p+ collector regions 21 (i.e., self-adjusting depletion region width). The smaller the width of the self-regulating depletion region, the larger the on-resistance (Rep) of the self-regulating depletion region is, which is helpful to increase the collector short-circuit resistance, so that the hysteresis voltage can be reduced, the forward conduction performance of the device is optimized, but the forward conduction voltage drop of the diode is increased, and the reverse conduction performance of the device is reduced; the larger the width of the self-regulating depletion region, the smaller its on-resistance (Rep), which helps to reduce the forward conduction voltage drop of the diode, thus improving the reverse conduction performance of the device, but this also reduces the collector shorting resistance, resulting in an increase in the hysteretic voltage, thus reducing the forward conduction performance of the device.
Compared with the reverse conducting IGBT device 002, in the forward conducting and reverse conducting processes, the electron current and the hole current both obtain favorable on-resistance (Rep) through the self-regulating depletion region in the N-high resistance region 13, so that the collector short-circuit resistance in forward conducting can be further increased by reducing the distance between two adjacent P+ collector regions 21 by sacrificing part of reverse conducting performance of the device, the forward voltage drop of the device 003 at the diode similar to the device 002 is realized, the hysteresis voltage is further reduced, and the voltage retracing problem of the reverse conducting IGBT is effectively improved.
3. As shown in fig. 10, the reverse conducting IGBT device 004 provided by the invention adopts the L-shaped p+ collector region 21, and a wider n+ short circuit region 22 is obtained between two adjacent L-shaped p+ collector regions 21, so that the effective area of the diode cathode in reverse conduction is increased, the conductivity modulation effect is enhanced, the forward conduction voltage drop of the diode is reduced, and the reverse conduction performance of the device is improved. Meanwhile, the device 004 adopts the N-high resistance region 13 in the shape of an inverted I, so that on one hand, the effective area of electron injection of the N+ short circuit region 22 in reverse conduction is ensured, and on the other hand, the overall thickness of the N-high resistance region 13 is increased, thereby further increasing the collector short circuit resistance, being beneficial to reducing the hysteresis voltage and inhibiting the snapback phenomenon.
As shown in fig. 11, in the initial forward conduction stage, the forward bias of the device front MOS gate 7 promotes the inversion of electrons in the P-type body region 8 to form a conductive channel at the outer side wall of the trench 5, and the electron current in the n+ emitter region 9 reaches the N-type drift region 4 through the conductive channel at both sides of the P-type body region 8, and since the doping concentration of the N-type field stop layer 3 is greater than that of the N-type high-resistance region 13, i.e., the on-resistance of the N-type field stop layer 3 is smaller than that of the N-type high-resistance region 13, most of the electron current in the N-type drift region 4 will pass through the N-type field stop layer 3 transversely, then longitudinally flow through the N-type high-resistance region 13 and its self-regulating depletion region in the inverted i shape, and finally reach the n+ short circuit region 22.
Compared with the reverse-conduction IGBT device 003, in the forward conduction process of the reverse-conduction IGBT device 004 provided by the invention, the N-high resistance region 13 in the shape of the inverted I increases the overall thickness compared with the N-high resistance region 13 in the shape of the T, and higher on-resistance is provided, so that the collector short-circuit resistance is further increased, the hysteresis voltage is reduced, and the snapback phenomenon is restrained.
As shown in fig. 12, when the reverse conduction is performed, the p+ type contact region 10 is used as the anode of the freewheeling diode, the n+ short-circuit region 22 is used as the cathode of the freewheeling diode, the electrons in the n+ short-circuit region 22 and the holes in the P type body region 8 are both injected into the N-type drift region 4, and a conductivity modulation effect, that is, a large injection effect of carriers, occurs in the N-type drift region 4, and since a large amount of carriers are accumulated in the N-type drift region 4, the on-resistance is greatly reduced, and the device has a low-resistance characteristic at this time, so that the reverse conduction type IGBT device is ensured to have a better reverse conduction capability.
When the reverse conducting type IGBT device 003 is conducted reversely, the quantity of electrons injected into the N-type drift region 4 is limited due to the fact that the electron injection area of the N+ short circuit region 22 is small, and therefore the generated conductivity modulation effect is limited. Compared with the reverse conducting IGBT device 003, the effective area of the N+ short-circuit region 22 is increased in the reverse conducting process of the reverse conducting IGBT device 004 provided by the invention, the conducting modulation effect is enhanced, so that the forward conducting voltage drop of the diode is reduced, the reverse conducting performance of the device is improved, the distance between two adjacent L-shaped P+ collector regions 21 can be reduced by sacrificing the raised reverse conducting performance, the collector short-circuit resistance in forward conducting is further increased, namely the forward voltage drop of the device 004 in the diode similar to the device 003 is realized, the hysteresis voltage is further reduced, and the voltage folding problem of the reverse conducting IGBT is effectively improved.
Therefore, compared with the T-shaped N-high resistance region 13 adopted by the reverse-conduction IGBT device 003, the reverse-conduction IGBT device 004 provided by the invention has the advantages that the reverse I-shaped N-high resistance region 13 is adopted, and the forward and reverse conduction performances of the device are both improved. On one hand, the overall thickness of the N-high resistance region 13 is increased, and the collector short-circuit resistance in forward conduction is further increased, so that the hysteresis voltage is reduced, and the voltage folding problem is improved; on the other hand, the effective area of electron injection of the N+ short circuit region 22 in reverse conduction is increased, the conductivity modulation effect is enhanced, so that the forward conduction voltage drop of the diode is reduced, the reverse conduction performance of the device is improved, the collector short circuit resistance in forward conduction can be further increased by sacrificing the improved reverse conduction performance, the forward voltage drop of the diode close to the devices 001, 002 and 003 is finally realized, the hysteresis voltage is greatly reduced, and the snapback phenomenon of the reverse conduction IGBT device is almost eliminated.
4. As shown in fig. 13, the present invention adopts an H ion back implantation process to form a deeper N-type field stop layer 3 to obtain a thicker N-high resistance region 13. Compared with the conventional reverse-conduction IGBT process, the N-type field stop layer 3 is formed by phosphorus injection, and H ions can be implanted to a larger depth under the same implantation energy. However, too deep N-type field stop layer 3 will generate too large forward voltage drop of the diode, seriously sacrificing reverse conduction performance of the device, and deeper N-type field stop layer 3 will greatly increase difficulty in process implementation. Therefore, the implantation depth of the H ions needs to be reasonably adjusted to ensure the reverse conduction capability of the device. Meanwhile, attention is paid to the doping concentration of H ions, and the lightly doped N-type field stop layer 3 is beneficial to increasing the collector short-circuit resistance and reducing the hysteresis voltage, but too low doping concentration is insufficient to obtain the required withstand voltage and increases the difficulty of optimizing the forward saturation voltage drop. Therefore, the doping concentration of the N-type field stop layer 3 can be appropriately optimized on the basis of ensuring the device withstand voltage.
5. As shown in fig. 13, the present invention adopts a laser annealing back surface process to activate and anneal the N-type field stop layer 3, the p+ collector region 21 and the n+ short circuit region 22 to obtain high activation, diffusion-free performance of the back surface structure. Compared with the common thermal annealing in the traditional reverse-conduction IGBT process, the annealing time of the laser annealing process is very short. Therefore, the laser annealing process is an ideal choice for performing backside processing without affecting the front side structure already present in the device process flow. The laser pulse of the laser can be utilized to enable the back surface to reach the required melting temperature within 10ns, and after the laser pulse is ended, the temperature of the back surface of the device is rapidly reduced due to heat conduction of the silicon wafer, and the temperature of the front surface cannot exceed 100 ℃. Even if thinner wafers or larger laser energy are used, the front surface temperature will be greater, but the duration of the temperature rise will not exceed 1ms, so the use of a laser annealed back side process will not affect the front side MOS structure of the reverse-conducting IGBT. Although the laser annealing process can reach very high temperature, the laser pulse time is very short, so that the N-type field stop layer 3 and the collector region 2 on the back of the device can be kept highly activated, and meanwhile, little diffusion occurs.
Drawings
Fig. 1 is a schematic diagram of a reverse-conducting IGBT.
Fig. 2 is a schematic diagram of forward turn-on current-voltage curves of a conventional IGBT and a reverse-conduction IGBT.
Fig. 3 is a schematic cross-sectional structure of a conventional reverse conducting IGBT device 001.
Fig. 4 is an equivalent circuit schematic diagram of a conventional reverse conducting IGBT.
Fig. 5 is a schematic cross-sectional structure of a reverse conducting IGBT device 002 according to the present invention.
Fig. 6 is a schematic diagram of a forward conduction electron current path and a collector short circuit resistance of the reverse conducting IGBT device 002 according to the present invention.
Fig. 7 is a schematic cross-sectional structure of a reverse conducting IGBT device 003 according to the present invention.
Fig. 8 is a schematic diagram of a forward conduction electron current path and a collector short circuit resistance of the reverse conducting IGBT device 003 according to the present invention.
Fig. 9 is a schematic cross-sectional structure of the cavity 211 in the p+ collector region 21.
Fig. 10 is a schematic cross-sectional structure of a reverse conducting IGBT device 004 according to the present invention.
Fig. 11 is a schematic diagram of a forward conduction electron current path and a collector short circuit resistance of the reverse conducting IGBT device 004 according to the present invention.
Fig. 12 is a schematic diagram of electron and hole injection during reverse conduction of the reverse conduction IGBT device 004 according to the present invention.
Fig. 13 is a schematic diagram of main manufacturing process steps of a reverse conducting type IGBT device 004 according to the present invention, in which fig. 13-1 defines a silicon substrate as a drift region, fig. 13-2 etches a trench, fig. 13-3 grows a gate oxide and deposits a polysilicon gate, fig. 13-4 implants and anneals to form a P-type body region, an n+ emitter region and a p+ type contact region, fig. 13-5 deposits a dielectric layer and an emitter metal layer, fig. 13-6 carries out back side hydrogen implantation and laser annealing to form an N-type field stop layer, fig. 13-7 carries out back side first P-type ion implantation to form an upper portion of a p+ collector region, fig. 13-8 carries out back side second P-type ion implantation and laser annealing to form an L-shaped p+ collector region, fig. 13-9 carries out back side N-type ion implantation and laser annealing to form an n+ short circuit region, and fig. 13-10 deposits a collector metal layer.
Fig. 14 is a diagram showing forward and reverse conduction characteristics and a partial enlarged view of a conventional reverse-conduction IGBT device 001 and a reverse-conduction IGBT device 002 according to the present invention, which are subjected to comparative simulation by a semiconductor device simulation software Sentaurus TCAD.
Fig. 15 is a diagram showing the forward and reverse turn-on characteristics and a partial enlarged view of the reverse conducting IGBT device 002 according to the present invention and the reverse conducting IGBT device 003 according to the present invention, which are subjected to comparative simulation by the semiconductor device simulation software Sentaurus TCAD.
Fig. 16 is a diagram showing a forward and reverse turn-on characteristic curve and a partial enlarged view of a reverse conducting type IGBT device 003 according to the present invention and a reverse conducting type IGBT device 004 according to the present invention, which are subjected to comparative simulation by a semiconductor device simulation software Sentaurus TCAD.
Detailed Description
Example 1
A low hysteresis voltage reverse conducting insulated gate bipolar transistor comprising: a collector metal layer 1 positioned at the bottom of the device, a collector region 2 is arranged above the collector metal layer 1, the collector region 2 comprises P+ collector regions 21 and N+ short-circuit regions 22 which are alternately arranged, an N-type field stop layer 3 is arranged above the collector region 2, an N-type drift region 4 is arranged above the N-type field stop layer 3, grooves 5 which are arranged in a one-dimensional array are arranged on the upper surface of the N-type drift region 4, a gate oxide layer 6 and a polysilicon gate 7 are arranged in the grooves 5, the gate oxide layer 6 is positioned between the polysilicon gate 7 and the inner wall of the grooves 5, a P-type body region 8 is arranged above the N-type drift region 4, and the P-type body region 8 is positioned between two adjacent grooves 5 and is in contact with the side walls of the grooves 5; an N+ emission region 9 and a P+ type contact region 10 are arranged on the P type body region 8, an emitter metal layer 12 is connected to the P+ type contact region 10, insulating medium layers 11 are arranged on two sides of the emitter metal layer 12, and an N-high resistance region 13 is arranged between the N type field stop layer 3 and the collector region 2.
In this embodiment, the depth of the p+ collector region 21 is greater than the depth of the n+ short-circuit region 22 and a recess is formed above the n+ short-circuit region 22, the N-high resistance region 13 extends, fills the recess, and the extension of the N-high resistance region 13 is a self-adjusting depletion region 131; a cavity 211 is formed on the p+ collector region 21, the cavity 211 abuts against the side surface of the n+ short-circuit region 22, and the height of the cavity 211 is greater than that of the n+ short-circuit region 22; the n+ short-circuit region 22 extends laterally and passes through the cavity 211 and ends in the p+ collector region 21, and the N-high resistance region 13 extends again and fills the cavity 211, so that the re-extending portion 132 of the N-high resistance region 13 covers the laterally extended n+ short-circuit region 22; the N-type field stop layer 2 is a buffer area formed by injecting H ions into the back, the doping concentration of the N-type field stop layer 2 is generally 1 multiplied by 10 15～1×1016cm-3, and the thickness is 2-3 mu m; the doping concentration of the N-high resistance region 13 is lower than that of the N-type field stop layer 3, the doping concentration of the N-high resistance region 13 is equal to that of the N-type drift region 4, and the thickness of the N-high resistance region 13 is 1-3 mu m; the N-type drift region 4 is an N-type monocrystalline silicon wafer substrate, and the resistivity is 90 omega cm; the junction depth of the n+ short circuit region 22 is 0.5 to 1 μm.
Example 2
A preparation process of a reverse conducting insulated gate bipolar transistor with low hysteresis voltage,
The first step: selecting an N-type silicon material as a substrate silicon wafer, and forming an N-type drift region 4 by using the N-type silicon material;
And a second step of: etching a groove 5 on the upper surface of the N-type drift region 4;
And a third step of: growing a gate oxide layer 6 on the inner side of the groove 5 etched on the upper surface of the N-type drift region 4, and then depositing heavily doped polysilicon to form a polysilicon gate 7; in the present embodiment, the gate oxide layer 6 has a thickness of The doping concentration of the heavy doping is 1 multiplied by 10 20cm-3;
fourth step: forming a P-type body region 8, an N+ emission region 9 and a P+ type contact region 10 on the upper surface of the N-type drift region 4 by utilizing an ion implantation or diffusion method and annealing;
Fifth step: depositing an insulating dielectric layer 11 on the upper surface of the device, wherein the insulating dielectric layer material can be borophosphosilicate glass, etching a contact hole on the insulating dielectric layer material, and depositing to form an emitter metal layer 12;
sixth step: turning over the device, carrying out hydrogen ion implantation on the back surface and carrying out laser annealing to form an N-type field stop layer 3 with the distance between the lower surface and the bottom of the device of 4-6 mu m and the thickness of 2-3 mu m;
seventh step: performing local ion implantation of P type (such as boron, aluminum, gallium and the like) with the ion implantation depth of 2-3 mu m on the back of the device by using a photoetching plate, and forming a P+ collector region 21 after activation and annealing by using a laser annealing process;
Eighth step: carrying out local N-type (such as phosphorus, arsenic and the like) ion implantation on the back of the device by utilizing a photoetching plate, wherein the junction depth is 0.5-1 mu m, and carrying out activation and annealing by adopting a laser annealing process to form an N+ short-circuit region 22, wherein the laser annealing process can realize high activation and diffusion-free performance of a back structure;
Ninth step: a collector metal layer 1 is deposited on the back of the device and forms an ohmic contact with collector region 2 comprising p+ collector region 21 and n+ short-circuit region 22.
In the embodiment, the resistivity of the N-type silicon material serving as a substrate silicon wafer is 90 Ω & cm, the implantation dosage of hydrogen ion implantation is 1×10 17～1×1020cm-3, the implantation energy is 300-500 KeV, and the depth and thickness of the N-type field stop layer 3 are controlled by controlling the implantation energy, the laser annealing temperature and the annealing time; the implantation dosage of the P-type ion implantation with the ion implantation depth of 2-3 mu m is 1 multiplied by 10 12～1×1014cm-3, and the implantation energy is 1-2 MeV; the implantation dose of N-type ion implantation is 5×10 13～5×1015cm-3, and the implantation energy is 20-80 KeV.
Example 3
A preparation process of a reverse conducting insulated gate bipolar transistor with low hysteresis voltage,
The first step: selecting an N-type silicon material as a substrate silicon wafer, and forming an N-type drift region 4 by using the N-type silicon material;
And a second step of: etching a groove 5 on the upper surface of the N-type drift region 4;
And a third step of: growing a gate oxide layer 6 on the inner side of the groove 5 etched on the upper surface of the N-type drift region 4, and then depositing heavily doped polysilicon to form a polysilicon gate 7; in the present embodiment, the gate oxide layer 6 has a thickness of The doping concentration of the heavy doping is 1 multiplied by 10 20cm-3;
fourth step: forming a P-type body region 8, an N+ emission region 9 and a P+ type contact region 10 on the upper surface of the N-type drift region 4 by utilizing an ion implantation or diffusion method and annealing;
Fifth step: depositing an insulating dielectric layer 11 on the upper surface of the device, wherein the insulating dielectric layer material can be borophosphosilicate glass, etching a contact hole on the insulating dielectric layer material, and depositing to form an emitter metal layer 12;
sixth step: turning over the device, carrying out hydrogen ion implantation on the back surface and carrying out laser annealing to form an N-type field stop layer 3 with the distance between the lower surface and the bottom of the device of 4-6 mu m and the thickness of 2-3 mu m;
seventh step: carrying out local ion implantation with the depth of 2-3 mu m on the back of the device by utilizing a photoetching plate, carrying out local P-type ion implantation with the junction depth of 1-2 mu m on the back of the device by utilizing the photoetching plate, and carrying out activation and annealing by adopting a laser annealing process to form an L-shaped P+ collector region 21, wherein the implanted ions can be boron, aluminum, gallium and the like, the ion implantation depth is the distance from the peak of the implanted impurity concentration to the bottom of the device, the junction depth is the distance from the bottom of the device to the diffusion layer concentration equal to the substrate concentration (namely the P-n junction interface), and the impurity concentration distribution of the ion implantation is subjected to a Gaussian distribution function and is mainly related to implantation dosage;
Eighth step: carrying out local N-type (such as phosphorus, arsenic and the like) ion implantation on the back of the device by utilizing a photoetching plate, wherein the junction depth is 0.5-1 mu m, and carrying out activation and annealing by adopting a laser annealing process to form an N+ short-circuit region 22, wherein the laser annealing process can realize high activation and diffusion-free performance of a back structure;
Ninth step: a collector metal layer 1 is deposited on the back of the device and forms an ohmic contact with collector region 2 comprising p+ collector region 21 and n+ short-circuit region 22.
In the embodiment, the resistivity of the N-type silicon material serving as a substrate silicon wafer is 90 Ω & cm, the implantation dosage of hydrogen ion implantation is 1×10 17～1×1020cm-3, the implantation energy is 300-500 KeV, and the depth and thickness of the N-type field stop layer 3 are controlled by controlling the implantation energy, the laser annealing temperature and the annealing time; the implantation dosage of the P-type ion implantation with the ion implantation depth of 2-3 mu m is 1 multiplied by 10 12～1×1014cm-3, the implantation energy is 1-2 MeV, the implantation dosage of the P-type ion implantation with the junction depth of 1-2 mu m is 1 multiplied by 10 12～1×1014cm-3, and the implantation energy is 150-1000 KeV; the implantation dose of N-type ion implantation is 5×10 13～5×1015cm-3, and the implantation energy is 20-80 KeV.
The invention will be described in more detail below with reference to the accompanying drawings:
Fig. 5 is a schematic cross-sectional structure of a reverse conducting IGBT device 002 according to the present invention. A reverse-conduction insulated gate bipolar transistor with low hysteresis voltage and a preparation process thereof are provided, wherein the reverse-conduction insulated gate bipolar transistor comprises: a collector metal layer 1 at the bottom of the device; a collector region 2 is arranged on the collector metal layer 1, and the collector region 2 consists of P+ collector regions 21 and N+ short-circuit regions 22 which are alternately arranged; an N-type field stop layer 3 is arranged above the collector region 2; the N-type field stop layer is characterized in that an N-high resistance region 13 is further arranged between the N-type field stop layer 3 and the collector region 2; an N-type drift region 4 is arranged above the N-type field stop layer 3; the upper surface of the N-type drift region 4 is provided with grooves 5 which are arranged in a one-dimensional array, a gate oxide layer 6 and a polysilicon gate 7 are arranged in the grooves 5, and the gate oxide layer 6 is positioned between the polysilicon gate 7 and the inner wall of the grooves 5; a P-type body region 8 is arranged above the N-type drift region 4, and the P-type body region 8 is positioned between two adjacent grooves 5 and is in contact with the side walls of the grooves 5; an N+ emission region 9 and a P+ type contact region 10 are arranged on the P type body region 8, and the N+ emission region 9 is in contact with the side wall of the groove 5; the P+ type contact region 10 is positioned between the two N+ emission regions 9; an emitter metal layer 12 is connected to the p+ type contact region 10, and insulating dielectric layers 11 are provided on both sides of the emitter metal layer 12. The N-type field stop layer 2 is a buffer area formed by implanting H ions into the back, the doping concentration of the N-type field stop layer 2 is generally 1 multiplied by 10 15～1×1016cm-3, and the thickness is 2-3 mu m. The doping concentration of the N-high resistance region 13 is lower than that of the N-type field stop layer 3, the doping concentration of the N-high resistance region 13 is equal to that of the N-type drift region 4, and the thickness of the N-high resistance region 13 is 1-3 mu m. The N-type drift region 4 is an N-type monocrystalline silicon wafer substrate, and the resistivity is 90 omega cm. The junction depth of the n+ short circuit region 22 is 0.5 to 1 μm. The junction depth of the P+ collector region 21 is equal to the junction depth of the N+ short circuit region.
The N-type field stop layer 3 of device 002 is formed using an H ion back side implantation process to obtain a thicker N-high resistance region 13. The N-type field stop layer 3 and the collector region 2 of the device 002 are both activated and annealed by a laser annealing process to obtain a high activation, diffusion-free performance of the back structure.
As shown in fig. 6, when the device 002 is in the initial stage of forward conduction, the electron current injected into the drift region 4 from the device front side MOS channel also needs to flow through the N-high resistance region 13 after passing through the N-type field stop layer 3 to reach the n+ short circuit region 22. Compared with the traditional reverse conducting IGBT device 001, the device 002 obtains larger collector short-circuit resistance after being introduced into the N-high resistance region 13, effectively reduces hysteresis voltage and greatly improves the voltage folding problem of forward opening. On the other hand, part of the electron current longitudinally passes through the N-type field stop layer 3 and then transversely flows through the N-high resistance region 13 to finally reach the N+ short circuit region 22, and as the on-resistance of the N-high resistance region 13 is larger than that of the N-type field stop layer 3, the electron current in the N-high resistance region 13 generates larger transverse voltage drop and more easily exceeds the PN junction barrier between the N-high resistance region 13 and the P+ collector region 21, so that a PN junction formed between the N-high resistance region 13 and the P+ collector region 21 can be opened when the electron current is smaller, the device enters an IGBT mode earlier, and the snapback phenomenon in the forward conduction process of the traditional reverse conduction type IGBT is effectively inhibited.
In order to verify the advantages of the reverse-conduction IGBT device 002, the structure and the characteristics of the reverse-conduction IGBT device 002 and the traditional reverse-conduction IGBT device 001 are subjected to comparison simulation through the semiconductor device simulation software Sentaurus TCAD, as shown in fig. 14. Fig. 14 is a diagram showing forward and reverse conduction characteristics and a partial enlarged view of a conventional reverse-conduction IGBT device 001 and a reverse-conduction IGBT device 002 according to the present invention, which are subjected to comparative simulation by a semiconductor device simulation software Sentaurus TCAD. It can be found from the graph that the hysteresis voltage Δvsb of the conventional reverse conducting IGBT device 001 is large, and the conventional reverse conducting IGBT device has a serious snapback phenomenon in the forward conducting process. Compared with the traditional reverse conducting IGBT device 001, the hysteresis voltage delta Vsb of the reverse conducting IGBT device 002 is reduced by 69%, and the diode forward voltage drop is increased by 8.3% when the normal working current is 20A. It can be found that the reverse conducting type IGBT device 002 effectively inhibits the snapback phenomenon of the conventional reverse conducting type IGBT by using the N-high resistance region 13, and only increases the small forward voltage drop of the diode, and completely within the allowable range, thereby ensuring that the device has certain reverse conducting capability.
Fig. 7 is a schematic cross-sectional structure diagram of a reverse conducting IGBT device 003 according to the present invention. Compared with the reverse-conduction IGBT device 002, the reverse-conduction IGBT device 003 also has the following characteristics: the junction depth of the P+ collector region 21 is 2-3 μm, and a certain interval is provided between the P+ collector region and the N-type field stop layer 3. The junction depth of the n+ short circuit region 22 is smaller than that of the p+ collector region 21, the N-high resistance region 13 is T-shaped, a self-adjusting depletion region is formed in a narrow N-high resistance region between two adjacent p+ collector regions 21, and an electron current path with required resistance can be obtained under forward and reverse bias, so that the forward and reverse conduction performance of the device can be optimized simultaneously.
When the device 003 is in the forward conduction initial stage, as shown in fig. 8, most of the electron current injected into the N-type drift region 4 from the MOS channel on the front side of the device passes through the N-type field stop layer 3 transversely, then flows longitudinally through the T-shaped N-high resistance region 13 and its self-regulating depletion region, and finally reaches the n+ short-circuit region 22. At this time, due to the built-in potential between the p+ collector region 21 and the N-high resistance region 13, electrons in the self-regulating depletion region are rapidly depleted, thereby reducing the doping concentration of the self-regulating depletion region, further increasing the on-resistance (Rep) of the self-regulating depletion region, providing a high-resistance electron current path, and achieving a larger collector short-circuit resistance, which helps to reduce the hysteresis voltage, improving the forward-turn-on voltage turn-back problem.
During reverse conduction, the collector electrode applies negative bias voltage, due to hole aggregation at the interface of the N-high resistance region 13 and the P+ collector regions 21, the self-regulating depletion regions between two adjacent P+ collector regions 21 become non-depleted, which is equivalent to improving the electron doping concentration of the self-regulating depletion regions, thereby reducing the on-resistance (Rep) of the self-regulating depletion regions, providing a low-resistance electron current path, which is beneficial to reducing the forward conduction voltage drop of the diode, reducing the conduction loss of the diode and improving the reverse conduction performance of the device.
Compared with the reverse conduction type IGBT device 002, in the forward conduction and reverse conduction processes, the reverse conduction type IGBT device 003 obtains favorable on-resistance (Rep) through the self-regulating depletion region in the N-high resistance region 13, so that the collector short-circuit resistance in the forward conduction process can be further increased by reducing the distance between two adjacent P+ collector regions 21 by sacrificing part of reverse conduction performance of the device, the effect that the reverse conduction type IGBT device 003 is reduced in forward voltage of a diode similar to the device 002, the hysteresis voltage is further reduced, and the voltage folding problem of the reverse conduction type IGBT is effectively improved.
To verify the advantages of the present device 003, the present invention compares the structure and characteristics of the present device 003 with those of the device 002 by means of the semiconductor device simulation software Sentaurus TCAD, as shown in fig. 14. Fig. 14 is a diagram showing the forward and reverse turn-on characteristics and a partial enlarged view of the reverse conducting IGBT device 002 and the reverse conducting IGBT device 003 of the present invention, which are subjected to comparative simulation by the semiconductor device simulation software Sentaurus TCAD. It can be seen from the graph that, compared with the device 002, the hysteresis voltage Δvsb of the device 003 is reduced by 27.4%, and the forward voltage drop of the diode at the normal operating current of 20A is increased by 5.1%. It can be found that the device 003 effectively suppresses snapback phenomenon by using the self-regulating depletion region, only increases the forward voltage drop of the small diode, and completely falls within the allowable range, thereby ensuring that the device has certain reverse conduction capability.
Fig. 10 is a schematic diagram showing a cross-sectional structure of the reverse conducting IGBT device 004. Compared with the reverse-conducting IGBT device 002 of the invention, the reverse-conducting IGBT device has the following characteristics: the p+ collector regions 21 are L-shaped, the N-high resistance regions 13 are inverted i-shaped, and the minimum distance between two adjacent L-shaped p+ collector regions 21 is smaller than the width of the n+ short circuit region 22. The collector region 2 is composed of alternately arranged L-shaped P+ collector regions 21 and N+ short circuit regions 22. The junction depth of the P+ collector region 21 is 2-3 μm, and the junction depth of the N+ short-circuit region 22 is 0.5-1 μm.
As shown in fig. 11, in the initial forward conduction stage, most of the electron current injected into the N-type drift region 4 from the device front MOS channel passes through the N-type field stop layer 3 transversely, then flows longitudinally through the N-high resistance region 13 in the shape of an inverted "i" and its self-regulating depletion region, and finally reaches the n+ short-circuit region 22. Compared with the device 003, in the forward conduction process of the device 004, the N-high resistance region 13 in the inverted I shape increases the overall thickness compared with the N-high resistance region 13 in the T shape, and provides higher on resistance, so that the collector short circuit resistance is further increased, the hysteresis voltage is reduced, and the snapback phenomenon is restrained.
As shown in fig. 12, when the reverse conduction is performed, the p+ type contact region 10 is used as the anode of the freewheeling diode, the n+ short-circuit region 22 is used as the cathode of the freewheeling diode, the electrons in the n+ short-circuit region 22 and the holes in the P type body region 8 are both injected into the N-type drift region 4, and a conductivity modulation effect, that is, a large injection effect of carriers, occurs in the N-type drift region 4, and since a large amount of carriers are accumulated in the N-type drift region 4, the on-resistance is greatly reduced, and the device has a low-resistance characteristic at this time, so that the reverse conduction type IGBT device is ensured to have a better reverse conduction capability. When the device 003 is turned on reversely, the n+ short circuit region 22 has a small electron injection area and thus has a limited number of electrons injected into the N-type drift region 4, so that the generated conductance modulation effect is limited. Compared with the device 003, the device 004 of the invention increases the effective area of the N+ short-circuit region 22 in the reverse conduction process, and the conductance modulation effect is enhanced, thereby reducing the forward conduction voltage drop of the diode, improving the reverse conduction performance of the device, further effectively improving the voltage folding problem of the reverse conduction IGBT by sacrificing part of reverse conduction performance of the device and reducing the distance between two adjacent L-shaped P+ collector regions 21 to further increase the collector short-circuit resistance in forward conduction, and realizing the reduction of the forward voltage of the diode similar to the device 003 by the device 004.
In order to verify the advantages of the device 004, the structure and the characteristics of the reverse-conduction IGBT device 004 and the reverse-conduction IGBT device 003 are subjected to comparison simulation through the semiconductor device simulation software Sentaurus TCAD, as shown in fig. 15. Fig. 15 is a diagram showing the forward and reverse conduction characteristics and a partial enlarged view of the reverse conduction type IGBT device 003 and the reverse conduction type IGBT device 004 which are subjected to comparative simulation by the semiconductor device simulation software Sentaurus TCAD. As can be seen from the figure, compared with the reverse-conduction IGBT device 003, the hysteresis voltage Δvsb of the reverse-conduction IGBT device 004 is further reduced by 81.9%, and the diode forward voltage drop at the normal operating current of 20A is increased by 0.9%. It can be found that the reverse-conduction type IGBT device 004 adopts an L-shaped P+ collector region and an inverted H-shaped N-high resistance region, so that the snapback phenomenon in the forward conduction process of the reverse-conduction type IGBT is greatly improved, the forward voltage drop of a diode of the device is hardly increased, and certain reverse conduction capacity of the device is fully ensured.
The following describes in detail the main process steps of the reverse conducting IGBT device 004 according to the present invention with reference to fig. 13-1 to 13-10, a process for preparing a reverse conducting insulated gate bipolar transistor with low hysteresis voltage, comprising:
The first step: an N-type silicon material with the resistivity of 90 omega cm is selected as a substrate silicon wafer, namely an N-type drift region 4, as shown in fig. 13-1;
and a second step of: etching a groove 5 on the upper surface of the N-type drift region 4, as shown in fig. 13-2;
and a third step of: growth inside the etched trench 5 on the upper surface of the N-type drift region 4 Then depositing heavily doped polysilicon to form a polysilicon gate 7, as shown in fig. 13-3;
Fourth step: forming a P type body region 8, an N+ emission region 9 and a P+ type contact region 10 on the upper surface of the N-type drift region 4 by utilizing an ion implantation or diffusion method and annealing in sequence, as shown in fig. 13-4;
Fifth step: depositing an insulating dielectric layer 11 on the upper surface of the device, wherein the material of the insulating dielectric layer 11 can be borophosphosilicate glass, etching a contact hole on the insulating dielectric layer, and depositing to form an emitter metal layer 12, as shown in fig. 13-5;
Sixth step: turning over the device, carrying out hydrogen ion implantation on the back surface, and then carrying out ion activation and annealing by adopting a laser annealing process to form an N-type field stop layer 3, wherein the depth and thickness of the N-type field stop layer 3 can be controlled by controlling implantation energy, laser annealing temperature and annealing time as shown in fig. 13-6;
seventh step: performing first P-type (such as boron, aluminum, gallium, etc.) ion implantation on the back of the device by using a photomask to form an upper part of an L-shaped P+ collector region 21, as shown in FIGS. 13-7;
eighth step: performing second P-type (such as boron, aluminum, gallium and the like) ion implantation on the back of the device by utilizing a photoetching plate, then performing ion activation and annealing by adopting a laser annealing process, and forming a complete L-shaped P+ collector region 21 by contacting with the upper part of the L-shaped P+ collector region 21 after annealing to reach the required junction depth, as shown in fig. 13-8;
Ninth step: performing local N-type (such as phosphorus, arsenic and the like) ion implantation on the back of the device by using a photoetching plate, and then performing ion activation and annealing by using a laser annealing process to form an N+ short circuit region 22 by annealing to a required junction depth, as shown in fig. 13-9;
tenth step: a collector metal layer 1 is deposited on the back of the device to form an ohmic contact with the collector region 2 as shown in fig. 13-10.

Claims (11)

1. A low hysteresis voltage reverse conducting insulated gate bipolar transistor comprising: the collector metal layer (1) is positioned at the bottom of the device, the collector metal layer (1) is provided with a collector region (2), the collector region (2) comprises P+ collector regions (21) and N+ short-circuit regions (22) which are alternately arranged, an N-type field stop layer (3) is arranged above the collector region (2), an N-type drift region (4) is arranged above the N-type field stop layer (3), grooves (5) which are arranged in a one-dimensional array are arranged on the upper surface of the N-type drift region (4), a gate oxide layer (6) and a polysilicon gate (7) are arranged in the grooves (5), the gate oxide layer (6) is positioned between the polysilicon gate (7) and the inner wall of the grooves (5), a P-type body region (8) is arranged above the N-type drift region (4), and the P-type body region (8) is positioned between two adjacent grooves (5) and is in contact with the side walls of the grooves (5); an N+ emission region (9) and a P+ type contact region (10) are arranged on the P type body region (8), an emitter metal layer (12) is connected to the P+ type contact region (10), and insulating medium layers (11) are arranged on two sides of the emitter metal layer (12), and the N-type field stop layer is characterized in that an N-high resistance region (13) is arranged between the N type field stop layer (3) and the collector region (2);
A cavity (211) is formed in the P+ collector region (21), the cavity (211) is propped against the side surface of the N+ short-circuit region (22), and the height of the cavity (211) is larger than that of the N+ short-circuit region (22); the N+ short-circuit region (22) transversely extends, passes through the cavity (211) and is stopped at the P+ collector region (21), and the N-high-resistance region (13) is re-extended and fills the cavity (211), so that a re-extension part (132) of the N-high-resistance region (13) is covered on the transversely extended N+ short-circuit region (22);
The doping concentration of the N-high-resistance region (13) is lower than that of the N-type field stop layer (3), the doping concentration of the N-high-resistance region (13) is equal to that of the N-type drift region (4), and the thickness of the N-high-resistance region (13) is 1-3 mu m.
2. The low hysteresis voltage reverse conducting insulated gate bipolar transistor according to claim 1, wherein the p+ collector region (21) has a depth greater than the depth of the n+ short-circuit region (22) and forms a recess above the n+ short-circuit region (22), the N-high resistance region (13) extends, fills the recess and the extension of the N-high resistance region (13) is a self-regulating depletion region (131).
3. The low hysteresis voltage reverse conducting insulated gate bipolar transistor according to claim 1, wherein the N-type field stop layer (2) is a buffer region formed by back implantation of H ions, and the doping concentration of the N-type field stop layer (2) is generally 1×10 15~1×1016cm-3, and the thickness is 2-3 μm.
4. The low hysteresis voltage reverse conducting insulated gate bipolar transistor according to claim 1, wherein said N-type drift region (4) is an N-type monocrystalline silicon wafer substrate having a resistivity of 90 Ω -cm.
5. The low hysteresis voltage reverse conducting type insulated gate bipolar transistor according to claim 1, wherein the junction depth of the n+ short-circuit region (22) is 0.5-1 μm.
6. A preparation process of a reverse conducting insulated gate bipolar transistor with low hysteresis voltage is characterized in that,
The first step: selecting an N-type silicon material as a substrate silicon wafer, and forming an N-type drift region (4) by using the N-type silicon material;
And a second step of: etching a groove (5) on the upper surface of the N-type drift region (4);
And a third step of: growing a gate oxide layer (6) on the inner side of a groove (5) etched on the upper surface of the N-type drift region (4), and then depositing heavily doped polysilicon to form a polysilicon gate (7);
Fourth step: an ion implantation or diffusion method is used for annealing on the upper surface of the N-type drift region (4), and a P-type body region (8), an N+ emission region (9) and a P+ type contact region (10) are formed in sequence;
Fifth step: depositing an insulating dielectric layer (11) on the upper surface of the device, wherein the insulating dielectric layer material can be borophosphosilicate glass, etching a contact hole on the insulating dielectric layer material, and depositing to form an emitter metal layer (12);
Sixth step: turning over the device, carrying out hydrogen ion implantation on the back surface and carrying out laser annealing to form an N-type field stop layer (3) with the distance between the lower surface and the bottom of the device of 4-6 mu m and the thickness of 2-3 mu m;
Seventh step: carrying out local P-type ion implantation with the ion implantation depth of 2-3 mu m on the back of the device by using a photoetching plate, carrying out local P-type ion implantation with the junction depth of 1-2 mu m on the back of the device by using the photoetching plate, and carrying out activation and annealing by using a laser annealing process to form an L-shaped P+ collector region (21);
Eighth step: carrying out local N-type ion implantation on the back of the device by utilizing a photoetching plate, wherein the junction depth is 0.5-1 mu m, and carrying out activation and annealing by adopting a laser annealing process to form an N+ short-circuit region (22);
ninth step: a collector metal layer (1) is deposited on the back of the device and forms ohmic contact with a collector region (2) comprising a P+ collector region (21) and an N+ shorting region (22).
7. The process of claim 6, wherein the P-type ion implantation with a junction depth of 1-2 μm has an implantation dose of 1 x 10 12~1×1014cm-3 and an implantation energy of 150-1000 kev.
8. The process according to claim 6, wherein the resistivity of the N-type silicon material as the substrate silicon wafer is 90Ω·cm.
9. The process of claim 6, wherein the hydrogen ion is implanted at a dose of 1 x 10 17~1×1020cm-3 and an implantation energy of 300 to 500kev.
10. The process of claim 6, wherein the P-type ion implantation having an ion implantation depth of 2-3 μm has an implantation dose of 1 x 10 12~1×1014cm-3 and an implantation energy of 1-2 mev.
11. The process of claim 6, wherein the N-type ion implantation is performed at an implantation dose of 5 x 10 13~5×1015cm-3 and an implantation energy of 20-80 kev.
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