CN115357080B - High-performance LDO circuit based on switch dynamic switching - Google Patents
High-performance LDO circuit based on switch dynamic switching Download PDFInfo
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- CN115357080B CN115357080B CN202211079987.1A CN202211079987A CN115357080B CN 115357080 B CN115357080 B CN 115357080B CN 202211079987 A CN202211079987 A CN 202211079987A CN 115357080 B CN115357080 B CN 115357080B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a high-performance LDO circuit based on dynamic switching of a switch, which comprises a voltage comparison unit, an inverter, a switch group and a load tube, wherein an VREF terminal is externally connected to an inverting input end of the voltage comparison unit, a voltage output end is externally connected to a non-inverting input end of the voltage comparison unit, the voltage output end is grounded through a first capacitor, the output end of the voltage comparison unit is electrically connected with the inverter, the output end of the inverter is connected with the switch group, the switch group is electrically connected with the load tube, and the output end of the inverter outputs a control signal to control the switch group to switch so as to enable the load tube to be turned on or off, so that the voltage output end outputs voltage feedback to the switching control signal of the voltage comparison module. According to the invention, through the structural design of the switching type LDO circuit, the voltage comparison switch is switched, the circuit structure is simple, the influence of loop stability is avoided, and the overall power consumption of the LDO circuit is greatly reduced.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a high-performance LDO circuit based on dynamic switching of a switch.
Background
The LDO is mainly composed of PMOS, an operational amplifier, a feedback resistor and a base reference voltage. The LDO mainly works by dividing the output voltage through a dividing resistor, amplifying the voltage of the dividing resistor and a difference signal of a reference voltage, and regulating the output voltage through operational amplifier output.
Disclosure of Invention
In view of the above, the present invention is to provide a high performance LDO circuit based on dynamic switching of a switch.
In order to solve the technical problems, the invention adopts the following technical scheme: the utility model provides a high performance LDO circuit based on switch dynamic switch, includes voltage comparison unit, dc-to-ac converter, switch group and load tube, the external VREF terminal that has of inverting input end of voltage comparison unit, the external voltage output end that has of noninverting input end of voltage comparison unit, voltage output end passes through first electric capacity ground connection, the output of voltage comparison unit with the dc-to-ac converter electric connection, the output of dc-to-ac converter with switch group links to each other, switch group with load tube electric connection, the output control signal control switch group of dc-to-ac converter switches so that the load tube switches on or off to realize voltage output end output voltage feedback back voltage comparison module switching control signal.
In the present invention, preferably, the output terminal of the inverter includes a low level control signal terminal and a high level control signal terminal, the switch group includes a first switch, a second switch, a third switch, a fourth switch, and a fifth switch, the second switch and the third switch are connected to the high level control signal terminal, and the first switch, the fourth switch, and the fifth switch are connected to the low level control signal terminal.
In the present invention, preferably, the drain electrode of the load tube is connected to the positive input end of the voltage comparing unit through a second capacitor, the drain electrode of the load tube is grounded through a first resistor, a second resistor and a third resistor which are connected in series, the gate electrode of the load tube is externally connected with the gate electrode of the field effect tube, the drain electrode of the field effect tube is grounded through a second switch, the source electrode of the field effect tube is connected to the source electrode of the load tube, the third switch is connected between the second capacitor and the first resistor in parallel, the first switch is connected between the source electrode of the load tube and the gate electrode of the load tube in parallel, the fourth switch is connected between the second capacitor and the second resistor in parallel, and the drain electrode of the load tube is grounded through a fifth switch.
In the present invention, preferably, the voltage comparing unit includes a first MOS transistor to a second eleventh MOS transistor, where a source of the first MOS transistor is connected to a source of the second MOS transistor and is connected to a drain of the third MOS transistor, a gate of the first MOS transistor and a gate of the second MOS transistor are respectively connected to a drain of the fifth MOS transistor and a drain of the sixth MOS transistor, a gate of the third MOS transistor, a gate of the fourth MOS transistor and a gate of the seventh MOS transistor are connected to a drain of the tenth MOS transistor, a gate of the tenth MOS transistor is externally connected to an ENN enable terminal, a drain of the first MOS transistor and a drain of the second MOS transistor are respectively connected to a drain of the twelfth MOS transistor and a drain of the thirteenth MOS transistor, a gate of the thirteenth MOS transistor is connected to a drain of the thirteenth MOS transistor, and the eleventh MOS transistor and the fourteenth MOS transistor are symmetrically connected to both sides of the twelfth MOS transistor and the thirteenth MOS transistor.
In the invention, preferably, the drain electrode of the twelfth MOS tube is connected with the drain electrode of the fifteenth MOS tube and the grid electrode of the seventeenth MOS tube, the drain electrode of the thirteenth MOS tube is connected with the drain electrode of the sixteenth MOS tube and the grid electrode of the eighteenth MOS tube, the grid electrodes of the fifteenth MOS tube and the sixteenth MOS tube are externally connected with ENP enabling terminals, the drain electrode of the seventeenth MOS tube is connected with the drain electrode of the nineteenth MOS tube, the drain electrode of the eighteenth MOS tube is connected with the drain electrode of the twentieth MOS tube and is used as the output end of the voltage comparison unit, the grid electrode of the nineteenth MOS tube is connected with the grid electrode of the twentieth MOS tube and the drain electrode of the twenty first MOS tube, and the grid electrode of the twenty first MOS tube is externally connected with ENN enabling terminals.
In the present invention, preferably, the source of the tenth MOS transistor, the source of the seventh MOS transistor, the source of the fourth MOS transistor, the source of the third MOS transistor, the source of the nineteenth MOS transistor, the source of the twentieth MOS transistor, and the source of the twenty first MOS transistor are externally connected with VSS terminals.
In the invention, preferably, the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are respectively connected with the drain electrode of the ninth MOS tube and the drain electrode of the eighth MOS tube, the grid electrode of the eighth MOS tube is externally connected with the VP terminal, the grid electrode of the ninth MOS tube is externally connected with the VN terminal, the source electrode of the eighth MOS tube and the source electrode of the ninth MOS tube are respectively connected with the drain electrode of the seventh MOS tube, and the drain electrode of the eighth MOS tube, the drain electrode of the ninth MOS tube, the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are respectively connected with the source electrode of the eleventh MOS tube through the fourth resistor, the fifth resistor, the sixth resistor and the seventh resistor.
In the invention, preferably, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor and the twenty-first MOS transistor are all N-type MOS transistors.
In the present invention, preferably, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, the seventeenth MOS transistor, and the eighteenth MOS transistor are all P-type MOS transistors.
The invention has the advantages and positive effects that: the invention can promote the output attack resistance, and improves the response speed of the whole LDO by improving the traditional operational amplifier structure of the LDO into a circuit structure which is mutually matched between the voltage comparison unit and the switch group, thereby improving the transient response of the output load and simultaneously improving the output attack resistance; in addition, the traditional PMOS operational amplifier LDO stabilizes output voltage through loop feedback and needs to consider the stability of a loop, but the invention has the advantages of simple circuit structure and no influence of loop stability through the structural design of a switch type LDO and the switching of a voltage comparison switch; the voltage comparison unit and the switch group are matched with each other in a simple structure, and compared with the traditional LDO circuit structure, the integral power consumption of the LDO circuit is greatly reduced.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
FIG. 1 is an overall block diagram of a high performance LDO circuit based on switch dynamic switching of the present invention;
FIG. 2 is a schematic circuit diagram of a voltage comparison unit of a high performance LDO circuit based on switching dynamic switching of the present invention;
FIG. 3 is an enlarged schematic view of a portion of the structure A of FIG. 2;
FIG. 4 is an enlarged schematic view of a portion of the B structure of FIG. 2;
in the figure: PASS, load tube; CMP1, voltage comparison unit; VOUT, voltage output; c1, a first capacitor; c2, a second capacitor; s1, a low-level control signal terminal; S1N, a high level control signal terminal; SW1, a first switch; SW2, a second switch; SW3, a third switch; SW4, fourth switch; SW5, a fifth switch; r1, a first resistor; r2, a second resistor; r3, a third resistor; m0, field effect transistor; m1, a first MOS tube; m2, a second MOS tube; m3, a third MOS tube; m4, a fourth MOS tube; m5, a fifth MOS tube; m6, a sixth MOS tube; m7, a seventh MOS tube; m8, an eighth MOS tube;
m9, a ninth MOS tube; m10, a tenth MOS tube; m11, eleventh MOS tube; m12, a twelfth MOS tube; m13, thirteenth MOS tube; m14, a fourteenth MOS tube; m15, a fifteenth MOS tube; m16, sixteenth MOS tube; m17, seventeenth MOS tube; m18, eighteenth MOS tube; m19, nineteenth MOS tube; m20, a twentieth MOS tube; m21, twenty-first MOS pipe.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When a component is considered to be "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the invention provides a high-performance LDO circuit based on dynamic switching of a switch, which comprises a voltage comparison unit CMP1, an inverter, a switch group and a load tube PASS, wherein the inverting input end of the voltage comparison unit CMP1 is externally connected with a VREF terminal, the non-inverting input end of the voltage comparison unit CMP1 is externally connected with a voltage output end VOUT, the voltage output end VOUT is grounded through a first capacitor C1, the output end of the voltage comparison unit CMP1 is electrically connected with the inverter, the output end of the inverter is connected with the switch group, the switch group is electrically connected with the load tube PASS, and the output end of the inverter outputs a control signal to control the switch group to switch so as to enable the load tube PASS to be turned on or off, thereby realizing feedback of the output voltage of the voltage output end VOUT to the switch control signal of the voltage comparison module. The inverter output end outputs control signals S1 and S1N, S1 is a low-level control signal terminal, S1N is a high-level control signal terminal, the switch group comprises a first switch to a fifth switch SW 1-SW 5, when S1N is at a high level, S1 is at a low level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are turned off, the second switch SW2 and the third switch SW3 are turned on, the load tube PASS charges the first capacitor C1, when the voltage of the VFB terminal is higher than the voltage of the VREF terminal, S1N is at a low level, S1 is at a high level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are turned on, the second switch SW2 and the third switch SW3 are turned off, so that the voltage of the load tube PASS tube is turned off, the voltage of the first capacitor C1 discharges through the fifth switch SW5, the voltage output end becomes low, the VFB voltage becomes low, when the voltage of the VFB terminal is lower than the voltage of the VREF terminal, the voltage of the VFB terminal becomes low, the S1N becomes low level, the voltage is not matched with the high level switch unit, and the switching unit becomes stable in dynamic balance, and the output voltage is achieved.
In this embodiment, further, the output end of the inverter includes a low level control signal terminal S1 and a high level control signal terminal S1N, the switch group includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4 and a fifth switch SW5, the second switch SW2 and the third switch SW3 are connected to the high level control signal terminal S1N, and the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are connected to the low level control signal terminal S1.
In this embodiment, further, the drain of the load tube PASS is connected to the non-inverting input terminal of the voltage comparison unit CMP1 through the second capacitor C2, and the drain of the load tube PASS is grounded through a first resistor R1, a second resistor R2, and a third resistor R3 that are connected in series with each other, the gate of the load tube PASS is externally connected with the gate of the field effect tube M0, the drain of the field effect tube M0 is grounded through the second switch SW2, the source of the field effect tube M0 is connected to the source of the load tube PASS, the third switch SW3 is connected in parallel between the second capacitor C2 and the first resistor R1, the first switch SW1 is connected in parallel between the source of the load tube PASS and the gate of the load tube PASS, the fourth switch SW4 is connected in parallel between the second capacitor C2 and the second resistor R2, and the drain of the load tube PASS is grounded through the fifth switch SW 5.
As shown in fig. 2, 3 and 4, in this embodiment, the voltage comparing unit CMP1 further includes a first MOS transistor M1 to a twenty-first MOS transistor M21, where the source of the first MOS transistor M1 is connected to the source of the second MOS transistor M2 and to the drain of the third MOS transistor M3, the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are respectively connected to the drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6, the gate of the third MOS transistor M3, the gate of the fourth MOS transistor M4 and the gate of the seventh MOS transistor M7 are all connected to the drain of the tenth MOS transistor M10, the gate of the tenth MOS transistor M10 is externally connected to the ENN enabling terminal, the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2 are respectively connected to the drain of the thirteenth MOS transistor M12 and the drain of the thirteenth MOS transistor M13, the gate of the twelfth MOS transistor M12 is connected to the drain of the thirteenth MOS transistor M13, and the gate of the thirteenth MOS transistor M13 is connected to the drain of the thirteenth MOS transistor M13, and the thirteenth MOS transistor M12 is connected to the thirteenth transistor M12 and the thirteenth transistor M14.
In this embodiment, further, the drain of the twelfth MOS transistor M12 is connected to the drain of the fifteenth MOS transistor M15 and the gate of the seventeenth MOS transistor M17, the drain of the thirteenth MOS transistor M13 is connected to the drain of the sixteenth MOS transistor M16 and the gate of the eighteenth MOS transistor M18, the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are both externally connected with an ENP enable terminal, the drain of the seventeenth MOS transistor M17 is connected to the drain of the nineteenth MOS transistor M19, the drain of the eighteenth MOS transistor M18 is connected to the drain of the twentieth MOS transistor M20 and serves as the output end of the voltage comparison unit CMP1, the gate of the nineteenth MOS transistor M19 is connected to the gate of the twentieth MOS transistor M20 and the drain of the twenty first MOS transistor M21, and the gate of the twenty first MOS transistor M21 is externally connected with an ENN enable terminal.
In this embodiment, further, the source of the tenth MOS transistor M10, the source of the seventh MOS transistor M7, the source of the fourth MOS transistor M4, the source of the third MOS transistor M3, the source of the nineteenth MOS transistor M19, the source of the twentieth MOS transistor M20, and the source of the twenty-first MOS transistor M21 are externally connected with VSS terminals.
In this embodiment, further, the gates of the fifth MOS transistor M5 and the sixth MOS transistor M6 are respectively connected to the drain of the ninth MOS transistor M9 and the drain of the eighth MOS transistor M8, the gate of the eighth MOS transistor M8 is externally connected to a VP terminal, the gate of the ninth MOS transistor M9 is externally connected to a VN terminal, the source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are both connected to the drain of the seventh MOS transistor M7, and the drain of the eighth MOS transistor M8, the drain of the ninth MOS transistor M9, the drain of the fifth MOS transistor M5, and the drain of the sixth MOS transistor M6 are respectively connected to the source of the eleventh MOS transistor through a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor.
In this embodiment, further, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, and the twenty-first MOS transistor M21 are all N-type MOS transistors.
In this embodiment, further, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, and the eighteenth MOS transistor M18 are all P-type MOS transistors.
The working principle and working process of the invention are as follows: the reverse phase input end of the voltage comparison unit CMP1 is externally connected with a VREF terminal, the positive phase input end of the voltage comparison unit CMP1 is externally connected with a VFB terminal, the output end of the inverter outputs control signals S1 and S1N, S1 is a low-level control signal terminal, S1N is a high-level control signal terminal, the switch group comprises first to fifth switches SW1 to SW5, when S1N is high level, S1 is low level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are disconnected, the second switch SW2 and the third switch SW3 are connected, the load tube PASS charges the first capacitor C1, when the voltage of the VFB terminal is higher than the VREF terminal, S1N is low level, S1 is high level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are connected, the second switch SW2 and the third switch SW3 are disconnected, the voltage of the first capacitor C1 discharges through the fifth switch SW5, the voltage output end becomes low, the VFB voltage is enabled to become low, when the voltage of the VFB terminal is lower than the VREF terminal, the voltage is lower than the voltage of the S1, and the voltage of the switch group becomes stable, and the voltage of the voltage comparison unit is enabled to be stable when the voltage of the voltage is not lower than the VREF terminal is reached, and the voltage is stable, and the voltage is changed to reach the balance.
When the output load jump of the voltage output end VOUT becomes low, the voltage of the terminal VFB is rapidly lowered through the second capacitor C2, and is directly fed back to the voltage comparison module CMP1, the terminal S1 becomes low level, the terminal S1N becomes high level, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are turned off, the second switch SW2 and the third switch SW3 are turned on, and the load tube PASS is turned on to pull the level of the voltage output end VOUT high; when the output load jump of the voltage output end VOUT becomes high, the terminal VFB is rapidly changed to be high through the second capacitor C2, the voltage is directly fed back to the voltage comparison module CMP1, the terminal S1 is changed to be high, the terminal S1N is changed to be low, the first switch SW1, the fourth switch SW4 and the fifth switch SW5 are turned on, the second switch SW2 and the third switch SW3 are turned off, the PASS tube of the load tube is turned off, the VOUT of the voltage output end is discharged through the fifth switch SW5, and the level of the voltage output end VOUT is pulled down. The second capacitor C2 can be used for improving loop feedback, so that acceleration is achieved when the circuit works and runs.
The invention can promote the output attack resistance, and the traditional operational amplifier structure of the LDO is changed into a comparison switch structure, so that the response speed of the whole LDO is improved, the transient response of the output load is improved, and the output attack resistance is improved at the same time; in addition, the traditional PMOS operational amplifier LDO stabilizes output voltage through loop feedback and needs to consider the stability of a loop, but the invention has the advantages of simple circuit structure and no influence of loop stability through the structural design of a switch type LDO and the switching of a voltage comparison switch; the voltage comparison unit and the switch group are matched with each other in a simple structure, and compared with the traditional LDO circuit structure, the integral power consumption of the LDO circuit is greatly reduced.
The foregoing describes the embodiments of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by this patent.
Claims (6)
1. The high-performance LDO circuit based on the dynamic switching of the switch is characterized by comprising a voltage comparison unit, an inverter, a switch group and a load tube, wherein the inverting input end of the voltage comparison unit is externally connected with a VREF terminal, the non-inverting input end of the voltage comparison unit is externally connected with a voltage output end, the voltage output end is grounded through a first capacitor, the output end of the voltage comparison unit is electrically connected with the inverter, the output end of the inverter is connected with the switch group, the switch group is electrically connected with the load tube, and the output end of the inverter outputs a control signal to control the switch group to switch so as to enable the load tube to be switched on or off, so that the voltage output end outputs a voltage feedback switching control signal to the voltage comparison module;
the voltage comparison unit comprises a first MOS tube and a second MOS tube, wherein the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is connected with the drain electrode of the third MOS tube, the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are respectively connected with the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube, the grid electrode of the third MOS tube, the grid electrode of the fourth MOS tube and the grid electrode of the seventh MOS tube are respectively connected with the drain electrode of the tenth MOS tube, the grid electrode of the tenth MOS tube is externally connected with an ENN enabling terminal, the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are respectively connected with the drain electrode of the twelfth MOS tube and the drain electrode of the thirteenth MOS tube, the grid electrode of the thirteenth MOS tube is connected with the drain electrode of the twelfth MOS tube, and the eleventh MOS tube are symmetrically connected with two sides of the twelfth MOS tube and the thirteenth MOS tube;
the drain electrode of the twelfth MOS tube is connected with the drain electrode of the fifteenth MOS tube and the grid electrode of the seventeenth MOS tube, the drain electrode of the thirteenth MOS tube is connected with the drain electrode of the sixteenth MOS tube and the grid electrode of the eighteenth MOS tube, the grid electrodes of the fifteenth MOS tube and the sixteenth MOS tube are externally connected with ENP enabling terminals, the drain electrode of the seventeenth MOS tube is connected with the drain electrode of the nineteenth MOS tube, the drain electrode of the eighteenth MOS tube is connected with the drain electrode of the twentieth MOS tube and serves as the output end of the voltage comparison unit, the grid electrode of the nineteenth MOS tube is connected with the grid electrode of the twentieth MOS tube and the drain electrode of the twenty first MOS tube, and the grid electrode of the twenty first MOS tube is externally connected with ENN enabling terminals;
the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are respectively connected with the drain electrode of the ninth MOS tube and the drain electrode of the eighth MOS tube, the grid electrode of the eighth MOS tube is externally connected with a VP terminal, the grid electrode of the ninth MOS tube is externally connected with a VN terminal, the source electrode of the eighth MOS tube and the source electrode of the ninth MOS tube are respectively connected with the drain electrode of the seventh MOS tube, and the drain electrode of the eighth MOS tube, the drain electrode of the ninth MOS tube, the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are respectively connected with the source electrode of the eleventh MOS tube through a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor.
2. The high-performance LDO circuit according to claim 1, wherein the output terminal of the inverter comprises a low-level control signal terminal and a high-level control signal terminal, the switch group comprises a first switch, a second switch, a third switch, a fourth switch and a fifth switch, the second switch and the third switch are connected to the high-level control signal terminal, and the first switch, the fourth switch and the fifth switch are connected to the low-level control signal terminal.
3. The high-performance LDO circuit based on the dynamic switching of the switch according to claim 2, wherein the drain electrode of the load tube is connected with the positive input end of the voltage comparison unit through a second capacitor, the drain electrode of the load tube is grounded through a first resistor, a second resistor and a third resistor which are connected in series, the grid electrode of the load tube is externally connected with the grid electrode of a field effect tube, the drain electrode of the field effect tube is grounded through a second switch, the source electrode of the field effect tube is connected with the source electrode of the load tube, the third switch is connected between the second capacitor and the first resistor in parallel, the first switch is connected between the source electrode of the load tube and the grid electrode of the load tube in parallel, the fourth switch is connected between the second capacitor and the second resistor in parallel, and the drain electrode of the load tube is grounded through a fifth switch.
4. The high-performance LDO circuit based on the dynamic switching of the switch according to claim 1, wherein the source electrode of the tenth MOS transistor, the source electrode of the seventh MOS transistor, the source electrode of the fourth MOS transistor, the source electrode of the third MOS transistor, the source electrode of the nineteenth MOS transistor, the source electrode of the twentieth MOS transistor and the source electrode of the twenty first MOS transistor are externally connected with VSS terminals.
5. The high-performance LDO circuit based on the dynamic switching of the switch according to claim 1, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor and the twenty-first MOS transistor are all N-type MOS transistors.
6. The high-performance LDO circuit based on the dynamic switching of the switch according to claim 1, wherein the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, the seventeenth MOS transistor and the eighteenth MOS transistor are all P-type MOS transistors.
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| CN202211079987.1A CN115357080B (en) | 2022-09-05 | 2022-09-05 | High-performance LDO circuit based on switch dynamic switching |
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| CN202211079987.1A CN115357080B (en) | 2022-09-05 | 2022-09-05 | High-performance LDO circuit based on switch dynamic switching |
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| CN115357080B true CN115357080B (en) | 2024-01-30 |
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| CN114257216A (en) * | 2020-09-22 | 2022-03-29 | 深圳英集芯科技股份有限公司 | Two-phase three-order ring oscillator circuit, related chip and electronic device |
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2022
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| CN103529895A (en) * | 2013-10-31 | 2014-01-22 | 无锡中星微电子有限公司 | High-stability voltage regulator |
| US9734904B1 (en) * | 2016-11-22 | 2017-08-15 | SK Hynix Inc. | Digital low drop-out regulator and resistive memory device using the same |
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| CN114257216A (en) * | 2020-09-22 | 2022-03-29 | 深圳英集芯科技股份有限公司 | Two-phase three-order ring oscillator circuit, related chip and electronic device |
| CN112256081A (en) * | 2020-10-27 | 2021-01-22 | 电子科技大学 | Low dropout regulator with self-adaptive charge pump |
| CN214098248U (en) * | 2020-12-31 | 2021-08-31 | 深圳开阳电子股份有限公司 | Low-power consumption LDO circuit |
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| CN115357080A (en) | 2022-11-18 |
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