CN116827087A - Switching power supply current estimation method applied to DCM/BCM mode - Google Patents
Switching power supply current estimation method applied to DCM/BCM mode Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application provides a switching power supply current estimation method applied to DCM/BCM mode, which is used for realizing approximate sampling of inductance current and comprises the following steps: according to the input voltage Vin, the inductance L and the output voltage Vo of the switching power supply, determining the inductance current I of the switching power supply under the condition of turn-off and turn-on L Is a slope of (2); designing an inductance current estimation circuit comprising a Vin sampling circuit, a Vo sampling circuit, an RC filter circuit and a charging and discharging circuit; the Vin sampling circuit and the Vo sampling circuit are utilized to sample the input voltage Vin and the output voltage Vo of the switching power supply to obtain a sampling input voltage and a sampling output voltage, and the capacitor C is charged and discharged through the sampling input voltage and the sampling output voltage, so that the slope of the sampling voltage Vcs on the capacitor C and the inductance current I L Is proportional to the slope of the inductor current estimation circuit, and the proportionality coefficient is the equivalent resistance Rcs of the inductor current estimation circuit; inductor current I L Equivalent voltage Vcs and inductance current estimation circuitThe ratio of the equivalent resistances Rcs.
Description
Technical Field
The application relates to a switching power supply current estimation method applied to DCM/BCM mode, which can be applied to the power supply control field of non-resonant switching topology structure.
Background
The discontinuous conduction mode (Discontinuous Conduction Mode, DCM) is that the inductor current always drops to 0 during the switching cycle, meaning that the inductor is properly "reset", i.e. the inductor current is zero at the beginning of the switching cycle.
The critical conduction mode (Boundary Conduction Mode, BCM) monitors the inductor current for the controller and the power switch is turned off immediately upon detecting a current equal to zero. The controller always "resets" the inductor current to activate the switch. The BCM control realizes that the inductor current just drops to zero in each switching period through frequency conversion control, and enters the beginning stage of the next period.
And (3) current sampling: by means of a suitable circuit, the current information of the inductive devices in the system can be detected and this signal is passed to the internal control module.
Current estimation: the current information of the inductive device in the system is not needed to be obtained through a current sampling circuit, and a signal proportional to the inductance current of the inductive device is constructed through indirectly sampling some simple signals through an internal proper circuit module by utilizing the working principle of the inductive device.
With the continuous improvement of functions and performances of electronic devices, higher and higher requirements are being put on power supply devices for supplying power to the electronic devices, such as high power density, high efficiency, high dynamics, etc. Under such a demand, the power supply design needs to reduce peripheral devices as much as possible, reduce device loss, adopt a control mode with high dynamic characteristics, and the like. Current mode control has faster dynamic response characteristics and simpler compensation than voltage mode control, and current mode control designs are becoming increasingly favored. However, compared with the voltage mode control, the current mode control needs to sample the voltage information and also needs to sample the related current information. Conventional current sampling methods are mainly represented by two types: direct current resistance sampling (DCR sampling) and applied resistance sampling. The DCR sampling method utilizes parasitic resistance of the inductor to sample current information, and the method has lossless characteristics and does not bring extra loss, but needs more peripheral devices to be matched with high-speed and high-precision operational amplifiers. The additional resistor sampling method is to add a sampling resistor into a system loop, and obtain current information by sampling the voltage drop of the inductor current flowing through the resistor. The method can directly obtain current information, but the sampled information is easy to be interfered at the switching moment of the switching tube due to the influence of noise and the like, and meanwhile, extra loss is caused by the current flowing through an externally added resistor, so that the efficiency is influenced. Inaccuracy in current sampling will affect system stability and dynamic performance, while current sampling methods employing too many peripheral devices will affect system power density and sampled current reliability. Therefore, finding a simple and reliable method of obtaining current information is of great value for current mode control applications.
In the prior art, two methods for obtaining current information mainly exist, namely a DCR sampling method and an external resistor sampling method.
The structural diagram of the DCR sampling method is shown in fig. 1, a group of series-connected RCs are connected in parallel at two ends of an inductor, and inductance current information can be obtained by selecting proper R values and C values.
The corresponding principle is as follows, let the current flowing through the inductor L be I L Rs is parasitic resistance of the inductor, and the voltages at two ends of the capacitor C can be obtained according to the principle of voltage equality and voltage division of the parallel circuit:
(1)
by adjusting the external RC value such that L/rs=rc, equation (1) can be simplified to:
(2)
therefore, the voltage at two ends of the capacitor can accurately reflect the current information under the proper peripheral parameter setting, and the sampling resistance of the current at this time is the parasitic resistance Rs of the internal inductance.
The DCR sampling method can accurately sample the inductance current information under ideal conditions, but in the practical application process, the inductance L and Rs can change along with the influence of factors such as process, temperature and aging, and the DCR sampling method can accurately sample the current information only under the condition of L/rs=rc, otherwise, the sampling accuracy is greatly influenced. Meanwhile, the method needs more peripheral separation devices such as a resistor R and a capacitor C, and a group of voltage dividing resistors are connected in parallel to the capacitor C in order to adjust the current sampling resistor in some cases, so that the power density of the system is reduced. In addition, because Rs is small, the voltage drop generated by the inductor current flowing through Rs is only tens of mV, and the signal is also a ripple signal working at MHz, so that a high-precision and high-bandwidth operational amplifier is required to sample and then can be used for current mode control. And the design of the high-speed and high-precision operational amplifier requires a larger area, which further influences the realization of high power density.
In order to reduce peripheral devices, an external resistor sampling method is shown in fig. 2, a resistor Rcs is directly connected in series in a system loop, and then the two ends of the resistor are sampled through a high-speed and high-precision operational amplifier to obtain current information.
Since the currents in the series circuit are equal, the current in Rs is equal to the current I flowing through the inductor L The voltage drop across resistor Rcs is:
(3)
rcs is the sampling resistor in the circuit, and appropriate values can be selected according to design requirements.
Compared with the DCR sampling method, the external resistor sampling method only needs one peripheral device Rcs, so that the periphery is simpler and the power density is improved more favorably. However, the additional resistor Rcs brings additional loss, which reduces the system efficiency. Meanwhile, when Rcs is not grounded, differential sampling is needed by a high-speed and high-precision operational amplifier, and the differential sampling can be used for current mode loop control, so that the area of a control chip is increased. Sometimes, according to different structures (such as Boost structures), the sampling resistor Rcs is connected between the power tube and the ground, so that high-speed and high-precision operational amplification can be omitted, but at the moment, current is sensitive to noise of switching of a switch, and the sampling precision is greatly influenced.
Disclosure of Invention
The application provides a switching power supply current estimation method applied to DCM/BCM mode, so as to realize the estimation of inductance current.
The specific technical scheme of the application is as follows: a switching power supply current estimation method applied to DCM/BCM mode comprises the following steps:
according to the input voltage Vin, the inductance L and the output voltage Vo of the switching power supply, determining the inductance current I of the switching power supply under the condition of turn-off and turn-on L Is a slope of (2);
designing an inductance current estimation circuit comprising a Vin sampling circuit, a Vo sampling circuit, an RC filter circuit and a charging and discharging circuit, wherein the value of RC product is equal to the value of inductance L;
the Vin sampling circuit and the Vo sampling circuit are utilized to sample the input voltage Vin and the output voltage Vo of the switching power supply to obtain the sampled input voltage and the sampled output voltage, and the capacitor C in the RC filter circuit is charged and discharged through the sampled input voltage and the sampled output voltage under the control of the charging and discharging circuit, so that the slope of the sampled voltage Vcs on the capacitor C and the inductance current I L Is proportional to the slope of the inductor current estimation circuit, and the proportionality coefficient is the equivalent resistance Rcs of the inductor current estimation circuit;
inductor current I L The equivalent is the ratio of the sampling voltage Vcs to the equivalent resistance Rcs of the inductor current estimation circuit.
The technical scheme is further designed as follows: the Vin sampling circuit samples an input voltage Vin through a first voltage dividing resistor R1 and a second voltage dividing resistor R2; the Vo sampling circuit samples the output voltage Vo by using a first voltage dividing resistor R1 and a second voltage dividing resistor R2 which are corresponding to the resistance value in the Vin sampling circuit.
The inductance current estimation circuit generates a current Iin proportional to the input voltage Vin and a current Io proportional to the output voltage Vo through two groups of voltage-to-current circuits respectively.
The voltage-to-current circuit consists of an operational amplifier, an NMOS tube and a resistor R in the RC filter circuit.
The technical scheme is further designed as follows: the capacitor C is charged through the current Iin in the switching-on stage of the main power tube of the switching power supply, and is discharged through the current Io in the switching-off stage of the main power tube of the switching power supply, so that the sampling voltage Vcs is generated.
The equivalent resistance。
The technical scheme is further designed as follows: the sampled input voltage and the sampled output voltage are input into a subtracting circuit, and the capacitor C is charged and discharged by the output of the subtracting circuit to generate a sampled voltage Vcs.
The technical scheme is further designed as follows: the RC filter circuit is provided with two groups of resistors R and capacitors C which are the same, the capacitor C in the RC filter circuit is charged through current Iin in the conduction stage of a main power tube of the switching power supply, and the voltage on the capacitor C is V1; charging a capacitor C in the other RC filter circuit through a current Io in the switching-off stage of a main power tube of the switching power supply, wherein the voltage on the capacitor C is V2; v1 and V2 are input into a subtracting circuit to obtain a sampling voltage Vcs.
The technical scheme is further designed as follows: the equivalent resistanceK is the subtraction circuit coefficient.
The technical scheme is further designed as follows: the charge-discharge circuit adopts an NMOS tube as a switch for controlling the charge-discharge state of the capacitor C.
The application also provides a switching power supply current estimation circuit applied to the DCM/BCM mode, which comprises a Vin sampling circuit, a Vo sampling circuit, an RC filter circuit and a charging and discharging circuit.
Compared with the prior art, the application has the following beneficial effects:
1. the current estimation method only needs to sample the output voltage Vo and the input voltage Vin of the switching power supply, and for the switching control chip, as voltage stabilization regulation, input voltage undervoltage/overvoltage protection and the like are needed, vin and Vout are needed to be sampled, so that the inductor current can be sampled without adding an additional circuit.
2. The circuit designed by the application does not need high-speed and high-precision operational amplifier, only needs two groups of current and current mirror circuits which are related to Vin and Vo, and only needs common operational amplifier in related voltage-to-current and subtracting circuits, thereby effectively reducing the chip area and the system application complexity and improving the power density of a module power supply.
3. According to the method for obtaining the inductance current by using the estimation algorithm, no sampling resistor is additionally introduced into the system, so that the system loss in the application process is reduced, and the improvement of the system efficiency is facilitated.
4. In the switching process of the switching tube, the voltage on the capacitor cannot be suddenly changed, so that the constructed inductance current information is insensitive to switching noise, and the current mode control is facilitated.
5. The estimation algorithm provided by the application can flexibly obtain different types of inductor current information, namely complete inductor current, inductor current in a conduction stage and inductor current information in a turn-off stage, so that the method can be conveniently used for various current mode control, such as peak current mode, average current mode, COT control and the like.
Drawings
FIG. 1 is a diagram of a prior art DCR sampling architecture;
FIG. 2 is a diagram of a prior art external resistor sampling structure;
FIG. 3 is a block diagram of an RC filter;
FIG. 4 is a circuit diagram illustrating a current estimation method according to an embodiment;
FIG. 5 is a simulation waveform diagram of a current estimation method according to an embodiment;
FIG. 6 is a circuit diagram of a second current estimation method according to the second embodiment;
FIG. 7 is a simulation waveform diagram of a current estimation method according to the second embodiment;
FIG. 8 is a circuit diagram of a three-current estimation method according to an embodiment;
fig. 9 is a simulation waveform diagram of a three-current estimation method according to an embodiment.
Detailed Description
The following describes the specific technical scheme of the application further with reference to the accompanying drawings:
the current sampling method of the application is based on the following principle:
the principle of the application is that inductance current information is obtained by constructing an RC filter circuit and detecting slope equivalence of the RC filter circuit. According to the application, the external inductance current slope is estimated by utilizing the initial charge-discharge slope (instead of the filtering voltage stabilizing effect) of the RC filter under a certain constraint condition (see formula (5)) through limiting the condition of the RC filter design, so that external inductance current information can be approximately obtained in a chip without an external high-bandwidth operational amplifier and related peripheral circuits, and inductance current estimation is realized.
Since the inductor current is an amount that varies with time, the slope of the inductor current is determined by the voltage across the inductor, which is a fixed value when the voltage across the inductor is fixed. For a non-resonant switching power supply, the voltage at two ends of an inductor is fixed in the on/off time of a switching tube, and the inductor current is obtained by integrating the slope of the corresponding inductor current in time in the on and off time of the switching tube respectively.
According to theoretical analysis of the inductance current, the application needs to construct a group of quantities which are in direct proportion to the slope of the external inductance current in the on/off time period of the switching tube in the chip, the proportionality coefficient is a fixed value, and then the quantities are integrated with time, so that accurate current information can be obtained.
The most easily implemented method is the charge and discharge of the capacitor due to the integration of time inside the chip, but the integration of time with a fixed slope is also required to reflect the amount of inductor current, as shown in fig. 3, which is an RC filter structure.
The voltage of the capacitor C is:
（4）
when t/RC < <1, the formula (4) can be simplified as follows according to Taylor's equation:
（5）
therefore, in the case of larger RC product, the slope of the initial voltage change of the RC filter capacitor is a fixed value V 1 and/RC, integrating the amount with time, so as to realize the construction of the inductor current internally.
The non-resonant switching power supply mainly comprises three types: buck, boost and Buck-Boost. The slopes of the inductive currents under the on and off conditions of the three switching power supply structures are shown in the table:
| slope of | Buck | Boost | Buck-Boost |
| Conduction slope sn | (Vin-Vo)/L | Vin/L | Vin/L |
| Shut-off slope sf | -Vo/L | (Vin-Vo)/L | -Vo/L |
Wherein Vin, vo, L are the system input voltage, output voltage and inductance, respectively. In a specific application process, only the external input voltage and the external output voltage are required to be sampled, the value corresponding to the on/off slope is built through an internal circuit, and the internal RC filter is required to be RC=L in design.
Embodiment one:
in this embodiment, taking a Buck-Boost structure as an example, an implementation manner of the switching power supply current estimation method is illustrated, and a schematic diagram of an inductor current obtained by sampling an input voltage Vin and an output voltage Vo is shown in fig. 4.
Wherein the switching power supply power stage section includes 4 power transistors Q1, Q2, Q3 and Q4, and an inductance L. The drain terminal of Q1 links to each other with input power Vin, and the source terminal of Q1 is connected with inductance L left end and the drain terminal of Q2, and the source terminal of Q2 is grounded, and the right-hand member of L is connected with the source terminal of Q3 and the drain terminal of Q4, and the drain terminal of Q3 links to each other with output voltage Vo, and the source terminal of Q4 links to each other with ground, and the bars end of Q1 is controlled by ON, and the bars end of Q2 and Q4 is controlled by ON and OFF jointly, and the bars end of Q3 is controlled by OFF. Q1-Q4 have three working modes in a system switching period, namely 1) when ON is high level, Q1 and Q4 are conducted, Q2 and Q3 are turned off, and at the moment, the current of the inductor L is linearly increased; 2) When OFF is high level, Q2 and Q3 are on, Q1 and Q4 are OFF, and the current of the inductor L is linearly reduced; 3) When both ON and OFF are low, Q2 and Q4 are ON, Q1 and Q3 are OFF, and the current of the inductor L remains unchanged.
The inductance current estimation circuit is designed in a control chip for controlling the power level and comprises a Vin sampling circuit, a Vo sampling circuit, a voltage-to-current circuit, a current mirror circuit and a charge-discharge circuit comprising an RC filter structure; the method can be divided into three parts according to functions: i) Generating a current Iin related to the input voltage; II) generating a current Io related to the output voltage; III) charging and discharging the capacitor through Iin and Io, generating a voltage Vcs proportional to the inductor current.
I) The connection relation of the circuit is as follows: the upper end of the first voltage dividing resistor R1 is connected with an input power supply Vin, the lower end of the first voltage dividing resistor R1 is connected with the upper end of the second voltage dividing resistor R2, the lower end of the R2 is connected with the ground, vin voltage dividing signals vin_s are generated by utilizing R1 and R2, and the voltage dividing resistors R1 and R2 form a Vin sampling circuit; the common node of the common node R1 and the common node R2 are connected with the common node R1, the common node R1 is connected with the common node R2, the common node R is connected with the common node R1, the drain end of the M1 is connected with the gate end and the drain end of the PMOS tube M2, A1, M1 and R form a voltage-to-current (V2I) circuit, and the generated current is in direct proportion to Vin; the source end of the M2 and the PMOS tube M3 are connected with an internal power supply of the chip, the grid electrode of the M3 is connected with the grid electrode and the drain electrode of the M2, the drain end of the M3 is connected with the drain end of the NMOS M4, the M2 and the M3 form a current mirror circuit, the proportionality coefficient is k1, the output current of the M3 is equal to or proportional to the current of the M2, and the finally obtained Iin is a current proportional to the input voltage. The circuit connection relation in II) is as follows: since the voltage division coefficient of Vo is required to be the same as that of Vin, two first voltage division resistors R1 and second voltage division resistors R2 which are the same as the voltage division resistance of Vin are adopted, the upper end of R1 is connected with the output voltage Vo, the lower end of R1 is connected with the upper end of R2, the lower end of R2 is connected with the ground, the voltage division resistors R1 and R2 in the part form a Vo sampling circuit, the common end of R1 and R2 is connected with the same phase end of A2, the inverting end of A2 is connected with the source end of an NMOS tube M5 and the upper end of a resistor R, the grid electrode of M5 is connected with the output end of A2, the drain end of M5 is connected with the grid end of a PMOS tube M6, A2, M5 and R form a voltage-to-current converting circuit, currents proportional to Vo are generated, the source ends of PMOS tubes M6 and M7 are connected with an internal power supply of a chip, the grid electrode of M7 is connected with the grid electrode of M6, the drain end of M7 is connected with the grid end and the drain end of an NMOS tube M11, the source end of M11 is connected with the ground, the grid electrode of an NMOS tube M10 is connected with the grid electrode of M10 and the drain end of M10 is proportional to the ground, and the drain end of the NMOS tube M10 is proportional to the drain end of M10, and the drain end of the PMOS tube is 3 is proportional to the ground 3.
III) NMOS tubes M4, M9 and M8 are switches for controlling the charge and discharge states of the capacitor C under three modes, and a charge and discharge circuit is formed. The grid of M4 is connected with an ON signal, the source of M4 is connected with the upper end of a capacitor C, the grid of M9 is connected with an OFF, the drain of M9 is connected with the upper end of the capacitor C, the grid of M8 is controlled by an oneshot signal, the oneshot is a short pulse signal triggered when the ON and OFF are simultaneously 0, the source of M8 is connected with a voltage source VSET, wherein the VSET can be set to 0 or a non-zero voltage, and the voltage is used for determining Vcs at the end of each switching periodAn initial voltage for a post reset. When ON is high, iin charges capacitor C and Vcs rises linearly; when OFF is high, io discharges capacitor C and Vcs drops linearly; when oneshot is high, the Vcs voltage is reset to V SET Values.
In the Buck-Boost structure of the embodiment, when Q1 and Q4 are conducted, the inductor L stores energy, and the inductor current rises; when Q2 and Q3 are conducted, the inductor L discharges, and the inductor current drops; when Q2 and Q4 are on, the inductor L is kept, and the inductor current is unchanged. When the device works in BCM/DCM mode, the expression of the inductor current is shown as the following formula:
(6)
wherein the method comprises the steps ofT on ，T off ，T dead The on-time of Q1 and Q4, the on-time of Q2 and Q3 and the on-time of Q2 and Q4 are respectively.I peak The peak current of the inductor current is Vin/L Ton.
The Vin sampling circuit and the Vo sampling circuit in the control chip sample the input voltage Vin and the output voltage Vo through the same first voltage dividing resistor R1 and the second voltage dividing resistor R2 to obtain vin_s and vo_s. The input/output voltage related currents Iin and Io are obtained through a voltage-to-current circuit and a current mirror circuit respectively, and the corresponding Iin and Io have the following expressions:
(7)
(8)
for convenience of description, k1, k2 and k3 are set to 1 here, but the actual design process may be arbitrarily positive as required, and k1, k2 and k3 may be arbitrarily positive.
When Q1 and Q4 are ON, the corresponding ON signal goes high, iin charges capacitor C, and Vcs rises linearly at this time; when Q2 and Q3 are on, the corresponding OFF signal goes high, io discharges the capacitor C, and Vcs linearly decreases at this time; when (when)When Q2 and Q4 are on, the oneshot signal goes high and Vcs is discharged to V SET . The expression for Vcs for these three phases is:
(9)
wherein R, C, rcs are the resistance, capacitance and equivalent sampling resistance of the inductance current estimation circuit of the filter respectively. Comparing equation (6) with equation (9), when the internal design is such that rc=l, the corresponding equivalent sampling resistor RCs expression is:
(10)
formula (9) may be represented as:
(11)
as is clear from formula (11), the Vcs node voltage and inductor current I in the internal circuitry of the chip L Proportional, proportional coefficient is equivalent to the sampling resistor Rcs, and V SET Is the initial voltage of Vcs, which can be chosen to be either 0 or a non-zero voltage, depending on the chip design requirements. Vcs can thus be seen as pair I L Can be used for subsequent current mode control, and can be seen from equations (9) and (10) that only the values of Vin and Vo are sampledIs a value of (2).
The simulation operation result of this embodiment is as follows:
fig. 5 shows an inductor current estimation waveform corresponding to the configuration of fig. 4. In the simulation, input voltages vin=70v, vo=30v, system period t=1us, on time ton=0.293 us, toff=0.693 ns, tdead=10ns, V are set SET =0，R1/R2=99。
The waveforms in FIG. 5 show the actual inductor current I from top to bottom L ON signal of Q1 and Q4, OFF signal of Q2 and Q3, ON signal of Q2 and Q4, oneshot, estimated inductor currentSignal Vcs. Simulation shows that when ON is high level, I L The corresponding Vcs is increased, the designed equivalent sampling resistance Rcs is 10mΩ, when I L Increasing by 7A, the corresponding Vcs increases by 70mV; when OFF is high level, I L When Vcs decreases and the OFF high level ends, I is known from the inductor volt-second balance L Decreasing to 0, the corresponding Vcs also becomes 0; during oneshot conduction, vcs is forced to reset to 0 in case the estimation circuit calculates a bias in one cycle, resulting in error accumulation affecting the current estimation results in the following cycle. In summary, in the high-level stage of ON, the inductance current increases linearly by 7A, and the corresponding Vcs increases linearly by 70mV; in the phase of OFF being high level, the inductance current is linearly reduced by 7A, and the corresponding Vcs is linearly reduced by 70mV; at dead time (oneshot), both inductor current and Vcs remain unchanged. During the working process of the system, vcs and inductance current are in a direct proportion relation, the proportion coefficient is an equivalent sampling resistor Rcs, and the resistance value of the Rcs is 10mΩ. Vcs can thus reflect the inductor current I L And the inductor current is approximately sampled.
According to the embodiment, the resistor R for generating the currents related to Vin and Vo can be arranged outside the chip and used for adjusting the resistors R with different resistance values according to different inductances, so that the estimated inductance current slope can be flexibly adjusted, and the application under different inductance conditions can be met.
Embodiment two:
in this embodiment, a Buck-Boost structure is taken as an example, and a structural diagram of this embodiment is shown in fig. 6.
The power stage component of the switching power supply is the same as that of the first embodiment, and the inductance current estimation circuit inside the control chip is different, in this embodiment, the estimation part can still be divided into three parts: i) Generating a voltage signal V1 with a change slope proportional to Vin; II) generating a voltage signal V2 with a change slope proportional to Vo; III) generates a voltage signal Vcs proportional to the inductor current.
The upper end of the middle resistor R1 is connected with Vin, the lower end of the R1 is connected with a resistor R2, the lower end of the R2 is connected with the ground, and the R1 and the R2 form a voltage division network, namely a Vin sampling circuit, so as to obtain an input voltage sampling voltage vin_s; the common node of R1 and R2 is connected with the in-phase end of the conventional operational amplifier A1, the inverting end is connected with the source end of the NMOS tube M1 and the upper end of the resistor R, the output end of the A1 is connected to the grid electrode of the M1, the drain end of the M1 is connected with the grid electrode and the drain electrode of the PMOS tube M2, and the A1, the M1 and the R form a V2I voltage-to-current circuit to generate current proportional to Vin; the PMOS tubes M3 and M2 form a current mirror circuit, and the proportionality coefficient is k1, so that Iin and Vin are in direct proportion; the drain end of the M3 is connected with the drain end of the NMOS tube M10, the grid electrode of the M10 is controlled by an ON signal, the source end of the M10 is connected with one end of a capacitor C, the other end of the capacitor C is connected to the ground, the drain end of the NMOS tube M8 is connected with the intersection point of the source ends of the capacitor C and the M10, the grid electrode of the M8 is controlled by oneshot, and the source end of the M8 is connected with a VSET power supply, wherein the VSET can be 0 or a non-zero positive potential.
The circuit structure in II) is symmetrical with I), the basic connection mode is basically the same as that in 1), and the only difference is that the grid electrode of the NMOS tube M11 is controlled by an OFF signal.
III), the left end of the resistor R3 is connected with V1, and the right end of the resistor R3 is connected with the upper end of the resistor R4 and the same-phase end of the operational amplifier A3; the other group of resistors R3 and R4 with equal resistance values are correspondingly connected with V2 at the left end of R3, the right end of R3 is connected with the left end of R4 resistor and the inverting end of operational amplifier A3, and the right end of R4 is connected with the output of A3, so that a subtracting circuit is formed.
Compared with the first embodiment, the input voltage Vin and the output voltage Vo of the present embodiment all work in a charging mode, and two capacitors C with the same capacitance are adopted, the switching power supply is turned on and off to charge the corresponding capacitor C by V1 and V2 respectively, and the sampling voltage Vcs is obtained by combining the on period and the off period through a subtracting circuit. The expressions for V1, V2 and Vcs are:
(12)
(13)
(14)
in chip design, it is necessary to ensure that rc=l, and the expression of the corresponding equivalent resistance RCs becomes:
(15)
combining equation (6), equation (14) and equation (15) can yield Vcs and I L The relation between them is as in the formula (16).
(16)
From equation (16), the chip generates a voltage signal Vcs and an inductor current I through the example two circuits L Proportional, the proportionality coefficient is Rcs. Therefore, the inductance current I can be obtained under the condition that the current sampling circuit is not sampled by the estimation algorithm example circuit L Information.
The simulation operation result of this embodiment is as follows: fig. 7 is a waveform corresponding to the inductor current estimation under the configuration of fig. 6. The conditions used in the simulation are identical to those of the example, and the coefficient k of the subtracting circuit is r3/r4=1. The waveforms from top to bottom in the figure respectively represent the actual inductor current I L The ON signal of Q1 and Q4, the OFF signal of Q2 and Q3, the oneshot signal of Q2 and Q4, the voltage waveform V1 reflecting the rising slope of the inductor current, the voltage waveform V2 reflecting the falling slope of the inductor current, the estimated inductor current signal Vcs. In this example, the equivalent sampling resistance was set to 10mΩ as well, and as can be seen from simulation, at I L During the rising phase, vcs is also linearly increased by 70mV in the period of 7A of linear increase of the inductance current; at I L In the falling stage, during the period that the inductance current is linearly reduced by 7A, vcs is also linearly reduced by 70mV, and Vcs can well reflect I L Is a variation of (c). In summary, in the high-level stage of ON, the inductance current increases linearly by 7A, and the corresponding Vcs increases linearly by 70mV; in the phase of OFF being high level, the inductance current is linearly reduced by 7A, and the corresponding Vcs is linearly reduced by 70mV; in dead time (oneshot)) Both the inductor current and Vcs remain unchanged. During the working process of the system, vcs and inductance current are in a direct proportion relation, the proportion coefficient is an equivalent sampling resistor Rcs, and the resistance value of the Rcs is 10mΩ. Vcs can thus reflect the inductor current I L And the inductor current is approximately sampled. In this embodiment, the rising and falling stages of the inductor current are estimated separately, so that more flexible control can be realized. The same embodiment can also place the resistors generating the currents related to Vin and Vo outside the chip, and the resistors are used for adjusting the resistors with different resistance values according to different inductances, so that the estimated inductance current slope is flexibly adjusted, and the application under different inductance conditions can be met.
Embodiment III:
in this embodiment, a Buck-Boost structure is taken as an example, and a specific scheme of this embodiment is shown in fig. 8.
The power stage components in fig. 8 are consistent with the previous examples, and the control chip internal inductor current estimation circuit is divided into three parts: i) Generating a voltage signal V1 proportional to an input voltage Vin; II) generating a voltage signal V2 proportional to the output voltage Vo; III) V1 and V2 are used to generate a voltage signal Vcs proportional to the inductor current.
I) The upper end of the middle resistor R1 is connected with Vin, the lower end of the resistor R1 is connected with the resistor R2, the lower end of the resistor R2 is connected with ground, and the resistor R1 and the resistor R2 form a Vin sampling circuit. The same-phase end of the operational amplifier A1 is connected with a common node of R1 and R2, the opposite-phase end of the operational amplifier A1 is connected with the output end of the operational amplifier A1, the source end of the NMOS tube M1 is connected with the output end of the operational amplifier A1, the grid electrode of the operational amplifier M1 is controlled by an ON signal, and the drain end of the operational amplifier M1 is connected with the drain end of the operational amplifier M2 to generate V1. The gate of M2 is controlled by the complementary signal on_b of ON, and the source of M2 is grounded. The circuit in II) is symmetrical with respect to I), essentially connected in correspondence, with the difference that the gates of M3 and M4 are controlled by OFF and its complementary signal off_b, respectively. III) two groups of R3 and R4, the operational amplifier A3 forms a subtracting circuit, the output of A3 is connected with the left end of a resistor R, the right end of R is connected with one end of a capacitor C and the drain end of an NMOS tube M5, the other end of the capacitor C is grounded, the grid electrode of the capacitor C is controlled by oneshot signals, the source end of the M5 is connected with VSET potential, and the VSET potential can be 0 or non-zero potential. In this embodiment, the capacitor C is charged to obtain Vcs by the difference between V1 and V2, thereby utilizing a subtracting circuit and RC filter networkRealize pair I L Is a sample of the sample.
The expressions corresponding to V1, V2 and Vcs are:
(17)
(18)
(19)
in the internal chip design, rc=l needs to be ensured as well, and the equivalent resistance is shown in equation (15).
From equations (6), (15), (17), (18) and (19), vcs and inductor current I can be obtained L Is a relational expression (20).
(20)
From formula (20), vcs and I L The scaling factor is Rcs, and VSET may be selected to be 0 or non-zero depending on the circuit design requirements.
Simulation operation result of this embodiment: fig. 9 is a waveform corresponding to the inductor current estimation under the configuration of fig. 8. The parameters in the simulation diagram are consistent with the parameters selected in the two examples, and waveforms from top to bottom in the diagram respectively represent the actual inductance current I L The ON signal of Q1 and Q4, the OFF signal of Q2 and Q3, the ON signal of Q2 and Q4, the oneshot signal, the input voltage waveform V1 sampled in the ON phase, the output voltage waveform V2 sampled in the OFF phase, the estimated inductor current signal Vcs. Through a subtracting circuit, voltages at two ends of the inductor in the ON-off stage can be constructed, then the voltages at two ends of the inductor in different stages are integrated by utilizing an RC network, and in the stage that ON is high level, the inductance current is linearly increased by 7A, and the corresponding Vcs is linearly increased by 70mV; in the phase of OFF being high level, the inductance current is linearly reduced by 7A, and the corresponding Vcs is linearly reduced by 70mV; at dead time (oneshot), inductanceBoth the current and Vcs remain unchanged. During the working process of the system, vcs and inductance current are in a direct proportion relation, the proportion coefficient is an equivalent sampling resistor Rcs, and the resistance value of the Rcs is 10mΩ. Vcs can thus reflect the inductor current I L And the inductor current is approximately sampled.
As can be seen from the simulated inductor current estimated waveforms in the above embodiments, the present application can not only construct a complete inductor current waveform, but also construct a partial inductor current waveform according to design requirements.
If the inductance in each embodiment is changed into the transformer to form the isolation/non-isolation structure, the inductance current of the primary side of the isolation/non-isolation transformer can be estimated by the method provided by the application.
The capacitor C in the above embodiment may be pulled down to zero potential during discharging, but sometimes, considering the static operating point of the later stage circuit, it may also be reset to a non-zero voltage, one method is to add a non-zero potential circuit under the switch tube controlled by the oneshot signal.
Embodiment four:
the application provides a switching power supply current estimation circuit applied to DCM/BCM mode, which comprises a Vin sampling circuit, a Vo sampling circuit, an RC filter circuit and a charging and discharging circuit. The implementation circuit of the current estimation circuit is shown in fig. 4, 6 or 8.
The technical scheme of the application is not limited to the embodiments, and all technical schemes obtained by adopting equivalent substitution modes fall within the scope of the application.
Claims (11)
1. A switching power supply current estimation method applied in DCM/BCM mode, comprising the steps of:
according to the input voltage Vin, the inductance L and the output voltage Vo of the switching power supply, determining the inductance current I of the switching power supply under the condition of turn-off and turn-on L Is a slope of (2);
designing an inductance current estimation circuit comprising a Vin sampling circuit, a Vo sampling circuit, an RC filter circuit and a charging and discharging circuit, wherein the value of RC product is equal to the value of inductance L;
the input voltage Vin and the output voltage Vo of the switching power supply are sampled by the Vin sampling circuit and the Vo sampling circuit to obtain a sampled input voltage and a sampled output voltage, and a capacitor C in the RC filter circuit is charged and discharged by the sampled input voltage and the sampled output voltage under the control of the charging and discharging circuit, so that the slope of the sampled voltage Vcs on the capacitor C and the inductance current I L Is proportional to the slope of the inductor current estimation circuit, and the proportionality coefficient is the equivalent resistance Rcs of the inductor current estimation circuit;
inductor current I L The equivalent is the ratio of the sampling voltage Vcs to the equivalent resistance Rcs of the inductor current estimation circuit.
2. The switching power supply current estimation method applied in DCM/BCM mode as claimed in claim 1, wherein: the Vin sampling circuit samples an input voltage Vin through a first voltage dividing resistor R1 and a second voltage dividing resistor R2; the Vo sampling circuit samples the output voltage Vo by using a first voltage dividing resistor R1 and a second voltage dividing resistor R2 which are corresponding to the resistance value in the Vin sampling circuit.
3. The switching power supply current estimation method applied in DCM/BCM mode as claimed in claim 2, wherein: the inductance current estimation circuit generates a current Iin proportional to the input voltage Vin and a current Io proportional to the output voltage Vo through two groups of voltage-to-current circuits respectively.
4. A switching power supply current estimation method applied in DCM/BCM mode as claimed in claim 3 wherein: the voltage-to-current circuit consists of an operational amplifier, an NMOS tube and a resistor R in the RC filter circuit.
5. A switching power supply current estimation method applied in DCM/BCM mode as claimed in claim 3 wherein: the capacitor C is charged through the current Iin in the switching-on stage of the main power tube of the switching power supply, and is discharged through the current Io in the switching-off stage of the main power tube of the switching power supply, so that the sampling voltage Vcs is generated.
6. The switching power supply current estimation method applied in DCM/BCM mode as set forth in claim 5, wherein: equivalent resistance of the inductance current estimation circuit。
7. The switching power supply current estimation method applied in DCM/BCM mode as claimed in claim 2, wherein: the sampled input voltage and the sampled output voltage are input into a subtracting circuit, and the capacitor C is charged and discharged by the output of the subtracting circuit to generate a sampled voltage Vcs.
8. A switching power supply current estimation method applied in DCM/BCM mode as claimed in claim 3 wherein: the RC filter circuit is provided with two groups of resistors R and capacitors C which are the same, the capacitor C of the RC filter circuit is charged through current Iin in the conduction stage of a main power tube of the switching power supply, and the voltage on the capacitor C is V1; charging a capacitor C in the other RC filter circuit through a current Io in the switching-off stage of a main power tube of the switching power supply, wherein the voltage on the capacitor C is V2; the voltage V1 and the voltage V2 are input into a subtracting circuit to obtain a sampling voltage Vcs.
9. A switching power supply current estimation method applied in DCM/BCM mode as claimed in claim 7 or 8, wherein: equivalent resistance of the inductance current estimation circuitK is the subtraction circuit coefficient.
10. A switching power supply current estimation method applied in DCM/BCM mode as claimed in any one of claims 5, 7 or 8 wherein: and the charge and discharge circuit adopts an NMOS tube as a switch for controlling the charge and discharge state of the capacitor C.
11. The switching power supply current estimation circuit applied to DCM/BCM mode is characterized in that: the circuit comprises a Vin sampling circuit, a Vo sampling circuit, an RC filter circuit and a charging and discharging circuit.
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