CN115347087A - Growth method of novel LED epitaxial stress release layer and chip prepared by method - Google Patents

Growth method of novel LED epitaxial stress release layer and chip prepared by method Download PDF

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CN115347087A
CN115347087A CN202210953377.3A CN202210953377A CN115347087A CN 115347087 A CN115347087 A CN 115347087A CN 202210953377 A CN202210953377 A CN 202210953377A CN 115347087 A CN115347087 A CN 115347087A
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layer
superlattice
gan
stress release
growing
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吕腾飞
王淑娇
郭园
祝光辉
展望
芦玲
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Huaian Aucksun Optoelectronics Technology Co Ltd
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Huaian Aucksun Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction

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Abstract

A method for growing a novel stress release layer of an LED epitaxy comprises providing a substrate, and sequentially growing a buffer layer, a u-shaped GaN layer, an n-shaped GaN layer heavily doped with Si, a stress release layer, a light-emitting layer and a p-shaped GaN layer on the surface of the substrate; the growth method of the stress release layer comprises the following steps: sequentially/circularly growing a first superlattice layer and a second superlattice layer; the first superlattice layer comprises GaN layers and In which are periodically and alternately grown X Ga (1‑X) N layer, X is more than or equal to 0 and less than 0.8; the second superlattice layer comprises GaN layers and In which are periodically and alternately grown Y Ga (1‑Y) N layers, Y is more than or equal to 0 and less than 1. The invention improves stacking faults by arranging the first superlattice layerThe effect of (2) can prevent the phenomenon that the stacking faults generate electrical abnormity due to large lattice mismatch caused by directly growing the second superlattice layer, can effectively improve the crystallization quality, and increases the internal quantum efficiency so as to improve the luminous efficiency of the LED.

Description

Growth method of novel LED epitaxial stress release layer and chip prepared by method
Technical Field
The invention relates to the technical field of semiconductor illumination, in particular to a growth method of a novel LED epitaxial stress release layer and a chip prepared by the method.
Background
Group III nitrides (including AlN, gaN, inN and alloys thereof) taking GaN as a basic material are one of the most important wide band gap semiconductor material systems, and the unique band gap range, excellent optical and electrical properties and excellent mechanical properties of the materials ensure that the group III nitrides have wide application prospects in the fields of optical devices, electronic devices, semiconductor devices under special conditions and the like.
LEDs have become a fourth generation illumination source following incandescent, fluorescent, and high-intensity gas discharge lamps. Compared with the traditional illumination light source, the LED semiconductor illumination light source has the advantages that: high luminous efficiency, small volume, long service life, energy saving, environmental protection, etc.
In the current LED epitaxial growth process, because the two materials have different lattice constants, polarization effect and growth defect are easy to generate, the polarization effect and the growth defect can influence the photoelectric property of the materials, and the luminous efficiency of the LED is greatly reduced.
At present, an active layer of the LED epitaxial growth mostly adopts a plurality of periodic structure GaN/InGaN quantum well barrier regions, and electrons and holes are subjected to composite luminescence in a well layer InGaN material with a narrower energy band. Due to the different lattice constants of GaN and InGaN materials, polarization charges and defects are generated at the growth interface of the two materials, resulting in spatial separation of electron and hole wave functions and the generation of some non-recombination luminescent centers.
Disclosure of Invention
Aiming at the technical problems, the technical scheme provides a novel LED epitaxial stress release layer growth method and a chip prepared by the method, the effect of improving stacking faults is achieved by arranging a first superlattice layer, the phenomenon that the stacking faults generate electrical abnormity due to large lattice mismatch caused by directly growing a second superlattice layer is prevented, the crystallization quality can be effectively improved, and the internal quantum efficiency is increased, so that the LED luminous efficiency is improved; the problems can be effectively solved.
The invention is realized by the following technical scheme:
an epitaxial structure based on a novel LED epitaxial stress release layer comprises a substrate, and a buffer layer, a u-shaped GaN layer, a heavily-doped Si n-shaped GaN layer, a stress release layer, a light emitting layer and a p-shaped GaN layer which are sequentially stacked and grown on the surface of the substrate; the stress release layer comprises a first superlattice layer and a second superlattice layer which are sequentially/circularly stacked; the first superlattice layer comprises GaN layers and In which are cyclically and alternately stacked X Ga (1-X) N layer, the second superlattice layer comprises GaN layer and In layer alternately stacked cyclically Y Ga (1-Y) N layers; the In doping concentration In the first superlattice layer is less than or equal to the In doping concentration In the second superlattice layer.
Further, when the In doping concentration In the first superlattice layer is less than that In the second superlattice layer, the stress release layer comprises the first superlattice layer and the second superlattice layer which are sequentially stacked; the In doping concentration In the first superlattice layer is 0-5 multiplied by 10 18 atom/cm 3 (ii) a The In doping concentration In the second superlattice layer is 5 × 10 18 ～2×10 20 atom/cm 3 。
Further, in the first superlattice layer X Ga (1-X) The N layer and the GaN layer are circularly laminated for 1-3 periods, the thickness of each GaN layer In the first superlattice layer is 4-8 nm, and each In layer X Ga (1-X) The thickness of the N layer is 2 nm-4 nm, and a first superlattice layer with the total thickness of 10-20 nm is obtained; in the second superlattice layer Y Ga (1-Y) The N layer and the GaN layer are circularly laminated for 2-5 periods, the thickness of each GaN layer In the second superlattice layer is 5-10 nm, and each In layer Y Ga (1-Y) The thickness of the N layer is 2 nm-5 nm, and the second superlattice layer with the total thickness of 20-40 nm is obtained.
Further, the growth temperature of the first superlattice layer is 800-880 ℃, and the growth temperature of the second superlattice layer is 850-900 ℃.
Further, the GaN layer in the first superlattice layer has a doping concentration of si of 1-5 × 10 during growth 18 atom/cm 3 (ii) a The doping concentration of Si is 3-5 multiplied by 10 when the GaN layer in the second superlattice layer grows 18 atom/cm 3 。
Further, when the In doping concentration In the first superlattice layer is equal to that In the second superlattice layer, the In doping concentrations In the first superlattice layer and the second superlattice layer are both 0; the stress release layer comprises a first superlattice layer and a second superlattice layer which are stacked in a circulating mode, the first superlattice layer is a GaXN layer, and the GaXN layer grows through TEGa; the second superlattice layer is a GayN layer, and the GayN layer is grown by adopting TMGa.
Further, the lamination period of the GaXN layer and the GayN cycle is 2-5.
Furthermore, the buffer layer is a three-dimensional nucleation layer, and the three-dimensional nucleation layer is a plurality of GaN island-shaped structures distributed on the substrate at intervals.
Further, the P-type semiconductor layer comprises an undoped P-type GaN layer and/or a P-type GaN layer doped with P-type impurities which are arranged in a stacked mode.
A growth method of a novel LED epitaxial stress release layer is used for manufacturing the epitaxial structure based on the novel LED epitaxial stress release layer, and the specific method comprises the steps of providing a substrate, and sequentially growing a buffer layer, a u-shaped GaN layer, an N-shaped GaN layer heavily doped with Si, an N-shaped GaN layer, a stress release layer, a light emitting layer and a p-shaped GaN layer on the surface of the substrate; the growth method of the stress release layer comprises the following steps: sequentially/circularly growing a first superlattice layer and a second superlattice layer; the first superlattice layer comprises GaN layers and In which are periodically and alternately grown X Ga (1-X) N layer, X is more than or equal to 0 and less than 0.15; the second superlattice layer comprises GaN layers and In which are periodically and alternately grown Y Ga (1-Y) N layer, Y is more than or equal to 0 and less than 0.25.
Further, when both X and Y are equal to 0, the growth method of the stress release layer is as follows:
the first step is as follows: after the growth of the n-type GaN layer is finished, adjusting the temperature to 800-900 ℃, the pressure to 300mbar, and growing a GaXN layer with the thickness of 2-5 nm, wherein the GaXN layer grows by adopting TEGa;
the second step: maintaining the original temperature and pressure, and growing a GayN layer with the thickness of 5 nm-8 nm, wherein the GayN layer grows by adopting TMGa;
the third step: maintaining the original temperature and pressure, circulating the first step and the second step for 2-5 periods, and sequentially stacking and growing GaXN layers and GayN layers for 2-5 periods to obtain the stress release layer with the total thickness of 30-60 nm.
Further, when both X and Y are greater than 0, the growth method of the stress release layer is as follows:
the first step is as follows: after the growth of the n-type GaN layer is finished, adjusting the temperature to 800-880 ℃, the pressure to 300mbar, and firstly growing a GaN layer with the thickness of 4-8 nm, wherein the GaN layer is an n-type GaN layer doped with Si, and the doping concentration of Si in the GaN layer is 1-5 multiplied by 10 18 atom/cm 3 ；
The second step: constant temperature 800-880 deg.C, constant pressure 300mbar, growth thickness of 2-4 nm InGaN layer with In doping concentration of 0-5 × 10 18 atom/cm 3 (ii) a (0 is not included).
The third step: keeping the temperature at 800-880 ℃, keeping the pressure constant at 300mbar, circulating the first step and the second step for 1-3 periods, and sequentially stacking and growing a GaN layer and an InGaN layer for 1-3 periods to obtain a first superlattice layer with the total thickness of 10-20 nm;
the fourth step: after the growth of the first superlattice layer is finished, adjusting the temperature to 850-900 ℃, keeping the constant pressure at 300mbar, and firstly growing a GaN layer with the thickness of 5-10 nm, wherein the GaN layer is an n-type GaN layer doped with si, and the doping concentration of si in the GaN layer is 1-3 multiplied by 10 18 atom/cm 3 ；
The fifth step: constant temperature of 850-900 deg.c, constant pressure of 300mbar, growth of InGaN layer with thickness of 2-5 nm and In doping concentration of 5 x 10 18 ～8×10 19 atom/cm 3 ；
And a sixth step: keeping the temperature at 850-900 ℃ and keeping the pressure constant at 300mbar, circulating the fourth step and the fifth step for 2-5 periods, and sequentially stacking and growing a GaN layer and an InGaN layer for 2-5 periods to obtain a second superlattice layer with the total thickness of 20-40 nm.
Advantageous effects
Compared with the prior art, the novel LED epitaxial stress release layer growth method and the chip prepared by the method have the following beneficial effects:
(1) This technical scheme plays the effect of improving the stacking fault through the setting on first superlattice layer, prevents that the direct growth second superlattice layer from forming that the lattice mismatch is big, leads to the stacking fault to produce the unusual phenomenon of electrical property, can effectively improve crystallization quality, thereby increases interior quantum efficiency and promotes LED luminous efficacy.
(2) In the technical scheme, the In concentration In the first superlattice layer is relatively low, and the V-Pits are relatively low, so that the stacking caused by excessive V-Pits is improved, a V-shaped groove ring is prevented from being formed, the leakage abnormity is reduced, the dislocation is reduced, and the crystallization quality is improved; the second superlattice layer has a higher relative In concentration due to the bedding of the first superlattice layer, and plays a role In opening V-pits, so that the luminous efficiency of the LED is improved.
Drawings
Fig. 1 is a schematic view of the entire structure of embodiment 1.
Fig. 2 is a schematic structural view of the stress relieving layer in example 1.
FIG. 3 is a schematic view of the entire structure of embodiment 2.
Fig. 4 is a schematic structural view of a stress relieving layer in example 2.
Fig. 5 is a schematic view of the overall structure of a comparative example.
Reference numbers in the drawings: the light-emitting diode comprises a 1-substrate, a 2-buffer layer, a 3-u type GaN layer, a 4-n type GaN layer, a 5-stress release layer, a 51-first superlattice layer, a 511-GaN layer with the thickness of 4 nm-8 nm, a 512-InGaN layer with the thickness of 2 nm-4 nm, a 513-GaXN layer, a 52-second superlattice layer, a 521-GaN layer with the thickness of 5 nm-10 nm, a 522-InGaN layer with the thickness of 2 nm-5 nm, a 523-GayN layer, a 6-light-emitting layer and a 7-P type semiconductor layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. Various modifications and improvements of the technical solutions of the present invention may be made by those skilled in the art without departing from the design concept of the present invention, and all of them should fall into the protection scope of the present invention.
Example 1:
an epitaxial structure based on a novel LED epitaxial stress release layer comprises a substrate 1, and a buffer layer 2, a u-shaped GaN layer 3, an n-shaped GaN layer 4 heavily doped with Si, a stress release layer 5, a light emitting layer 6 and a p-shaped GaN layer 7 which are sequentially stacked and grown on the surface of the substrate 1.
The stress release layer 5 includes a first superlattice layer 51 and a second superlattice layer 52 stacked in this order.
The first superlattice layer 51 includes GaN layers and In alternately stacked cyclically X Ga (1-X) N layers, the second superlattice layer 52 including cyclically and alternately stacked GaN layers and In Y Ga (1-Y) N layers; the In doping concentration In the first superlattice layer 51 is smaller than the In doping concentration In the second superlattice layer 52.
The specific structure of the first superlattice layer 51 is: a GaN layer 511 with a thickness of 4 nm-8 nm and disposed on the surface of the N-type GaN layer, wherein the GaN layer is an N-type GaN layer doped with Si with a doping concentration of 1-5 × 10 18 atom/cm 3 (ii) a An InGaN layer 512 having a thickness of 2nm to 4nm and provided on the surface layer of the GaN layer, the InGaN layer having an In doping concentration of 0 to 5X 10 18 atom/cm 3 (ii) a The GaN layer and the InGaN layer were sequentially stacked for 1 to 3 periods to obtain the first superlattice layer 51 having a total thickness of 10 to 20 nm.
The specific structure of the second superlattice layer 52 is: a GaN layer 521 of 5-10 nm thickness formed on the surface of the first superlattice layer 51, wherein the GaN layer is an n-type GaN layer doped with Si and the doping concentration of Si in the GaN layer is 3-5 × 10 18 atom/cm 3 (ii) a An InGaN layer 522 having a thickness of 2nm to 5nm and provided on a surface layer of the GaN layer, the InGaN layer having an In doping concentration of 5 × 10 18 ～8×10 19 atom/cm 3 (ii) a The GaN layer and the InGaN layer are sequentially stacked for 2 to 5 periods to obtain the second superlattice layer 52 having a total thickness of 20 to 40 nm.
The growth temperature of the first superlattice layer 51 is 800-880 ℃, and the growth temperature of the second superlattice layer 52 is 850-900 ℃.
In this embodiment, the buffer layer 2 is a three-dimensional nucleation layer, and the three-dimensional nucleation layer is a plurality of GaN island-shaped structures distributed at intervals on the substrate 1.
The P-type semiconductor layer 7 includes a non-doped P-type GaN layer and/or a P-type GaN layer doped with P-type impurities, which are stacked, and is selected to be a P-type GaN layer doped with Mg in the present embodiment.
Comparative example:
as shown in fig. 5, the comparative example employs the stress relaxation layer 5 having only the first superlattice layer 51 or only the second superlattice layer 52; the structure of the stress relaxation layer 5 in the comparative example includes: and cyclically stacking 3 periods of InGaN layers and GaN layers.
The InGaN layer and the GaN layer grow circularly for 3 periods, the growth temperature is 870-890 ℃, and the pressure is 300mbar. The InGaN layer was grown using TEGa at an in concentration of 6E19atom/cm at 1300sccm 3 (ii) a The GaN layer is grown by adopting TMGa, the input amount is 450sccm, the si doping concentration is 1E18atom/cm 3 (ii) a InGaN/GaN for 3 periods to obtain a stress relief layer with a total thickness of 50-60 nm.
The inventors tested the new LED chip structure obtained in example 1 and the original LED chip structure obtained by using the comparative example. The new LED chip and the original LED chip are selected to be of the same type,the same area is 45.12The LED chip of (1) was tested.
In the test, the model number of the test equipment produced by Shenzhen silicon single semiconductor manufacturer is L-906H Is/are as followsFull-automatic Probe stationThe equipment was tested and the results are shown in table 1:
Figure 743679DEST_PATH_IMAGE002
TABLE 1
The data from table 1 lead to the conclusion: by the first embodiment, the period of the obtained superlattice is increased from 1 to 3, the brightness gradually rises, and the voltage is in a stable state; the superlattice periods 2 to 5 may have a voltage drop tendency. Compared with the total thickness of a comparative example of 55nm, the new LED chip superlattice two keeps 5 periods, the period of the superlattice is increased by 1-3, and the brightness of the LED chip is respectively improved by +0.78%, +0.9%, +1.26%; the voltage of the new LED chip is respectively increased by 0.007,0.005,0.002 compared with the voltage of the original LED chip; obtaining: compared with the original LED chip, the overall brightness of the new LED chip is improved by 0.7% -1.2%, and the voltage is equivalent. The new stress relief layer structure obtained in example 1 has certain advantages over the original stress relief layer structure.
Example 2:
the stress release layer 5 includes a first superlattice layer 51 and a second superlattice layer 52 which are cyclically stacked. The first superlattice layer 51 comprises a GaXN layer 513 with the thickness of 2 nm-5 nm, which is arranged on the surface layer of the N-type GaN layer 4, and the GaXN layer 513 is grown by TEGa; the second superlattice layer 52 comprises a GayN layer 523 with the thickness of 5 nm-8 nm, which is arranged on the surface layer of the GaXN layer 513, and the GayN layer 523 grows by adopting TMGa; and (first superlattice layer) GaXN layer 513 and (second superlattice layer) GayN layer 523 are sequentially and circularly stacked and grown for 2-5 periods, so that the stress release layer 5 with the total thickness of 30-60 nm is obtained.
Other structures and the positional relationship and the connection relationship between the structures in this embodiment are the same as those in embodiment 1, and a repetitive description will not be made here.
The comparative example of this example is the same as that of example 1, and will not be described in more detail here.
The inventors tested the new LED chip structure obtained in example 1 and the original LED chip structure obtained using the comparative example. The new LED chip and the original LED chip are selected to be of the same type,the same area is 45.12The LED chip of (1) was tested.
In the test, the model number of the test equipment produced by Shenzhen silicon single semiconductor manufacturer is L-906H Is/are as followsFull-automatic Probe stationThe equipment was tested and the results are shown in table 2:
Figure 723137DEST_PATH_IMAGE004
TABLE 2
The data from table 2 lead to the conclusion: the GaXN layer and the GayN layer in example 2 were adjusted to integers and tested to obtain: and adjusting the cycle number, wherein the brightness gradually rises and the voltage gradually falls as the cycle number increases to 4, and the data change is less obvious than that of 4 cycles when 5 cycles are reached. Compared with the total thickness of the comparative example of 55nm, the brightness of the new LED chip obtained by the embodiment 2 by finding the number of the cycles and increasing the number by 2-4 is respectively improved by-0.1%, +0.63%, +1.1%; compared with the voltage of the original LED chip, the voltage of the new LED chip obtained in the embodiment 2 is respectively increased by 0.016,0.02 and minus 0.002; obtaining: compared with the original LED chip, the overall brightness of the new LED chip obtained in the embodiment 2 is improved by-0.1% -1.1%, and the voltage is improved by 0.016 to-0.002V. Therefore, the new stress relief layer structure obtained in example 2 has a certain number of cycles 3 to 5, which is advantageous over the original stress relief layer structure.
Example 3:
a method for growing an LED epitaxial novel stress relief layer, which is used to fabricate the LED epitaxial novel stress relief layer-based epitaxial structure of embodiment 1, and includes: providing a substrate 1, and sequentially growing a buffer layer 2, a u-type GaN layer 3, a heavily-doped Si n-type GaN layer 4, a stress release layer 5, a light-emitting layer 6 and a p-type GaN layer on the surface of the substrate 1; the specific operation steps of the epitaxial structure are as follows:
step 1: providing a substrate 1, wherein the substrate 1 is a PSS substrate, and an AlN layer is deposited on a PSS pattern: treating for 2-5 min under the conditions that the temperature is 1000-1200 ℃, the pressure of a reaction cavity is 100-300 mbar and 75-150L/min H2 is introduced.
And 2, step: and (3) growing a buffer layer 2: putting a substrate 1 into a reaction cavity, introducing a Ga source and an N source into the reaction cavity, growing a GaN crystal grain thin layer on the surface layer of the substrate, closing the Ga source and the N source for 5-60 s, raising the temperature in the reaction cavity to 500-850 ℃, keeping the pressure in the reaction cavity at 200-500 mbar, and introducing NH of 15000-30000 sccm 3 And H of 150 to 200L/min 2 Under the condition of; and obtaining a grown three-dimensional nucleation layer on the substrate, wherein the three-dimensional nucleation layer is a plurality of GaN island-shaped structures distributed on the substrate at intervals.
And step 3: growing a u-type GaN layer 3 on the surface layer of the three-dimensional nucleation layer: introducing NH of 45000-60000 sccm at the temperature of 1000-1200 ℃ and the pressure of the reaction cavity of 300-600 mbar 3 The input flow of TMGa is 200-700sccm, and the input flow of H is 150-200L/min 2 Growing an undoped N-type GaN layer under the condition;
and 4, step 4: growing an n-type GaN layer 4 on the surface layer of the u-type GaN layer 3: growing an N-type GaN layer doped with Si, maintaining the pressure, temperature and H of step 3 2 Under the condition of introducing 45000-70000 sccm NH 3 The flow rate of TMGa is 800-1200sccm 4 The flow rate of the silicon is 30-80sccm, the doping concentration of Si is 1 multiplied by 10 19 ～1×10 20 atom/cm 3 。
And 5: growing a stress release layer 5 on the surface layer of the n-type GaN layer 4, wherein the growth method of the stress release layer 5 comprises the following steps: sequentially growing a first superlattice layer 51 and a second superlattice layer 52; the first superlattice layer 51 includes alternately grown GaN layers and In layers periodically X Ga (1-X) N layer, X is more than or equal to 0 and less than 0.15; the second superlattice layer 52 includes GaN layers and In alternately grown periodically Y Ga (1-Y) N layer, Y is more than or equal to 0 and less than 0.25; when both X and Y are greater than 0, the growth method of the stress release layer comprises the following steps:
the first step is as follows: after the growth of the n-type GaN layer 4 is finished, the temperature is adjusted to 800-880 ℃, the pressure is 300mbar, a GaN layer 511 with the thickness of 4 nm-8 nm is grown firstly, the GaN layer is an n-type GaN layer doped with Si, and the doping concentration of Si in the GaN layer is 1-5 multiplied by 10 18 atom/cm 3 ；
The second step: constant temperature 800-880 deg.C, constant pressure 300mbar, growth of InGaN layer 512 with thickness of 2-4 nm, in doping concentration of 0-5 × 10 18 atom/cm 3 ；
The third step: keeping the temperature at 800-880 ℃, keeping the pressure constant at 300mbar, circulating the first step and the second step for 1-3 periods, and sequentially stacking and growing a GaN layer and an InGaN layer for 1-3 periods to obtain a first superlattice layer 51 with the total thickness of 10-20 nm;
the fourth step: after the first superlattice layer 51 is grown, the temperature is adjusted to 850-900 ℃ and the constant pressure is 300mbarA GaN layer 521 with a length of 5-10 nm, the GaN layer being an n-type GaN layer doped with Si with a doping concentration of 3-5 × 10 18 atom/cm 3 ；
The fifth step: growing an InGaN layer 522 with the thickness of 2nm to 5nm at the constant temperature of 850-900 ℃ and the constant pressure of 300mbar, wherein the doping concentration of In the InGaN layer is 5 multiplied by 10 18 ～8×10 19 atom/cm 3 ；
And a sixth step: keeping the temperature at 850-900 ℃ and keeping the pressure constant at 300mbar, circulating the fourth step and the fifth step for 2-5 periods, and sequentially stacking and growing a GaN layer and an InGaN layer for 2-5 periods to obtain a second superlattice layer 52 with the total thickness of 20-40 nm.
Step 6: growing a light emitting layer 6 which is an InGaN/GaN layer grown by superlattice, wherein the InGaN/GaN layer grows cyclically for 8-12 periods; the growth method of the luminescent layer comprises the following steps:
A. growing an InGaN potential well layer, controlling the pressure of a reaction cavity at 200-300 mbar, controlling the temperature at 750-800 ℃, introducing NH3 with the flow rate of 65000-75000 sccm, introducing TEGa with the flow rate of 400-800sccm, and introducing N2 with the flow rate of 50000-70000 sccm;
B. growing a GaN barrier layer, wherein the temperature is 850-900 ℃, the N2 flow rate is 30000-50000 sccm, the H2 flow rate is 10000-30000sccm, the TEGa introduction flow rate is 800-1200 sccm, and the SiH4 introduction flow rate is 5-20 sccm;
C. and circulating the steps of A and B for 8-12 times to grow InGaN/GaN layers with 8-12 periods.
And 7: growth of a P-type semiconductor layer 7 (Mg-doped P-type GaN layer): growing under the conditions that the temperature is 950-1000 ℃, the pressure of a reaction cavity is 200-500 mbar, NH3 of 50000-70000 sccm, TEGa of 1500-2500 sccm and CP2 Mg of 1000-2000 sccm are introduced; wherein the Mg doping concentration is 1 x 1019atom/cm 3-1 x 1020atom/cm 3.
And 8: and cooling to obtain the LED epitaxial structure.
Example 4:
a growth method of a novel LED epitaxial stress release layer is used for manufacturing an epitaxial structure based on the novel LED epitaxial stress release layer in embodiment 2, and the stress release layer 5 comprises the following steps: growing stress relief on the surface layer of the n-type GaN layer 4The growth method of the stress release layer 5 is as follows: cyclically growing a first superlattice layer 51 and a second superlattice layer 52; the first superlattice layer 51 includes periodically and alternately grown GaN layers and In X Ga (1-X) N layer, X is more than or equal to 0 and less than 0.8; the second superlattice layer 52 includes GaN layers and In alternately grown periodically Y Ga (1-Y) N layers, wherein Y is more than or equal to 0 and less than 1; when both X and Y are equal to 0, the growth method of the stress release layer 5 is as follows:
the first step is as follows: after the growth of the n-type GaN layer 4 is finished, adjusting the temperature to 800-900 ℃, the pressure to 300mbar, growing a GaXN layer 513 with the thickness of 2 nm-5 nm, and growing the GaXN layer 513 by using TEGa;
the second step is that: maintaining the original temperature and pressure, growing a GayN layer 523 with the thickness of 5 nm-8 nm, and growing the GayN layer 523 by adopting TMGa;
the third step: maintaining the original temperature and pressure, circulating the first step and the second step for 2-5 periods, and sequentially stacking and growing GaXN layers 513 and GayN layers 523 for 2-5 periods to obtain the stress release layer 5 with the total thickness of 20-40 nm.
Other steps and operation manners in this embodiment are the same as those in embodiment 3, and will not be described in detail herein.

Claims (10)

1. An epitaxial structure based on a novel LED epitaxial stress release layer comprises a substrate (1), and a buffer layer (2), a u-shaped GaN layer (3), an N-shaped GaN layer (4), a stress release layer (5), a light emitting layer (6) and a P-shaped semiconductor layer (7) which are sequentially stacked on the surface of the substrate (1); the method is characterized in that: the stress release layer (5) comprises a first superlattice layer (51) and a second superlattice layer (52) which are sequentially/circularly laminated; the first superlattice layer (51) comprises GaN layers and In which are cyclically and alternately stacked X Ga (1-X) N layers, the second superlattice layer (52) including cyclically and alternately stacked GaN layers and In layers Y Ga (1-Y) N layers; the In doping concentration In the first superlattice layer (51) is less than/equal to the In doping concentration In the second superlattice layer (52).
2. Root of herbaceous plantThe epitaxial structure based on the epitaxial new stress relief layer of the LED as claimed in claim 1, wherein: when the In doping concentration In the first superlattice layer (51) is less than that In the second superlattice layer (52), the stress release layer (5) comprises the first superlattice layer (51) and the second superlattice layer (52) which are sequentially stacked; the In doping concentration In the first superlattice layer (51) is 0-5 × 10 18 atom/cm 3 (ii) a The second superlattice layer (52) has an In doping concentration of 5 × 10 18 ～2×10 20 atom/cm 3 。
3. The epitaxial structure of claim 2, wherein the epitaxial structure comprises a novel stress relief layer formed on the surface of the LED, and the stress relief layer comprises: in the first superlattice layer (51) X Ga (1-X) The N layer and the GaN layer are cyclically laminated for 1-3 periods, the thickness of each GaN layer In the first superlattice layer (51) is 4-8 nm, and each In layer X Ga (1-X) The thickness of the N layer is 2 nm-4 nm, and a first superlattice layer (51) with the total thickness of 10-20 nm is obtained; in the second superlattice layer (52) Y Ga (1-Y) The N layer and the GaN layer are cyclically laminated for 2-5 periods, the thickness of each GaN layer In the second superlattice layer (52) is 5-10 nm, and each In layer Y Ga (1-Y) The thickness of the N layer is 2nm to 5nm, and a second superlattice layer (52) with the total thickness of 20nm to 40nm is obtained.
4. The epitaxial structure of claim 3, wherein the epitaxial structure comprises a novel stress relief layer formed on the surface of the LED, and the stress relief layer comprises: the GaN layer in the first superlattice layer (51) has a doping concentration of si of 1 to 5 x 10 during growth 18 atom/cm 3 (ii) a The GaN layer in the second superlattice layer (52) has a doping concentration of si of 3 to 5 × 10 during growth 18 atom/cm 3 。
5. The epitaxial structure based on the LED epitaxial novel stress release layer as claimed in claim 1, wherein: when the In doping concentration In the first superlattice layer (51) is equal to the In doping concentration In the second superlattice layer (52), the In doping concentrations In the first superlattice layer (51) and the second superlattice layer (52) are both 0; the stress release layer (5) comprises a first superlattice layer (51) and a second superlattice layer (52) which are circularly stacked, the first superlattice layer (51) is a GaXN layer (513), and the GaXN layer (513) is grown by adopting TEGa; the second superlattice layer (52) is a GayN layer (523), and the GayN layer (52) is grown by adopting TMGa.
6. The epitaxial structure based on the LED epitaxial novel stress release layer as claimed in claim 1, wherein: the buffer layer (2) is a three-dimensional nucleation layer which is a plurality of GaN island-shaped structures distributed on the substrate at intervals.
7. The epitaxial structure based on the LED epitaxial novel stress release layer as claimed in claim 1, wherein: the P-type semiconductor layer (7) comprises an undoped P-type GaN layer and/or a P-type GaN layer doped with P-type impurities which are stacked.
8. A growth method of an LED epitaxial novel stress release layer is used for manufacturing an epitaxial structure based on the LED epitaxial novel stress release layer, and the method comprises the steps of providing a substrate (1), and sequentially growing a buffer layer (2), a u-type GaN layer (3), an n-type GaN layer (4), a stress release layer (5), a light-emitting layer (6) and a p-type GaN layer (7) on the surface of the substrate (1); the method is characterized in that: the growth method of the stress release layer (5) comprises the following steps: sequentially/cyclically growing a first superlattice layer (51) and a second superlattice layer (52); the first superlattice layer (51) comprises GaN layers and In which are periodically and alternately grown X Ga (1-X) N layer, X is more than or equal to 0 and less than 0.15; the second superlattice layer (52) comprises GaN layers and In which are periodically and alternately grown Y Ga (1-Y) N layer, Y is more than or equal to 0 and less than 0.25.
9. The method for growing the epitaxial novel stress relief layer of the LED as claimed in claim 8, wherein: when X and Y are both equal to 0, the growth method of the stress release layer (5) comprises the following steps:
the first step is as follows: after the growth of the n-type GaN layer (4) is finished, adjusting the temperature to 800-900 ℃, the pressure to 300mbar, and growing a GaXN layer (513) with the thickness of 2 nm-5 nm, wherein the GaXN layer (513) grows by adopting TEGa;
the second step is that: maintaining the original temperature and pressure, growing a GayN layer (523) with the thickness of 5 nm-8 nm, wherein the GayN layer (523) grows by adopting TMGa;
the third step: maintaining the original temperature and pressure, circulating the first step and the second step for 2-5 periods, and sequentially stacking and growing a GaXN layer (513) and a GayN layer (523) for 2-5 periods to obtain the stress release layer (5) with the total thickness of 30-60 nm.
10. The method for growing the epitaxial novel stress release layer of the LED according to claim 8, wherein the method comprises the following steps: when both X and Y are more than 0, the growth method of the stress release layer (5) is as follows:
the first step is as follows: after the growth of the n-type GaN layer (4) is finished, the temperature is adjusted to 800-880 ℃, the pressure is 300mbar, a GaN layer (511) with the thickness of 4 nm-8 nm is grown first, the GaN layer is an n-type GaN layer doped with si, and the doping concentration of si in the GaN layer is 1-5 multiplied by 10 18 atom/cm 3 ；
The second step is that: growing an InGaN layer (512) with a thickness of 2nm to 4nm at a constant temperature of 800 to 880 ℃, a constant pressure of 300mbar, wherein the doping concentration of In the InGaN layer is 0 to 5 multiplied by 10 18 atom/cm 3 ；
The third step: keeping the temperature at 800-880 ℃, keeping the pressure constant at 300mbar, circulating the first step and the second step for 1-3 periods, and sequentially stacking and growing a GaN layer and an InGaN layer for 1-3 periods to obtain a first superlattice layer (51) with the total thickness of 10-20 nm;
the fourth step: after the growth of the first superlattice layer is finished, adjusting the temperature to 850-900 ℃, keeping the constant pressure at 300mbar, and firstly growing a GaN layer (521) with the thickness of 5-10 nm, wherein the GaN layer is an n-type GaN layer doped with si, and the doping concentration of si in the GaN layer is 3-5 multiplied by 10 18 atom/cm 3 ；
Fifth aspect of the inventionThe method comprises the following steps: growing an InGaN layer (522) with a constant temperature of 850-900 deg.C and a constant pressure of 300mbar and a thickness of 2-5 nm, wherein the doping concentration of In the InGaN layer is 5 × 10 18 ～2×10 20 atom/cm 3 ；
And a sixth step: and (3) keeping the temperature at 850-900 ℃ and keeping the pressure constant at 300mbar, circulating the fourth step and the fifth step for 2-5 periods, and sequentially stacking and growing a GaN layer and an InGaN layer for 2-5 periods to obtain a second superlattice layer (52) with the total thickness of 20-40 nm.
CN202210953377.3A 2022-08-10 2022-08-10 Growth method of novel LED epitaxial stress release layer and chip prepared by method Pending CN115347087A (en)

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CN104362233A (en) * 2014-10-29 2015-02-18 华灿光电(苏州）有限公司 Epitaxial slice of GaN-based light emitting diode (LED) and preparation method thereof
CN106328777A (en) * 2016-09-08 2017-01-11 湘能华磊光电股份有限公司 Light emitting diode stress release layer epitaxial growth method
CN113161451A (en) * 2021-04-20 2021-07-23 湘能华磊光电股份有限公司 LED epitaxial structure and growth method thereof
CN113451458A (en) * 2020-05-22 2021-09-28 重庆康佳光电技术研究院有限公司 Superlattice layer, LED epitaxial structure, display device and manufacturing method thereof

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CN103985797A (en) * 2014-05-05 2014-08-13 湘能华磊光电股份有限公司 Multi-quantum-well structure, growing method and LED chip with structure
CN104362233A (en) * 2014-10-29 2015-02-18 华灿光电(苏州）有限公司 Epitaxial slice of GaN-based light emitting diode (LED) and preparation method thereof
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