CN115333484B

CN115333484B - Multiple frequency sweeping method

Info

Publication number: CN115333484B
Application number: CN202211007299.4A
Authority: CN
Inventors: 谢丹
Original assignee: Chengdu Sicore Semiconductor Corp Ltd
Current assignee: Chengdu Sicore Semiconductor Corp Ltd
Priority date: 2022-08-22
Filing date: 2022-08-22
Publication date: 2023-08-22
Anticipated expiration: 2042-08-22
Also published as: CN115333484A

Abstract

The invention discloses a frequency multiplication frequency sweeping method, which relates to the field of frequency modulation and is applied to a frequency sweeping device, wherein the frequency sweeping device comprises: the device comprises a sweep frequency module, a decimal modulator module, a frequency divider and a phase-locked loop; the clocks of the sweep frequency module and the decimal modulator module are respectively controlled by a phase discrimination clock and a frequency division clock of the phase-locked loop, the phase-locked loop outputs a locking indication signal to the sweep frequency module, the integer frequency division ratio and the decimal frequency division ratio output by the sweep frequency module are used as the input of the decimal modulator module, and the decimal modulator module outputs the frequency division ratio to the phase-locked loop; the method comprises the following steps: the method comprises the steps that an initial frequency dividing ratio and a final frequency dividing ratio are obtained based on a control signal and input into a frequency sweep module, and the frequency sweep module outputs the frequency dividing ratio to a frequency dividing ratio switching signal of a frequency divider control frequency divider; setting a plurality of working states of the frequency sweeping device; the frequency sweep device is controlled to switch in a plurality of working states, so that the frequency divider outputs multi-octave frequency sweep signals.

Description

Multiple frequency sweeping method

Technical Field

The invention relates to the field of frequency modulation, in particular to a frequency multiplication frequency sweeping method.

Background

The Frequency Modulation Continuous Wave (FMCW) is widely applied to the fields of modern radars, unmanned aerial vehicles, automobile autopilots and the like, has the advantages of high resolution, high sensitivity and more measurable information compared with Doppler radars, realizes the Frequency sweeping function through a digital circuit by continuously controlling the Frequency division ratio of a delta-sigma decimal modulator, and can improve the performance compared with a mode of controlling a PLL (phase locked loop) by DDS (direct digital Frequency synthesis). The common PLL directly outputs through a VCO (voltage controlled oscillator) and feeds back to a feedback frequency divider, so that the frequency sweep range that can be achieved is one octave, but in practical engineering application, the VCO may be further connected to an output frequency divider, which implements power division of 2 (such as a division ratio of 1/2/4/8 … …, etc.), in this case, the frequency sweep output of multiple octaves needs to be provided, so as to expand the frequency sweep range, but how to implement multiple frequency sweep modes through a digital circuit becomes a problem that is generally focused at present, however, the prior art lacks a multiple frequency sweep method and a digital circuit thereof that are applied in combination with the frequency divider, and related reports are not seen.

Disclosure of Invention

The invention aims to provide a multi-octave sweep frequency output.

In order to achieve the above object, the present invention provides a multiple frequency sweep method, which is applied to a sweep apparatus, the sweep apparatus includes: the device comprises a sweep frequency module, a delta-sigma decimal modulator module, a frequency divider and a phase-locked loop; the clocks of the sweep frequency module and the delta-sigma decimal modulator module are respectively controlled by a phase discrimination clock and a frequency division clock of the phase-locked loop, a locking indication signal LDT output by the phase-locked loop is connected with the input of the sweep frequency module, the integer frequency division ratio and the decimal frequency division ratio output by the sweep frequency module are used as the input of the delta-sigma decimal modulator module, and the delta-sigma decimal modulator module outputs the frequency division ratio to the phase-locked loop;

the method comprises the following steps:

the method comprises the steps that an initial frequency dividing ratio and a final frequency dividing ratio are obtained based on a control signal and input into a frequency sweep module, and the frequency sweep module outputs the frequency dividing ratio to a frequency dividing ratio switching signal of a frequency divider control frequency divider;

setting a plurality of working states of the frequency sweeping device;

the frequency sweep device is controlled to switch in a plurality of working states, so that the frequency divider outputs a multi-octave frequency sweep signal.

The working frequency of the sweep frequency module is controlled by the phase discrimination frequency fref of the phase-locked loop, and in the locked state, the working frequency of the sweep frequency module and the working frequency of the delta-sigma decimal modulator are ensured to be the same and have fixed phase difference (namely, in the phase-locked state, the same frequency and fixed phase difference of two clocks are input). In the circuit, the clock clk_ swp represented as a sweep module is connected with the phase discrimination clock clk_ref of the phase-locked loop, and for convenience of explanation, the invention provides that the values of the integer frequency division ratio nint and the fractional frequency division ratio nfrac of the sweep output are updated in response to the rising edge of the sweep clock clk_ swp, that is, when the rising edge of clk_ swp comes. The initial frequency dividing ratio odiv_str and the final frequency dividing ratio odiv_ trm of the external control signals are input to the frequency sweep module to be used as octave control for indicating a frequency multiplication algorithm of the frequency sweep module, and after algorithm processing, the frequency sweep module outputs a control word odiv_cal to a power frequency divider of 2 to be used as a frequency dividing ratio switching signal for controlling the power frequency divider of 2. The power frequency divider of 2 outputs a multi-octave sweep frequency signal to the outside.

The frequency sweep module realizes continuous change from high frequency to low frequency (or from low frequency to high frequency); the decimal modulation module realizes the decimal frequency division function, and the phase-locked loop realizes that the frequency of the output signal reflects the frequency of the input signal in proportion; the frequency divider implements frequency division of the output frequency.

Preferably, the frequency sweep device includes 8 operating conditions, respectively: an initialization and locking judgment state S1, a sweep frequency mode judgment state S2, an uplink sweep frequency state S3, a downlink sweep frequency state S4, an initial unlocking processing state S5, an uplink unlocking processing state S6, a downlink unlocking processing state S7 and a termination state S8;

starting the sweep frequency to start to enter a state S1, after completing configuration of initialization parameters in the state S1, performing phase-locked loop locking judgment, and switching to a state S5 if the phase-locked loop is out of lock;

switching back to the state S1 after waiting for the phase-locked loop to be locked again in the state S5, and switching to the state S2 if the phase-locked loop is locked in the state S1;

in the state S2, the sweep frequency mode judgment is carried out, then the sweep frequency direction judgment is carried out, if the sweep frequency is the uplink sweep frequency, the state S2 is switched to the state S3, if the sweep frequency is the downlink sweep frequency, the state S2 is switched to the state S4, and the pointer of the frequency division ratio jump is set;

Performing uplink sweep frequency control in a state S3, switching to a state S8 if the sweep frequency reaches a termination frequency division ratio and the phase-locked loop is locked, and switching to a state S6 if the phase-locked loop is unlocked; in the state S6, performing phase-locked loop locking judgment in the uplink process, and switching back to the state S3 if the phase-locked loop is locked;

in the state S4, downlink sweep frequency control is carried out, if the sweep frequency returns to the initial frequency division ratio and the phase-locked loop is locked, the state is switched to the state S8, and if the phase-locked loop is unlocked, the state is switched to the state S7;

in the state S8, the next section of sweep frequency state is determined according to the sweep frequency mode, if the sweep frequency is continuous, the state is switched to the state S2, and if the sweep frequency is triggered, the state is switched to the state S1.

Preferably, the frequency sweep signal comprises a plurality of frequency sweep signal sections which are sequentially connected, the frequency sweep direction of each frequency sweep signal section is any one of uplink frequency sweep, downlink frequency sweep and parallel frequency sweep, and each frequency sweep signal section corresponds to the corresponding frequency sweep time length respectively.

Preferably, the method further comprises marking the initial integer frequency division ratio and the initial fractional frequency division ratio of each sweep signal segment to obtain marking information, and configuring the condition information to be met according to the sweep signal.

The frequency sweep signal is an upper sawtooth wave type frequency sweep signal, or the frequency sweep signal is a lower sawtooth wave type frequency sweep signal, or the frequency sweep signal is a triangular wave type frequency sweep signal, or the frequency sweep signal is a trapezoidal wave type frequency sweep signal.

Namely, the device can realize the sweep frequency of any waveform, and the specific implementation mode is as follows:

in order to realize the upper sawtooth wave type sweep frequency signal, the upper sawtooth wave can be characterized as an uplink sweep frequency band, and the method is correspondingly designed, particularly when the sweep frequency signal is the upper sawtooth wave type sweep frequency signal, the method further comprises the following steps before sweep frequency:

configuring nint_ramp0, nfrac_ramp0, step_ramp0, nint_ramp1 and nfrac_ramp1, wherein the configuration satisfies at least one of the following two conditions:

condition 1: nint_ramp0 < nint_ramp1;

condition 2: nint_ramp0 = nint_ramp1 and nfrac_ramp0 < nfrac_ramp1;

the initial integer frequency division ratio of the first section of frequency sweeping signal section is marked as nint_ramp0, the initial fractional frequency division ratio of the first section of frequency sweeping signal section is marked as nfrac_ramp0, and the frequency sweeping step of the first section of frequency sweeping signal section is marked as step_ramp0; the initial integer frequency division ratio of the second section of sweep frequency signal section is marked as nint_ramp1, the initial fractional frequency division ratio of the second section of sweep frequency signal section is marked as nfracramp 1, and the sweep frequency step of the second section of sweep frequency signal section is marked as step_ramp1.

In order to realize the lower sawtooth wave type sweep frequency signal, the lower sawtooth wave can be characterized as a section of downlink sweep frequency band, the method is correspondingly designed, and particularly when the sweep frequency signal is the lower sawtooth wave type sweep frequency signal, the method further comprises the following steps before sweep frequency:

condition 3: nint_ramp0 > nint_ramp1;

condition 4: nint_ramp 0=nint_ramp 1 and nfracjramp 0 > nfracjramp 1;

In order to realize the triangular wave type frequency sweep signal, the triangular wave can be characterized in that an uplink frequency sweep section is connected with a downlink frequency sweep section, the method is correspondingly designed, and particularly when the frequency sweep signal is the triangular wave type frequency sweep signal, the method further comprises the following steps before frequency sweep:

Configuring nint_ramp0, nfrac_ramp0, step_ramp0, nint_ramp1, nfrac_ramp1, step_ramp1, nint_ramp2 and nfrac_ramp2, and configuring to satisfy at least one of the following four conditions:

condition 5: nint_ramp0 < nint_ramp1 and nint_ramp1 > nint_ramp2;

condition 6: nint_ramp0 = nint_ramp1 and nfracjramp 0 < nfracjramp 1 and nint_ramp1 > nint_ramp2;

condition 7: nint_ramp0 < nint_ramp1 and nint_ramp 1=nint_ramp 2 and nfrac_ramp1 > nfrac_ramp2;

condition 8: nint_rap0=nint_rap1 and nfracjrap0 < nfracjrap1 and nint_rap1=nint_rap2 and nfracjrap1 > nfracjrap2;

the initial integer frequency division ratio of the first section of frequency sweeping signal section is marked as nint_ramp0, the initial fractional frequency division ratio of the first section of frequency sweeping signal section is marked as nfrac_ramp0, and the frequency sweeping step of the first section of frequency sweeping signal section is marked as step_ramp0; the starting integer frequency division ratio of the second section of frequency sweep signal section is marked as nint_ramp1, the starting fractional frequency division ratio of the second section of frequency sweep signal section is marked as nfrac_ramp1, the frequency sweep step of the second section of frequency sweep signal section is marked as step_ramp1, the starting integer frequency division of the third section of frequency sweep signal section is marked as nint_ramp2, the starting fractional frequency division ratio of the third section of frequency sweep signal section is marked as nfrac_ramp2, and the frequency sweep step of the third section of frequency sweep signal section is marked as step_ramp2.

In order to realize the trapezoidal wave type frequency sweep signal, the trapezoidal wave can be characterized in that an uplink frequency sweep section is connected with a parallel frequency sweep section and then is connected with a downlink frequency sweep section, and the method is correspondingly designed, specifically, when the frequency sweep signal is the trapezoidal wave type frequency sweep signal, the method further comprises the following steps before frequency sweep:

configuring nint_ramp0, nfrac_ramp0, step_ramp0, nint_ramp1, nfrac_ramp1, step_ramp1, nint_ramp2, nfrac_ramp2, step_ramp2, nint_ramp3 and nfrac_ramp3, and configuring to satisfy at least one of the following four conditions:

condition 9: nint_ramp0 < nint_ramp1 and nint_ramp2 > nint_ramp3 and nint_ramp 1=nint_ramp 2 and nfracjramp 1=nfracjramp 2;

condition 10: nint_ram 0 = nint_ram 1 and nfracram 0 < nfracram 1 and nint_ram 2 > nint_ram 3 and nint_ram 1 = nint_ram 2 and nfracram_ram 1 = nfracram 2;

condition 11: nint_ram 0 < nint_ram 1 and nint_ram 2 = nint_ram 3 and nfrac_ram 2 > nfrac_ram 3 and nint_ram 1 = nint_ram 2 and nfrac_ram 1 = nfrac_ram 2;

condition 12: nint_ramp0=nint_ramp1 and nfracjramp0 < nfracjramp1 and nint_ramp2=nint_ramp3 and nfracjramp2 > nfracjramp3 and nintjramp1=nint_ramp2 and nfracjramp1=nfracjramp2;

The initial integer frequency division ratio of the first section of frequency sweeping signal section is marked as nint_ramp0, the initial fractional frequency division ratio of the first section of frequency sweeping signal section is marked as nfrac_ramp0, and the frequency sweeping step of the first section of frequency sweeping signal section is marked as step_ramp0; the starting integer frequency division ratio of the second section of the frequency sweep signal section is marked as nint_ramp1, the starting fractional frequency division ratio of the second section of the frequency sweep signal section is marked as nfrac_ramp1, the frequency sweep step of the second section of the frequency sweep signal section is marked as step_ramp1, the starting integer frequency division of the third section of the frequency sweep signal section is marked as nint_ramp2, the starting fractional frequency division ratio of the third section of the frequency sweep signal section is marked as nfrac_ramp2, the frequency sweep step of the third section of the frequency sweep signal section is marked as step_ramp2, the starting integer frequency division ratio of the fourth section of the frequency sweep signal section is marked as nint_ramp3, the starting fractional frequency division ratio of the fourth section of the frequency sweep signal section is marked as nfrac_ramp3, and the step of the fourth section of the frequency sweep signal section is marked as step_ramp3.

Preferably, in the state S1, the following steps are included:

processing the input initial integer frequency division ratio nint_str, initial fractional frequency division ratio nfrac_str and initial frequency division ratio odiv_str to obtain an extended initial integer frequency division ratio nint_str_expansion and an extended initial fractional frequency division ratio nfrac_str_expansion;

Processing the input termination integer division ratio nint_ trm, termination fractional division ratio nfrac_ trm and termination division ratio odiv_ trm to obtain a termination integer division ratio nint_ trm _expansion and an extended termination fractional division ratio nfrac_ trm _expansion;

the state of the current phase-locked loop is judged through a locking indication signal LDT output by the phase-locked loop, if the phase-locked loop is in a locked state, the phase-locked loop enters a state S2, if the phase-locked loop is in an unlocked state, the phase-locked loop is switched from the state S1 to the state S5, a re-locking process is entered, and after locking is completed, the phase-locked loop returns to the state S1 and is switched to the state S2.

Preferably, in the state S2, the following steps are included:

judging a set frequency sweep mode, wherein the frequency sweep mode comprises continuous bidirectional frequency sweep, trigger type bidirectional frequency sweep and trigger type unidirectional frequency sweep, the continuous bidirectional frequency sweep is formed by alternately carrying out uplink frequency sweep and downlink frequency sweep, the trigger type bidirectional frequency sweep is formed by alternately starting the uplink frequency sweep and the downlink frequency sweep through an external trigger signal, and the trigger type unidirectional frequency sweep is formed by controlling the starting of the uplink frequency sweep through the external trigger signal, and the starting frequency point is returned after the end of the uplink frequency sweep;

setting the change condition of the frequency division ratio of the frequency divider odiv in the frequency sweeping process;

For continuous bidirectional frequency sweep and trigger bidirectional frequency sweep, when uplink frequency sweep is adopted, switching from state S2 to state S3, and when downlink frequency sweep is adopted, switching from state S2 to state S4; for triggered unidirectional sweep, switch from state S2 to state S3.

Preferably, in the state S3, the following steps are included:

the ascending sweep is realized by accumulating the temporary register nfrac_tmp in step to obtain the increment of the frequency division ratio of the sweep module, and the values of the temporary register nint_tmp and the temporary register nfrac_tmp are updated once every time the rising edge of the clk_ swp clock comes once;

judging whether to switch the state or not through a locking indication signal LDT output by the phase-locked loop, switching from the state S3 to the state S6 when the phase-locked loop is out of lock, and continuously maintaining the state S3 if the phase-locked loop is still locked;

a decision is made as to whether or not the temporary register nint_tmp and temporary register nfrac_tmp have reached the ending integer division ratio and ending fractional division ratio, and if so, the state is switched from state S3 to state S8, and if not, the state S3 is continued to be maintained.

Preferably, in the state S4, the following steps are included:

a gradual decrease of the frequency division ratio of the sweep module is obtained by decrementing the temporary register nfrac_tmp by a step to realize the downstream sweep, once every time the rising edge of the clk_ swp clock, the values of nint_tmp and nfrac_tmp are updated once;

Judging whether to perform state switching or not through a locking indication signal LDT output by the phase-locked loop, switching from a state S4 to a state S7 when the phase-locked loop is out of lock, and continuously maintaining the state S4 if the phase-locked loop is still locked;

a decision is made as to whether the temporary register nint_tmp and temporary register nfrac_tmp have reached the starting integer division ratio and the starting fractional division ratio of the first segment, if so, a switch is made from state S4 to state S8, and if so, state S4 is continued to be maintained.

Preferably, in state S6, the following steps are included:

when the pointer odiv_up=1, the values of the temporary registers nint_tmp and nfrac_tmp are divided by 2, respectively;

the timer is timed from 0 by externally configuring the duration of the timer, and the state S6 is switched back to the state S3 after the timer is full;

the state S7 includes the following steps:

when the pointer odiv_dw=1, the values of the temporary registers nint_tmp and nfrac_tmp are divided by 2, respectively;

by externally configuring the duration of the timer, the timer is timed from 0, and after expiration, the state is switched back to the state S4 from the state S7.

Preferably, the sweep signal is an up sawtooth wave type sweep signal, or the sweep signal is a down sawtooth wave type sweep signal, or the sweep signal is a triangle wave type sweep signal, or the sweep signal is a trapezoid wave type sweep signal.

The one or more technical schemes provided by the invention have at least the following technical effects or advantages:

according to the invention, through reasonably setting each state, the working steps are decomposed orderly and logically, so that the implementation efficiency of the frequency sweeping function is greatly improved;

the invention provides a multi-octave frequency sweep method adopting a shift algorithm, and the frequency sweep range is greatly expanded by combining a power frequency divider of 2;

the added exception handling means can flexibly and effectively interrupt the lock loss in the frequency sweeping process, and solves the problems of faults such as the lock loss caused by signal loss and the like in practical application;

the continuous mode and the external trigger mode provided by the invention can meet the requirements of different application scenes.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention;

FIG. 1 is a schematic diagram of the method;

fig. 2 is a schematic diagram of state switching in the present method.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than within the scope of the description, and the scope of the invention is therefore not limited to the specific embodiments disclosed below.

Example 1

Referring to fig. 1, fig. 1 is a schematic diagram of a multiple frequency sweep method, which is a method for controlling a frequency sweep frequency division ratio by a shift algorithm, thereby realizing a multiple octave frequency sweep function.

The embodiment of the invention is realized by the following technical scheme: the device comprises a sweep frequency module, a delta-sigma decimal modulator module, a phase-locked loop and a power frequency divider of 2, wherein the sweep frequency module, the delta-sigma decimal modulator module and the phase-locked loop are realized in multiple octaves. The algorithm of the first two modules is realized by synthesizing hardware description language (Hardware Description Language, HDL) (such as verilog language and the like) into a digital circuit, the integer frequency division ratio and the fractional frequency division ratio of the output of the sweep frequency module are used as the input of the delta-sigma fractional modulator, and the power frequency divider of 2 can be realized by adopting a digital circuit or an analog circuit.

The working frequency of the sweep frequency module is controlled by the phase discrimination frequency fref of the phase-locked loop, and in a locking state, the working frequency of the sweep frequency module and the working frequency of the delta-sigma decimal modulator are ensured to be the same and have fixed phase difference. In the circuit, the clock clk_ swp represented as a sweep module is connected with the phase discrimination clock clk_ref of the phase-locked loop, and for convenience of explanation, the invention provides that the values of the integer frequency division ratio nint and the fractional frequency division ratio nfrac of the sweep output are updated in response to the rising edge of the sweep clock clk_ swp, that is, when the rising edge of clk_ swp comes. The initial frequency dividing ratio odiv_str and the final frequency dividing ratio odiv_ trm of the external control signals are input to the frequency sweep module to be used as octave control for indicating a frequency multiplication algorithm of the frequency sweep module, and after algorithm processing, the frequency sweep module outputs a control word odiv_cal to a power frequency divider of 2 to be used as a frequency dividing ratio switching signal for controlling the power frequency divider of 2. The power frequency divider of 2 outputs a multi-octave sweep frequency signal to the outside.

In the present invention, the maximum frequency division ratio achievable by the power-of-2 frequency divider is set for odiv_str > odiv_ trm, with odiv_str corresponding to the minimum frequency division ratio achievable by the power-of-2 frequency divider. Since the frequency divider has a frequency division ratio that is a power of 2, odiv_str and odiv_ trm are each values that are powers of 2.

The connection diagram of the three modules of the sweep frequency module, the delta-sigma decimal modulator module and the power divider of 2 is shown in figure 1. The clocks of the frequency sweep module and the delta-sigma decimal modulator are respectively controlled by a phase discrimination clock and a frequency division clock of the phase-locked loop, on the other hand, a locking indication signal LDT output by the phase-locked loop is connected with the input of the frequency sweep module, the delta-sigma decimal modulator outputs a frequency division ratio to the phase-locked loop, a multi-octave algorithm of the frequency sweep module is controlled by an initial frequency division ratio and a termination frequency division ratio which are input externally, and the variable frequency division ratio is output to a power divider of 2.

For a single octave sweep module, a variable integer division ratio nint and fractional division ratio nfrac are output, and the relation between the two signals and the output frequency fout is as follows:

fout＝fref×nint.nfrac。

where fref is the phase discrimination frequency of the phase locked loop, nint represents the integer part, nfrac represents the fractional part, for example 47 in 47.65 is nint,0.65 is nfrac, and nint.nfrac is accumulated or decremented according to a fixed sweep step, so that the output frequency fout is linear, and in this way FMCW is realized. The range of the single octave swept output is determined by the range of nint.nfrac (maximum nint.nfrac@max and minimum nint.nfrac@min), i.e. the range of fout is maximum fref× (nint.nfrac@max) and minimum fref× (nint.nfrac@min).

In the following, nfrac needs to be converted to binary by the following formula: decimal nfracx 2^p, then converted to binary nfrac. Where p is the number of bits of the delta-sigma fractional modulator.

For a multi-octave sweep module, since the division ratio of the power divider of 2 can be controlled, and odiv_str corresponds to the maximum division ratio achievable by the power divider of 2, the minimum value of the frequency range fout of the achievable sweep output is fref× (nint.nfrac@min)/odiv_str, and odiv_ trm corresponds to the minimum division ratio achievable by the power divider of 2, and the maximum value of the frequency range fout of the achievable sweep output is fref× (nint.nfrac@max)/odiv_ trm. Compared with a single octave frequency sweep module, the output frequency range of the multi-octave frequency sweep module is greatly increased (for example, the odiv_ trm is set to be 1 frequency division), so that the range of practical application is further expanded.

The multi-octave frequency sweep method applied by combining the power divider of 2 comprises 8 states, including an initialization and locking judgment state (marked as S1), a frequency sweep mode judgment state (marked as S2), an uplink frequency sweep state (marked as S3), a downlink frequency sweep state (marked as S4), an initial unlocking processing state (marked as S5), an uplink unlocking processing state (marked as S6), a downlink unlocking processing state (marked as S7) and a termination state (marked as S8), and the switching among the states is shown in figure 2.

The frequency sweep direction comprises an uplink frequency sweep and a downlink frequency sweep. The initial frequency of the uplink frequency sweep, namely the frequency sweep, is smaller than the final frequency, and the uplink frequency sweep is represented as a slope upward on a relation chart taking a time axis as a horizontal axis and a frequency axis as a vertical axis; the initial frequency fstr of the downlink frequency sweep is larger than the final frequency ftrm, and the downlink frequency sweep is characterized by downward slope on a relation graph with a time axis as a horizontal axis and a frequency axis as a vertical axis.

The invention can realize the sweep frequency of any waveform, and the specific implementation mode is as follows:

the arbitrary waveform frequency sweep of the invention is formed by sequentially connecting multiple sections, the frequency sweep direction of each section can be any one of uplink frequency sweep, downlink frequency sweep and parallel frequency sweep, and each section can correspond to different frequency sweep time lengths; for adjacent sweep frequency segments in the same direction, if the sweep frequency time is different, the segments can be regarded as different segments; for convenience of explanation, the embodiment of the invention adopts 3 segments for illustration, and the number of segments of any waveform can be expanded in practical application. The sawtooth wave is divided into an upper sawtooth wave and a lower sawtooth wave, wherein the upper sawtooth wave can be characterized as an uplink sweeping frequency band; the lower sawtooth wave can be characterized as a section of descending sweeping frequency band; the triangular wave can be characterized as that an uplink sweep frequency section is connected with a downlink sweep frequency section; the trapezoidal wave can be characterized as an uplink sweep segment connected with a parallel sweep segment and then connected with a downlink sweep segment.

In order to realize the scanning of any waveform, each section of sweep frequency signal section needs to be marked according to actual needs, wherein the number of the sweep frequency signal sections can be designed according to the requirements of actual sweep frequency signals, the embodiment is only exemplified by 8 th sections, but is not limited to 8 th sections, and only a mode thought which can be realized is provided.

For convenience of explanation, the first-segment initial integer frequency division ratio is labeled as nint_ramp0, the first-segment initial fractional frequency division ratio is labeled as nfrac_ramp0, and the first-segment sweep frequency step is labeled as step_ramp0; the initial integer frequency division ratio of the second section, namely the final integer frequency division ratio of the first section, is marked as nint_ramp1, the initial fractional frequency division ratio of the second section, namely the final fractional frequency division ratio of the first section, is marked as nfrac_ramp1, and the sweep frequency step of the second section is marked as step_ramp1; the starting integer frequency division ratio of the third section, namely the ending integer frequency division ratio of the second section, is marked as nint_ramp2, the starting fractional frequency division ratio of the third section, namely the ending fractional frequency division ratio of the second section, is marked as nfrac_ramp2, and the sweep frequency step of the third section is marked as step_ramp2; the starting integer frequency division ratio of the fourth section, namely the ending integer frequency division ratio of the third section, is marked as nint_ramp3, the starting fractional frequency division ratio of the fourth section, namely the ending fractional frequency division ratio of the third section, is marked as nfrac_ramp3, and the sweep frequency step of the fourth section is marked as step_ramp3; the initial integer frequency division ratio of the fifth section, namely the final integer frequency division ratio of the fourth section, is marked as nint_ramp4, the initial fractional frequency division ratio of the fifth section, namely the final fractional frequency division ratio of the fourth section, is marked as nfrac_ramp4, and the sweep frequency step of the fifth section is marked as step_ramp4; the starting integer frequency division ratio of the sixth section, namely the ending integer frequency division ratio of the fifth section, is marked as nint_ramp5, the starting fractional frequency division ratio of the sixth section, namely the ending fractional frequency division ratio of the fifth section, is marked as nfrac_ramp5, and the sweep frequency step of the sixth section is marked as step_ramp5; the initial integer frequency division ratio of the seventh section, namely the final integer frequency division ratio of the sixth section, is marked as nint_ramp6, the initial fractional frequency division ratio of the seventh section, namely the final fractional frequency division ratio of the sixth section, is marked as nfrac_ramp6, and the sweep frequency step of the seventh section is marked as step_ramp6; the starting integer frequency division ratio of the eighth section, namely the ending integer frequency division ratio of the seventh section, is marked as nint_ramp7, the starting fractional frequency division ratio of the eighth section, namely the ending fractional frequency division ratio of the seventh section, is marked as nfrac_ramp7, and the sweep frequency step of the eighth section is marked as step_ramp7; the ending integer divide ratio of the eighth segment is labeled nint_ramp8 and the ending fractional divide ratio of the eighth segment is labeled nfracramp 8. The frequency division ratio and the step are set according to the application waveform, the number of the sections is selected through a gating device, and the invalid sweep frequency section is shielded.

The upper saw-tooth wave sweep frequency needs to be configured with nint_ramp0, nfrac_ramp0, step_ramp0, nint_ramp1 and nfrac_ramp1 according to design requirements, shielding other frequency division ratios and steps, and at least meeting one of the following two conditions needs to be ensured:

1)nint_ramp0＜nint_ramp1；

2) nint_rap0=nint_rap1 and nfracjrap0 < nfracjrap1

The lower saw-tooth wave sweep frequency needs to be configured with nint_ramp0, nfrac_ramp0, step_ramp0, nint_ramp1 and nfrac_ramp1 according to design requirements, shielding other frequency division ratios and steps, and at least meeting one of the following two conditions needs to be ensured:

1)nint_ramp0＞nint_ramp1；

2) nint_ramp 0=nint_ramp 1 and nfracjramp 0 > nfracjramp 1;

the triangular wave sweep frequency needs to configure nint_ramp0, nfrac_ramp0, step_ramp0, nint_ramp1, nfrac_ramp1, step_ramp1, nint_ramp2, nfrac_ramp2 according to the design requirement, and shielding other frequency division ratios and steps, and at least one of the following four conditions needs to be guaranteed to be met:

1) nint_ramp0 < nint_ramp1 and nint_ramp1 > nint_ramp2;

2) nint_rap0=nint_rap1 and nfracjrap0 < nfracjrap1 and nint_rap1 >

nint_ramp2；

3) nint_ramp0 < nint_ramp1 and nint_ramp 1=nint_ramp 2 and nfrac_ramp1 >

nfrac_ramp2；

4) nint_rap0=nint_rap1 and nfracjrap0 < nfracjrap1 and nint_rap1=

nint_ramp2 and nfrac_ramp1 > nfrac_ramp2;

the trapezoidal wave frequency sweep needs to configure nint_ramp0, nfrac_ramp0, step_ramp0, nint_ramp1, nfrac_ramp1, step_ramp1, nint_ramp2, nfrac_ramp2, step_ramp2, nint_ramp3, nfrac_ramp3 according to the design requirement, and shielding other frequency division ratios and steps, and at least one of the following four conditions needs to be guaranteed:

1) nint_ramp0 < nint_ramp1 and nint_ramp2 > nint_ramp3 and nint_ramp1 =

nint_ramp2 and nfracjramp 1=nfracjramp 2;

2) nint_ramp0=nint_ramp1 and nfracjramp0 < nfracjramp1 and nint_ramp2 >, respectively

nint_ramp3 and nint_ramp 1=nint_ramp 2 and nfracramp_ramp 1=nfrac_ramp 2;

3) nint_ramp0 < nint_ramp1 and nint_ramp 2=nint_ramp 3 and nfrac_ramp2 >

nfracram 3 and nint_ramp1=nint_ramp2 and nfracram_ramp1=nfracram_ramp2;

4) nint_rap0=nint_rap1 and nfracjrap0 < nfracjrap1 and nint_rap2=

nint_ramp3 and nfrac_ramp2 > nfrac_ramp3 and nint_ramp 1=nint_ramp 2 and nfrac_ramp1

＝nfrac_ramp2；

The sweep frequency duration is the elapsed time t from the beginning to the ending frequency, and the slope k of the sweep frequency can be obtained by the following formula:

k＝(ftrm-fstr)/t

the relation between the sweep frequency stepping step and the sweep frequency duration t is as follows:

step＝t×fref

The above-mentioned characteristic sweep frequency duration is in direct proportion to the sweep frequency step and phase discrimination frequency.

For ease of description, in the following discussion, the power of 2 divider is defined as odiv.

The S1 state step of the invention is as follows:

the first step, shift algorithm operation is carried out on the input initial integer frequency division ratio nint_str, initial fractional frequency division ratio nfrac_str and initial odiv frequency division ratio odiv_str, and the initial integer frequency division ratio nint_str_expansion and the initial fractional frequency division ratio nfrac_str_expansion are processed; the algorithm processing method comprises the following steps:

1) When odiv_str=1, i.e., the starting odiv division ratio is divide by 1, nint_str_expansion=nint_str,

nfrac_str_expand＝nfrac_str；

2) When odiv_str=2, i.e. the starting odiv frequency division ratio is 2, the integer frequency division ratio nint_str and the fractional frequency division ratio nfrac_str need to be multiplied by 2, and the carry problem of nfrac_str needs to be considered, so the following steps are adopted:

a) After the two are respectively converted into binary, the bit number is determined by the bit number of the delta-sigma decimal modulator, and the bit numbers are respectively kept unchanged in the process of carrying out a shifting algorithm;

b) Shift 1 bit to the left of nint_str and register as nint_str_a;

c) Whether to carry is decided according to whether the most significant bit of nfracstr is 1:

i. when the most significant bit of binary nfrac_str is 1, it is necessary to advance 1 bit to the integer, i.e

nint_str_a+1＝nint_str_expand；

When the most significant bit of binary nfrac_str is 0, no carry to integer is required, i.e

nint_str_a＝nint_str_expand；

d) Then, the nfrac_str is shifted to the left by 1 bit to obtain nfrac_str_expansion.

3) When odiv_str=4, that is, when the starting odiv frequency division ratio is 4, a multiplication 4 algorithm is required for the integer frequency division ratio nint_str and the fractional frequency division ratio nfrac_str, and the carry problem of nfrac_str is considered, and the carry operation is equal to an operation of multiplying 2 and then multiplying 2, so that 4 cases are considered, and the following steps are adopted:

b) Shift 2 bits left to nint_str and register as nint_str_b;

c) The carry case is selected according to the most significant and next most significant (i.e., high) bits of nfracstr:

i. when the highest and next highest bits of binary nfrac_str are 1 and 1, respectively, 3 bits are required to be added to the integer, i.e., nint_str_b+3=nint_str_expansion;

when the highest and next highest bits of binary nfrac_str are 1 and 0, respectively, 2 bits are needed to advance the integer, i.e., nint_str_b+2=nint_str_expansion;

when the highest and next highest bits of binary nfrac_str are 0 and 1, respectively, 1 bit is needed to the integer, i.e., nint_str_b+1=nint_str_expansion;

When the highest and next highest bits of binary nfrac_str are 0 and 0, respectively, no carry to the integer is required, i.e., nint_str_b=nint_str_expansion;

d) Then, the nfrac_str is shifted to the left by 2 bits to obtain nfrac_str_expansion.

4) When odiv_str=8, that is, when the starting odiv frequency division ratio is 8, the integer frequency division ratio nint_str and the fractional frequency division ratio nfrac_str need to be multiplied by 8, and the carry problem of nfrac_str needs to be considered, and the carry operation is equal to an operation of multiplying 2 and then multiplying 2, so that 8 cases need to be considered, and the following steps are adopted:

b) Shift 3 bits left to nint_str and register as nint_str_c;

c) The carry case is selected according to the upper three bits of nfracstr:

i. when the upper three bits of the binary nfrac_str are 111, respectively, 7 bits of the integer are required, i.e

nint_str_c+7＝nint_str_expand；

When the upper three bits of the binary nfrac_str are 110, respectively, it is necessary to advance the integer by 6 bits, i.e

nint_str_c+6＝nint_str_expand；

When the upper three bits of binary nfrac_str are 101, respectively, it is necessary to advance the integer by 5 bits, i.e

nint_str_c+5＝nint_str_expand；

When the upper three bits of the binary nfrac_str are 100, respectively, it is necessary to advance the integer by 4 bits, i.e

nint_str_c+4＝nint_str_expand；

v. when the upper three bits of binary nfrac_str are 011 respectively, 3 bits of the integer are required, i.e

nint_str_c+3＝nint_str_expand；

When the upper three bits of binary nfrac_str are 010 respectively, it is necessary to advance the integer by 2 bits, i.e

nint_str_c+2＝nint_str_expand；

When the upper three bits of the binary nfrac_str are 001, respectively, it is necessary to advance 1 bit to the integer, i.e

nint_str_c+1＝nint_str_expand；

viii when the upper three bits of binary nfrac_str are 000 respectively, no carry to integer is required, i.e

nint_str_c＝nint_str_expand；

d) Then, the nfrac_str is shifted to the left by 3 bits to obtain nfrac_str_expansion.

5) Similarly, when odiv_str=2ζ (m represents the power of 2 and 2ζ represents the power of 2), that is, when the starting odiv frequency division ratio is 2ζ, the integer frequency division ratio nint_str and the fractional frequency division ratio nfrac_str need to be multiplied by 2ζ algorithm, and the carry problem of nfrac_str needs to be considered, since the operation is equivalent to m times of 2, the carry operation needs to consider the cases of 2ζ, and therefore the following steps are adopted:

b) Shifting the bit of nint_str left and temporarily storing as nint_str_c;

c) Carry cases are selected according to the upper m bits of nfracstr:

i. when the upper m bits of binary nfrac_str are all 1's (denoted as k, k=2 ζ -1), it is necessary to advance the integer by 2 ζ -1 bits, i.e., nint_str_c+2 ζ -1=nint_str_expan;

When the upper m bits of binary nfrac_str are k-1 (corresponding binary), respectively, it is necessary to advance the integer by 2 m-2 bits, i.e., nint_str_c+2 m-1=nint_str_expansion;

the following is a analogy

When the upper m bits of binary nfrac_str are 1, respectively, it is necessary to advance 1 bit to the integer, i.e

nint_str_c+1＝nint_str_expand；

When the upper m bits of binary nfrac_str are all 0's, respectively, no carry to the integer is required, i.e., nint_str_c=nint_str_expand;

d) Then shifting nfrac_str left by m bits to obtain nfrac_str_expansion;

e) Nfrac_str_expansion is stored in a temporary register nfrac_tmp, and nint_str_expansion is stored in a temporary register nint_tmp.

The second step, shift algorithm operation is carried out on the input termination integer frequency division ratio nint_ trm, termination fractional frequency division ratio nfrac_ trm and termination odiv frequency division ratio odiv_ trm, and the shifting algorithm operation is processed into an extended termination integer frequency division ratio nint_ trm _expansion and an extended termination fractional frequency division ratio nfrac_ trm _expansion; the algorithm processing method comprises the following steps:

1) When odiv_ trm =1, i.e., the ending odiv division ratio is divide by 1, nint_ trm _expansion=nint_ trm,

nfrac_trm_expand＝nfrac_trm；

2) When odiv_ trm =2, i.e. when stopping the division by odiv with division ratio of 2, the multiplication by 2 algorithm is needed for both the integer division ratio nint_ trm and the fractional division ratio nfrac_ trm, and the carry problem of nfrac_ trm is considered, so the following steps are adopted:

b) Shift nint_ trm left by 1 bit and register as nint_ trm _a;

c) Whether to carry is decided according to whether the most significant bit of nfrac trm is 1:

i. when the highest order bit of binary nfrac trm is 1, it is necessary to advance 1 bit to the integer, i.e

nint_trm_a+1＝nint_trm_expand；

When the most significant bit of binary nfrac trm is 0, no carry to integer is required, i.e

nint_trm_a＝nint_trm_expand；

d) Then moving nfrac trm left by 1 bit to obtain nfrac trm _expansion.

3) When odiv_str=4, i.e. when stopping the division by odiv frequency division ratio of 4, the multiplication 4 algorithm is needed for the integer division ratio nint_ trm and the fractional division ratio nfrac_ trm, and the carry problem of nfrac_ trm is considered, and the carry operation is equal to the multiplication 2 operation and then the multiplication 2 operation, so that the carry operation is considered for 4 cases, the following steps are adopted:

b) Shift nint_ trm by 2 bits to the left and register as nint_ trm _b;

c) The carry case is selected according to the highest and next highest (i.e., high) bits of nfrac trm:

i. When the highest and next highest bits of binary nfrac_ trm are 1 and 1, respectively, 3 bits are required to be added to the integer, i.e., nint_ trm _b+3=nint_ trm _expansion;

when the highest and next highest bits of binary nfrac trm are 1 and 0, respectively, it is necessary to advance the integer by 2 bits, i.e., nint trm _b+2=nint trm _expansion;

when the highest and next highest bits of binary nfrac trm are 0 and 1, respectively, 1 bit is needed to the integer, i.e., nint_ trm _b+1=nint_ trm _expansion;

when the highest and next highest bits of binary nfrac trm are 0 and 0, respectively, no carry to the integer is required, i.e., nint trm _b=nint trm _expand;

d) Then moving the nfrac trm left by 2 bits to obtain nfrac trm _expansion.

4) When odiv_ trm =8, i.e. when stopping the division by odiv, the integer division ratio nint_ trm and the fractional division ratio nfrac_ trm need to be multiplied by 8, and the carry problem of nfrac_ trm needs to be considered, the carry operation is equal to the operation of multiplying 2 and then multiplying 2, so the carry operation needs to consider 8 cases, and the following steps are adopted:

b) Shift nint_ trm left by 3 bits and register as nint_ trm _c;

c) The carry case is selected according to the upper three bits of nfrac trm:

i. when the upper three bits of binary nfrac_ trm are 111, respectively, 7 bits are required to be added to the integer, i.e., nint_ trm _c+7=nint_ trm _expansion;

when the upper three bits of binary nfrac trm are 110, respectively, it is necessary to advance the integer by 6 bits, i.e., nint trm _c+6=nint trm _expansion;

when the upper three bits of binary nfrac trm are 101, respectively, it is necessary to advance the integer by 5 bits, i.e., nint trm _c+5=nint trm _expansion;

when the upper three bits of binary nfrac trm are 100, respectively, it is necessary to advance the integer by 4 bits, i.e., nint trm _c+4=nint trm _expansion;

when the upper three bits of binary nfrac trm are 011 respectively, 3 bits are needed to be added to the integer, namely nint trm _c+3=nint trm _expansion;

when the upper three bits of binary nfrac trm are 010 respectively, it is necessary to advance the integer by 2 bits, namely nint trm _c+2=nint trm _expansion;

when the upper three bits of binary nfrac trm are 001, respectively, 1 bit is needed to be added to the integer, i.e., nint trm _c+1=nint trm _expansion;

when the upper three bits of binary nfrac trm are 000 respectively, no carry to the integer is required, i.e., nint trm _c=nint trm _expand;

d) Then moving nfrac trm left by 3 bits to obtain nfrac trm _expansion.

5) Similarly, when odiv_ trm =2ζ (m represents the power of 2 and 2ζ represents the power of 2), i.e. when the odiv frequency division ratio is terminated by 2ζ, the integer frequency division ratio nint_ trm and the fractional frequency division ratio nfrac_ trm need to be multiplied by 2ζ algorithm, and the carry problem of nfrac_ trm needs to be considered, which is equivalent to m times 2, so the carry operation needs to consider the cases of 2ζ, and the following steps are adopted:

b) Shift left m bits for nint_ trm and register as nint_ trm _c;

c) The carry case is selected according to the upper m bits of nfrac trm:

i. when the upper m bits of binary nfrac trm are all 1's (denoted as k, k=2 μm-1), respectively,

it is necessary to advance the integer by 2 m-1 bits, i.e., nint_ trm _c+2 m-1=nint_ trm _expansion;

when the upper m bits of binary nfrac trm are k-1 (corresponding binary), respectively, it is necessary to advance the integer by 2 m-2 bits, namely nint trm _c+2 m-1 = nint trm _expansion;

the following is a analogy

When the upper m bits of binary nfrac trm are 1 respectively, it is necessary to advance 1 bit to the integer, i.e

nint_trm_c+1＝nint_trm_expand；

When the upper m bits of binary nfrac trm are all 0's, respectively, no carry to the integer is required, i.e., nint trm _c=nint trm _expand;

d) Then shifting nfrac_ trm left by m bits to obtain nfrac_ trm _expansion.

Thirdly, judging the state of the current phase-locked loop through the locking instruction LDT, and entering the next state S2 if the phase-locked loop is in a locked state. If the phase-locked loop is in an unlocking state, the phase-locked loop is switched from an S1 state to an S5 state, enters a re-locking process, returns to the S1 state after locking is completed, and is immediately switched to an S2 state.

The S2 state of the invention judges the frequency sweep mode according to the externally set frequency sweep mode and judges the frequency sweep direction (uplink or downlink), and the steps of the state are as follows:

the first step is to make a decision according to an externally set sweep frequency mode. Taking the invention as an example, the sweep frequency modes comprise three modes of continuous bidirectional sweep frequency, trigger type bidirectional sweep frequency and trigger type unidirectional sweep frequency. The continuous bidirectional frequency sweep refers to that the uplink frequency sweep and the downlink frequency sweep are alternately performed, namely, the downlink frequency sweep is performed immediately after the uplink frequency sweep, the uplink frequency sweep is performed immediately after the downlink frequency sweep, and the like, and the frequency sweep is continuously performed, so that triangular waveforms are realized; the trigger type bidirectional frequency sweep is similar to the direction of continuous bidirectional frequency sweep, and the uplink and downlink frequency sweeps are alternately carried out, but the uplink or downlink frequency sweep needs to be controlled and started by an external trigger signal; the triggering unidirectional frequency sweep adopts an uplink frequency sweep, and returns to a starting frequency point after the uplink frequency sweep is finished, and the starting of each uplink frequency sweep is controlled by an external triggering signal. For the sweep mode of this state, for example, a mode of adding an arbitrary sweep waveform can be referred to in the patent of the application, "arbitrary waveform sweep method based on a continuously controlled delta-sigma decimal modulator".

Setting an odiv change direction pointer, namely indicating the change condition of the frequency division ratio of the power frequency divider of 2 in the frequency sweeping process, wherein the pointer is marked as odiv_updw, when the odiv changes from a high frequency division ratio to a low frequency division ratio, the frequency sweeping is performed from a low frequency to a high frequency, and if no jump exists, the odiv_up=1 is set as the frequency sweeping pointer; when odiv changes from low to high frequency, the sweep is from high to low frequency, odiv_dw=1, and 0 if there is no transition. By setting the odiv_up and odiv_dw pointers, continuous coverage of the sweep frequency can be realized between different octaves. And storing the odiv_str in a temporary register odiv_tmp, switching to the next octave after the sweep of one octave is completed, updating the corresponding odiv_tmp, and ending the updating until the odiv_ trm is reached.

And thirdly, after the sweep frequency mode is determined, the uplink or downlink sweep frequency needs to be judged. Taking the invention as an example, for continuous bidirectional frequency sweep and trigger bidirectional frequency sweep, when uplink frequency sweep is adopted, the state S2 is switched to the state S3, and when downlink frequency sweep is adopted, the state S2 is switched to the state S4. For the triggered unidirectional sweep, the current state S2 is directly switched to the state S3 because only the uplink sweep is adopted.

S3 is uplink sweep frequency treatment.

The method comprises the following steps:

the first step is to obtain an increment of the frequency division ratio of the sweep module by accumulating nfrac_tmp in steps controlled by clk_ swp clock, i.e. updating the values of nint_tmp and nfrac_tmp once every time clk_ swp rises;

secondly, after the steps are finished, if the abnormal state of the lock loss occurs, the abnormal processing stage after the lock loss needs to be immediately shifted to, namely, judging whether the state switching is performed or not through a locking instruction LDT, and switching from the S3 state to the S6 state when the lock loss occurs; if the lock is still maintained, continuing the present state (S3);

third, a decision is made as to whether nint_tmp and nfrac_tmp have reached the ending integer divide ratio and ending fractional divide ratio, the arrival decisions being made according to the following criteria:

1) When the current power of 2 divider has a division ratio of odiv_ trm and nint_tmp > nint_ trm _expansion;

2) When nint_tmp=nint_ trm _expansion and nfrac_tmp > nfrac_ trm _expansion.

When the two criteria are met, it is considered that the two criteria arrive, and the switch from the S3 state to the S8 state is needed. If neither is satisfied, the present state is continued (S3).

The S4 is downlink sweep frequency treatment, and comprises the following steps:

first, a gradual decrease of the frequency division ratio of the sweep module is obtained by decrementing nfrac_tmp in steps controlled by clk_ swp clock, i.e. once every time the rising edge of clk_ swp, the values of nint_tmp and nfrac_tmp are updated once;

secondly, after the steps are finished, if the abnormal state of the lock loss occurs, the abnormal processing stage after the lock loss needs to be immediately shifted to, namely, judging whether the state switching is performed or not through a locking instruction LDT, and switching from the S4 state to the S7 state when the lock loss occurs; if the lock is still maintained, continuing the present state (S4);

third, a decision is made as to whether nint_tmp and nfrac_tmp have reached the starting integer divide ratio and the starting fractional divide ratio of the first segment, the arrival decision being made according to the following criteria:

1) When the current division ratio of the power-of-2 divider is odiv_str and nint_tmp < nint_str_expansion;

2) When nint_tmp=nint_str_expansion and nfrac_tmp < nfrac_str_expansion.

When the two criteria are met, it is considered that the two criteria arrive, and the switch from the S4 state to the S8 state is needed. If neither is satisfied, the present state is continued (S4).

The step of S5 state is to make the timer count from 0 by configuring the time length of the timer externally, and switch from S5 state to S1 state after the timer is full, in order to make the sweep frequency module enter sleep, and wait for the phase-locked loop to finish locking from losing lock to re-locking in the sleep process.

The step of S6 state of the invention is:

in the first step, when the pointer odiv_up=1, the division ratio of the power divider of 2 is shifted from high division ratio to low division ratio, and the values in nint_tmp and nfrac_tmp are divided by 2 respectively to adapt to the new octave, and the shift algorithm is performed on the binary system to shift one bit to the right at the same time.

And secondly, the timer is timed from 0 by externally configuring the duration of the timer, and the state is switched from the S6 state to the S3 state after the timer is full, so that the sweep frequency module is put into dormancy, and the phase-locked loop is waited for finishing the process from losing lock to re-locking in the dormancy process.

The step of S7 state of the invention is:

in the first step, when the pointer odiv_dw=1, the division ratio of the power divider of 2 is shifted from a low division ratio to a high division ratio, and the values in nint_tmp and nfrac_tmp are multiplied by 2 respectively to adapt to the new octave, and the shift algorithm is performed on the binary system to shift one bit leftwards at the same time.

And secondly, the timer is timed from 0 by externally configuring the duration of the timer, and the state is switched from the S7 state to the S4 state after the timer is full, so that the sweep frequency module is put into dormancy, and the phase-locked loop is waited to finish locking from unlocking to re-locking in the dormancy process.

The S8 state is the next state judged according to the frequency sweep mode, when the frequency sweep mode is continuous, the state is switched from S8 to S2 in the continuous bidirectional frequency sweep mode, and a new round of uplink and downlink frequency sweep is automatically entered, so that continuous frequency sweep work is realized; when the sweep frequency mode is trigger type, in the invention, the trigger type bidirectional sweep frequency and the trigger type unidirectional sweep frequency are switched from S8 to S1, a relock process is needed to be entered, and after the relock is finished, the S1 is switched to S2, an instruction command of an external trigger signal is waited, and a new round of sweep frequency is entered, so that the trigger type sweep frequency is realized.

The transition diagram of each state described above is shown in fig. 2.

Starting to enter an S1 state from the starting sweep frequency, after the configuration of the initialization parameters is completed in the S1, switching to an S5 state if the initialization parameters are unlocked, switching back to the S1 state after waiting for the phase-locked loop to be locked again in the S5 state, and switching to an S2 state if the initialization parameters are locked; in the S2 state, the sweep frequency mode judgment is carried out, in the judgment of the sweep frequency direction, if the sweep frequency is the uplink sweep frequency, the S2 is switched to the S3 state, if the sweep frequency is the downlink sweep frequency, the S2 is switched to the S4 state, and the pointer of the power frequency division ratio jump of 2 is set so as to indicate the octave switching of the sweep frequency; in the S3 state, uplink sweep frequency control is carried out, judgment of ending the frequency division ratio is carried out, locking judgment is carried out at the same time, and if the lock is lost, switching to S6 is carried out; in the S4 state, downlink sweep frequency control is carried out, judgment of reaching an initial frequency division ratio is carried out, locking judgment is carried out at the same time, and if the lock is lost, switching to S7 is carried out; s5, carrying out locking judgment in the initial process, and switching back to the S1 state if the locking is carried out; s6, carrying out locking judgment in the uplink process, and switching back to the S3 state if the locking is carried out; s7, carrying out locking judgment in the downlink process, and switching back to the S4 state if the locking is carried out; and S8, determining to enter the next section of frequency sweeping state according to the frequency sweeping mode, switching to S2 if the frequency sweeping is continuous, and switching to S1 if the frequency sweeping is triggered.

Example two

Based on the first embodiment, the second embodiment of the invention takes the triangular wave for realizing continuous bidirectional frequency sweep as an example, the time length of the uplink and downlink frequency sweep parts of the triangular wave is 50us, the phase discrimination frequency of the clock output to the frequency sweep module by the phase-locked loop is 100MHz, the frequency division frequency of the clock output to the delta-sigma decimal modulator is 100MHz, and the delta-sigma decimal modulator is 8 bits. The lowest frequency division ratio configured under single octave is 42, the fractional frequency division ratio is 0.5, the highest frequency division ratio is 47, the fractional frequency division ratio is 0.5, the lowest frequency under single octave is 4250MHz, the highest frequency is 4750MHz, and the sweep frequency step is obtained by the formula step=t×fref. The highest frequency division ratio of the power of 2 divider is 2 and the lowest frequency division ratio is 1.

The following parameters are correspondingly configured:

nint_str＝42

nfrac_str＝0.5

step＝5000

nint_trm＝47

nfrac_trm＝0.5

odiv_str＝2

odiv_trm＝1

the lowest frequency of the frequency-multiplied sweep is 2125MHz by the formula fref× (nint. Nfrac@min)/odiv_str, and the highest frequency is 4750Mz by the formula fref× (nint. Nfrac@max)/odiv_ trm. Compared with the single octave frequency sweep range, the frequency sweep range of multiple frequency is expanded by 2125MHz.

The above configuration satisfies the design requirements of the triangular wave described above.

The sweep is started, the S1 state is entered, the configured nint_str=42 is stored in the temporary register nint_tmp, nfrac_str=0.5 is stored in the temporary register nfrac_tmp, and the same time, the rising edge of clk_ swp is temporarily output to the delta-sigma decimal modulator. Judging the state of the current phase-locked loop through the locking instruction LDT, and switching from the S1 state to the S5 state if the phase-locked loop is in an unlocking state; the initial state of the phase-locked loop in the embodiment is an out-of-lock state, the phase-locked loop is switched from the S1 state to the S5 state, the sweep frequency module enters dormancy through the time length of an external configuration timer in the S5, the phase-locked loop waits for the completion of the out-of-lock to the re-lock in the dormancy process, and the phase-locked loop is switched from the S5 state to the S1 state.

Shifting algorithm operation is carried out on the input initial integer frequency division ratio nint_str, the initial fractional frequency division ratio nfrac_str and the initial odiv frequency division ratio odiv_str, and the shifting algorithm operation is processed into an extended initial integer frequency division ratio nint_str_expansion and an extended initial fractional frequency division ratio nfrac_str_expansion; the algorithm processing method comprises the following steps:

1) Since odiv_str=2, i.e. when the starting odiv frequency division ratio is 2, the integer frequency division ratio nint_str and the fractional frequency division ratio nfrac_str need to be multiplied by 2, and the carry problem of nfrac_str needs to be considered, the following steps are adopted:

a) Respectively converting the two into binary, wherein the bit number is agreed to be 8 bits, nint_str=42 is converted into binary 00101010, and the formula is as follows: decimal nfrac_str× 2^8 =128, and converting into binary nfrac_str to obtain 10000000;

b) Shifting nint_str by 1 bit to the left and temporarily storing as nint_str_a= 01010100, corresponding to decimal value 84;

c) Judging whether to carry according to whether the highest bit of nfrac_str is 1, and if the highest bit of nfrac_str is 1, 1 bit needs to be fed into the integer, namely, nint_str_a+1=nint_str_expansion, so that 01010101 is obtained, and the corresponding decimal is 85;

d) Then shift left by 1 bit to nfrac_str to obtain nfrac_str_expansion

nfracstr_expansion=00000000, corresponding to decimal 0;

e) As can be seen from the above verification, 42.5×2=85.

2) When odiv_ trm =1, i.e., the ending odiv division ratio is 1 division, nint_ trm _expansion=nint_ trm, nfrac_ trm _expansion=nfrac_ trm, i.e., nint_ trm _expansion=00101111, nfractrm_expansion=10000000.

The frequency division ratio of the power divider of 2 is then indicated in the S1 state from high frequency division ratio 2 to low frequency division ratio 1 in the upstream frequency sweep and from low frequency division ratio 1 to high frequency division ratio 2 in the downstream frequency sweep. And then judging the state of the current phase-locked loop through the locking instruction LDT, and entering the next state S2 if the phase-locked loop is in a locking state. If the phase-locked loop is in an unlocking state, the phase-locked loop is switched from an S1 state to an S5 state, enters a re-locking process, returns to the S1 state after locking is completed, and is immediately switched to an S2 state.

In the S2 state, the sweep mode is first determined, and when the uplink sweep is adopted, the state S2 is switched to the state S3, the uplink sweep stage is entered first, and odiv_str=2 is stored in the temporary register odiv_tmp, because the continuous bidirectional sweep is adopted as a design requirement.

In the S3 state, step=5000 is added up nfrac_tmp to obtain increment of frequency division ratio of the sweep frequency module, so as to realize uplink sweep frequency, the step is controlled by clk_ swp clock, that is, every time clk_ swp rising edge comes, the values of nint_tmp and nfrac_tmp complete updating once, after this step is completed, if abnormal out-of-lock occurs, it is required to immediately shift to an abnormal processing stage after out-of-lock, that is, by locking to instruct LDT to decide whether to switch state, in the present example, the phase-locked loop still remains locked, then the present state is continued (S3); a pointer signal indicating an octave switch is set. At the same time, it is determined whether or not the nint_tmp and nfrac_tmp reach the ending integer division ratio nint_ trm _expansion and the ending fractional division ratio nfrac_ trm _expansion, which are not satisfied in this case, and the present state is continued (S3). When the octave has been scanned, in this case, the sweep frequency range is 2125M-4250 MHz. The indication signal odiv_up=1 indicates that when the next octave needs to be entered, an out-of-lock will occur, and the up-going out-of-lock processing state S6 is immediately entered. In this case, switching from a high division ratio of 2 to a low division ratio of 1, the second octave stage is entered.

In the S6 state, in response to the indication signal of odiv_up=1, the operations of dividing 2 by nint_tmp and nfrac_tmp are performed, that is, the operations of shifting 1 bit to the right in the two-way operation are performed, and the locked state is returned to the S3 state after the locked state is entered.

Continuing the increment operation of the uplink sweep frequency of the second octave stage in the S3 state, if the targets of ending the integer frequency division ratio and ending the fractional frequency division ratio are met, namely, when one of the following conditions is met:

2) When nint_tmp=nint_ trm _expansion and nfrac_tmp > nfrac_ trm _expansion.

Then enter state S8, finish the second octave up sweep frequency range is 4250M-4750 MHz, the continuous switching of two octaves has realized 2125M-4750 MHz up sweep frequency range.

In S8, the continuous bidirectional sweep is judged according to the sweep mode, and then the switching is carried out to S2. In S2, the frequency sweep is switched from the uplink frequency sweep to the downlink frequency sweep, and the frequency sweep is switched from S2 to S4.

In S4, the gradual reduction of the frequency division ratio of the sweep frequency module is obtained by decrementing nfrac_tmp by a step step=5000, the step is controlled by the clk_ swp clock, that is, the values of the nint_tmp and nfrac_tmp are updated once every time the rising edge of clk_ swp is reached, when this step is completed, if an abnormality of lock loss occurs, it is required to immediately shift to an abnormality processing stage after lock loss, that is, by locking to instruct LDT decision whether to perform state switching, in this example, the phase locked loop still remains locked, then the present state is continued (S4), while decision is made as to whether the nint_tmp and nfrac_tmp reach the initial integer division ratio nint_str and the final fractional division ratio nfrac_str, and when not satisfied, the present state is continued (S4). When the octave has been scanned, in this case, the sweep frequency range is 4750M-4250 MHz. The indication signal odiv_dw=1 indicates that when the next octave needs to be entered, an out-of-lock will occur, and the uplink out-of-lock processing state S7 is immediately shifted. In this case, switching from a low division ratio of 1 to a high division ratio of 2, the second octave stage is entered.

In the S7 state, in response to the indication signal of odiv_dw=1, the multiplication 2 operation is performed on nint_tmp and nfrac_tmp, i.e. 1 bit shift to the left is performed on the two-way, and the re-lock stage is entered, and the state returns to the S4 state after locking.

Continuing the decrementing operation of the upstream sweep of the second octave stage in the S4 state if the objectives of reaching the initial integer divide ratio and the initial fractional divide ratio are met, i.e., when one of the following conditions is met:

2) When nint_tmp=nint_str_expansion and nfrac_tmp < nfrac_str_expansion.

Then enter state S8, finish the up sweep frequency range of the second octave as 4250M-2125 MHz, the continuous switching of two octaves has realized the downstream sweep frequency range of 4750M-2125 MHz.

In S8, the continuous bidirectional sweep is judged according to the sweep mode, and then the switching is carried out to S2. In S2, the frequency sweep is switched from the downlink frequency sweep to the uplink frequency sweep, and the operation steps are repeated from S2 to S3, so that continuous bidirectional frequency sweep is realized.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. The frequency multiplication frequency sweeping method is characterized by being applied to a frequency sweeping device, wherein the frequency sweeping device comprises: the device comprises a sweep frequency module, a delta-sigma decimal modulator module, a frequency divider and a phase-locked loop; the clocks of the sweep frequency module and the delta-sigma decimal modulator module are respectively controlled by a phase discrimination clock and a frequency division clock of the phase-locked loop, a locking indication signal LDT output by the phase-locked loop is connected with the input of the sweep frequency module, the integer frequency division ratio and the decimal frequency division ratio output by the sweep frequency module are used as the input of the delta-sigma decimal modulator module, and the delta-sigma decimal modulator module outputs the frequency division ratio to the phase-locked loop;

the method comprises the following steps:

setting a plurality of working states of the frequency sweeping device;

The frequency sweep device is controlled to switch in a plurality of working states, so that the frequency divider outputs a multi-octave frequency sweep signal;

the frequency sweep device comprises 8 working states, namely: an initialization and locking judgment state S1, a sweep frequency mode judgment state S2, an uplink sweep frequency state S3, a downlink sweep frequency state S4, an initial unlocking processing state S5, an uplink unlocking processing state S6, a downlink unlocking processing state S7 and a termination state S8;

in the state S8, determining to enter the next section of sweep frequency state according to the sweep frequency mode, switching to the state S2 if the sweep frequency is continuous, and switching to the state S1 if the sweep frequency is triggered;

the sweep frequency signal comprises a plurality of sections of sweep frequency signal sections which are sequentially connected, the sweep frequency direction of each section of sweep frequency signal section is any one of uplink sweep frequency, downlink sweep frequency and parallel sweep frequency, and each section of sweep frequency signal section corresponds to a corresponding sweep frequency duration respectively;

the method also comprises the steps of marking the initial integer frequency division ratio and the initial fractional frequency division ratio of each sweep frequency signal section to obtain marking information, and configuring the condition information which needs to be met according to the sweep frequency signal.

2. The frequency-multiplied sweeping method of claim 1, wherein in state S1 comprises the steps of:

3. The frequency-multiplied sweep method of claim 1, wherein in state S2 comprises the steps of:

4. The multiple frequency sweep method according to claim 1, characterized in that in state S3 it comprises the steps of:

5. The multiple frequency sweep method according to claim 1, characterized in that in state S4 it comprises the steps of:

6. The frequency-multiplied sweep method of claim 1, wherein in state S6 comprises the steps of:

the state S7 includes the following steps:

7. The multiple frequency sweep method of claim 1, wherein the sweep signal is an up saw tooth wave type sweep signal, or the sweep signal is a down saw tooth wave type sweep signal, or the sweep signal is a triangle wave type sweep signal, or the sweep signal is a trapezoid wave type sweep signal.