CN115332358A - Two-dimensional material transistor structure and preparation method thereof - Google Patents
Two-dimensional material transistor structure and preparation method thereof Download PDFInfo
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- CN115332358A CN115332358A CN202210967917.3A CN202210967917A CN115332358A CN 115332358 A CN115332358 A CN 115332358A CN 202210967917 A CN202210967917 A CN 202210967917A CN 115332358 A CN115332358 A CN 115332358A
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Abstract
The invention discloses a two-dimensional material transistor structure and a preparation method thereof.A two-dimensional material layer is formed on a semiconductor substrate, a protective layer covering a channel region of the two-dimensional material layer is formed, a source contact region and a drain contact region on the two-dimensional material layer are exposed, the source contact region and the drain contact region are immersed in a reagent for Li intercalation, so that the two-dimensional material layer of the source contact region and the drain contact region induces phase change through Li intercalation, a 2H phase in a semiconductor state is induced to form a 1T phase in a metal state, a 2H-1T homojunction is formed on an interface between the two-dimensional material layer and the 2H phase two-dimensional material layer of the channel region, and meanwhile, the two-dimensional material in the 2H phase is used as a channel, thereby enhancing the conduction performance of a transistor device.
Description
Technical Field
The invention relates to the technical field of semiconductor device processes, in particular to a two-dimensional material transistor structure for improving transistor performance based on improved contact and a preparation method thereof.
Background
Two-dimensional transition metal chalcogenide compounds have attracted great interest as a novel atomic-scale thin film transistor channel material. However, in recent years, the performance of the transistor is greatly limited by the large contact resistance between the metal electrode at the source and drain and the semiconductor channel, which is one of the main problems affecting the performance of the two-dimensional material field effect transistor. The formation of schottky barriers affecting carrier injection and the presence of fermi level pinning effect have a great influence on device performance. In recent years, transistor contact improvement has been studied by several methods, such as contact topology, metal selection, and interface improvement.
Depositing metal on the source and drain regions of a two-dimensional material device can form a huge schottky barrier on the interface, which can significantly affect the efficiency of carrier injection into the channel and reduce the effective mobility. On the other hand, the contact resistance is too high, which may mask the performance of the device itself, resulting in non-ideal transistor performance. The existing main improvement method comprises the following steps:
(1) And optimizing the work function of the metal. Schottky theory indicates that modulating the metal work function can reduce the barrier height, and in general, high and low work function metals tend to form better contacts with p-type and n-type semiconductors, respectively. While this is theoretically true, it is more complex for two-dimensional materials. Due to the abrupt termination of the structure and the presence of foreign atoms at the interface, the properties of the material may differ greatly from the desired properties due to the presence of defects. In addition, the fermi level pinning effect makes the contact characteristics insensitive to the metal work function, making it difficult to achieve improved transistor performance through metal selection.
(2) And (5) contact doping. Another effective method is to dope the semiconductor of the contact region to achieve efficient charge injection. The Schottky barrier width is reduced by heavy doping such as doping diffusion or ion implantation, so that the current passing through the metal semiconductor contact is greatly improved by electron tunneling. However, this approach presents some difficulties because the doping techniques used for bulk semiconductors (e.g., ion implantation, etc.) are not compatible with two-dimensional materials.
(3) A heterojunction is formed. Yet another more efficient approach is to insert two-dimensional materials, such as graphene and BN, as tunneling layers in the contact area, forming van der waals heterostructures in the contact area. The method has the advantages that the smooth graphene can inhibit interface states and weaken the Fermi level pinning effect of a metal-two-dimensional material interface, the metal work function of Co and Ni can be reduced by about 2eV by the BN single-layer film, and the Fermi level and two-dimensional channel materials such as MoS can be made to be 2 The conduction band is close for better electron injection. However, the structure has high requirements on the process and is complex to prepare.
In summary, the prior art, although applied quite a lot, still has many problems. Due to the special properties of the two-dimensional material, the method (1) is subject to the Fermi pinning effect, so that the relation between the barrier height and the work function of the metal is weakened, and the contact performance cannot be well improved by optimizing the work function of the metal. The method (2) is also due to the characteristics of the two-dimensional material, so that the conventional semiconductor doping technology cannot be compatible with the two-dimensional material device. The method (3) can solve the fermi pinning effect to a certain extent, but the insertion of a layer of two-dimensional material (such as graphene, BN, etc.) complicates the preparation process, and the process of introducing the two-dimensional material layer may simultaneously introduce organic substances and other pollutants, which causes the degradation of the device performance.
Therefore, it is necessary to provide a new technique for improving the performance and enhancing the conduction by improving the contact resistance, so as to solve the above problems in the prior art.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides a two-dimensional material transistor structure and a method for manufacturing the same, in which a phase change of a two-dimensional material is induced by a Li intercalation method, the two-dimensional material in source and drain contact regions is induced from a semiconductor state 2H phase to form a metal state 1T phase, and meanwhile, the two-dimensional material in the 2H phase is used as a channel to enhance the conduction of a transistor device.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention provides a two-dimensional material transistor structure, comprising:
a semiconductor substrate;
a dielectric layer overlying the substrate;
the two-dimensional material layer is arranged on the surface of the dielectric layer and comprises a source contact area and a drain contact area which are respectively arranged at two ends of the two-dimensional material layer, and a channel area which is positioned between the source contact area and the drain contact area;
the two-dimensional material layer is located on the source contact area and the drain contact area, the portion of the two-dimensional material layer located on the source contact area and the portion of the two-dimensional material layer located on the channel area are provided with a 1T phase, the portion of the two-dimensional material layer located on the channel area is provided with a 2H phase, and a 2H-1T homojunction is formed between the two-dimensional material layer of the 2H phase and the two-dimensional material layer of the 1T phase on an interface.
Further, the two-dimensional material layer of the 1T phase has a metal phase transition structure induced to form after Li intercalation.
Further, the two-dimensional material layer material comprises MoS 2 Or WS 2 。
The invention also provides a preparation method of the two-dimensional material transistor structure, which comprises the following steps:
providing a semiconductor substrate;
forming a dielectric layer covering the substrate;
forming a two-dimensional material layer on the surface of the dielectric layer;
defining a channel region, a source contact region and a drain contact region on the two-dimensional material layer;
forming a protective layer covering the channel region, and exposing the source contact region and the drain contact region;
immersing the source contact region and the drain contact region in a reagent for Li intercalation, so that the two-dimensional material layers of the source contact region and the drain contact region are induced to form a 1T phase from a 2H phase through Li intercalation, and a 2H-1T homojunction is formed on an interface between the two-dimensional material layers of the 2H phase of the channel region;
performing rinsing after soaking;
and forming a metal electrode on the source contact region and the drain contact region.
Further, the forming a two-dimensional material layer on the surface of the dielectric layer includes: and transferring one to more than one two-dimensional material layer films onto the surface of the medium layer by adopting a mechanical stripping method.
Further, the two-dimensional material layer material comprises MoS 2 Or WS 2 。
Further, the forming a protection layer covering the channel region and exposing the source contact region and the drain contact region includes:
spin-coating a layer of positive photoresist on the surface of the dielectric layer to completely cover the two-dimensional material layer;
and exposing the source contact region and the drain contact region by using an electron beam lithography method, so that the photoresist on the source contact region and the drain contact region is removed, and the source contact region and the drain contact region are exposed.
Further, in N 2 And immersing the source contact region and the drain contact region in a reagent for Li intercalation in an atmosphere.
Further, the Li intercalation reagent comprises n-hexane solution of n-butyl lithium.
Further, the forming a metal electrode on the source contact region and the drain contact region includes:
depositing a metal on the protective layer and on the exposed source and drain contact regions;
and forming metal electrodes on the source contact area and the drain contact area by using a lift-off process.
According to the technical scheme, the conversion of the two-dimensional material film from the 2H semiconductor phase to the 1T metal phase is realized by utilizing the Li intercalation method, so that a two-dimensional transistor device with 1T contact in a source contact region and a drain contact region can be formed, and better performance is obtained by improving the contact. Compared with the traditional two-dimensional material device, the reduction of the Schottky barrier width can promote the generation of tunneling to obtain higher carrier injection efficiency, so that the performance of the transistor with the 2H phase-1T same-texture junction is greatly improved, and the transistor is particularly characterized by higher mobility, larger on-state current and smaller subthreshold swing.
Meanwhile, compared with other methods for regulating and controlling the Schottky barrier, such as optimizing the metal work function and the like, the method for realizing the metal phase change in the contact area of the original two-dimensional material film adopted by the invention is more visual and effective. With this approach, two phases of a two-dimensional material can coexist, forming stable boundaries on the same sheet, with atomic-scale phase boundaries and minimal defects that are easily introduced in conventional heterobonding or stacking methods.
The invention can promote the injection of carriers in a channel and the reduction of the width of a tunneling barrier between 2H phase-1T same-mass junctions by improving metal contact. This provides a promising approach for large scale integration of two-dimensional devices for high performance and high reproducibility nanoelectronic applications.
Drawings
FIG. 1 is a schematic diagram of a two-dimensional transistor structure according to a preferred embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating a two-dimensional transistor structure according to a preferred embodiment of the invention;
fig. 3-8 are schematic diagrams illustrating process steps for fabricating a two-dimensional material transistor structure according to the method of fig. 2 in accordance with a preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
The following provides a more detailed description of embodiments of the present invention, with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic diagram of a two-dimensional material transistor structure according to a preferred embodiment of the invention. As shown in fig. 1, the two-dimensional transistor structure of the present invention includes: a semiconductor substrate 10; a dielectric layer 11 overlying the upper surface of the substrate 10; a two-dimensional material layer 12 provided on the upper surface of the dielectric layer 11, and the like.
The two-dimensional material layer 12 includes a source contact region 121 and a drain contact region 123 respectively disposed on the illustrated left and right ends of the two-dimensional material layer 12, and a channel region 122 located between the source contact region 121 and the drain contact region 123.
Wherein, the part of the two-dimensional material layer 12 located in the source contact region 121 and the drain contact region 123 has a 1T phase, and the part located in the channel region 122 has a 2H phase, that is, the source contact region 121 and the drain contact region 123 are provided with the two-dimensional material layer 12 having the 1T phase, and the channel region 122 is provided with the two-dimensional material layer 12 having the 2H phase; and, a 2H-1T homojunction is formed at the interface of the 2H phase and the 1T phase between the portion of the two-dimensional material layer 12 of the 2H phase located at the channel region 122 and the portion of the two-dimensional material layer 12 of the 1T phase located at the source contact region 121 and the drain contact region 123.
Please refer to fig. 1. In a preferred embodiment, the substrate 10 may be a conventional semiconductor substrate, such as a silicon substrate 10. The dielectric layer 11 may be made of conventional dielectric material, such as SiO 2 And the like.
In a preferred embodiment, the two-dimensional material layer 12 may comprise MoS 2 Or WS 2 . But is not limited thereto.
The two-dimensional material layer 12 of the 1T phase located in the source contact region 121 and the drain contact region 123 has a metal phase transition structure induced after Li intercalation.
A metal electrode 14 (refer to fig. 8) may be further disposed on the source contact region 121 and the drain contact region 123.
The present invention utilizes Li intercalation to provide a two-dimensional transistor device having 1T contacts at the source and drain contact regions 121, 123. Compared with the traditional two-dimensional material device, the transistor with 2H phase-1T homojunction has the advantages that the reduction of the width of the tunneling barrier between homojunctions well reduces the contact resistance, so that the performance of the transistor is greatly improved, and the mobility is improved and the sub-threshold swing amplitude is reduced. Carrier injection in the channel and reduction of the tunnel barrier width between 2H phase-1T homojunctions can be facilitated by improving the metal contact. This provides a promising approach for large scale integration of two-dimensional devices for high performance and high reproducibility nanoelectronic applications.
The technology can be applied to devices such as field effect transistors based on two-dimensional materials and the like, and can obviously enhance the conduction performance of the field effect transistor devices.
The following describes a method for manufacturing a two-dimensional transistor structure according to the present invention in detail with reference to the accompanying drawings.
Please refer to fig. 2. The preparation method of the two-dimensional material transistor structure can be used for preparing the two-dimensional material transistor structure such as the transistor structure shown in FIG. 1, and can comprise the following steps:
step S1: a semiconductor substrate is provided.
Please refer to fig. 3. In a preferred embodiment, the substrate 10 may be a conventional semiconductor substrate, such as a silicon substrate 10.
Step S2: a dielectric layer is formed overlying the substrate.
Please refer to fig. 3. In a preferred embodiment, the dielectric layer 11 may be made of a conventional dielectric material, such as SiO 2 。
In one example, a conventional deposition process may be employed to form, for example, 300nm thick SiO on the upper surface of the silicon substrate 10 2 A dielectric layer 11. But is not limited thereto.
The silicon substrate 10 and SiO 2 The laminated structure of the dielectric layer 11 is not affected by the Li intercalation reagent, such as n-butyl lithium solution, and is very stable during the subsequent Li intercalation process.
And step S3: a two-dimensional material layer is formed on the surface of the dielectric layer.
Please refer to fig. 4. In a preferred embodiment, mechanical lift-off is used to transfer one to more than one two-dimensional material layers 12 with a certain area into SiO 2 On the surface of the dielectric layer 11.
To prepare WS having 1T contacts 2 Taking a back gate field effect transistor as an example (the method is also applicable to MoS) 2 Equal two-dimensional material devices), e.g., 5-10 layers of WS in 2H phase 2 Mechanical stripping of thin films to SiO of silicon substrate 10 2 Forming WS on the surface of the dielectric layer 11 2 A two-dimensional material layer 12.
And step S4: and defining a channel region and a source contact region and a drain contact region on the two-dimensional material layer.
Can be made on SiO by using a photolithography system according to design rules 2 The channel region 122, the source contact region 121 and the drain contact region 123 including the two-dimensional material layer 12 are defined on the surface of the dielectric layer 11.
Step S5: and forming a protective layer covering the channel region and exposing the source contact region and the drain contact region.
Please refer to fig. 5. In a preferred embodiment, it may be on the entire SiO 2 A layer of positive photoresist 13, such as polymethyl methacrylate (PMMA) photoresist 13, is spin-coated on the surface of the dielectric layer 11, and the two-dimensional material layer 12 is completely covered to serve as a protection layer.
PMMA is an effective n-butyllithium solution-resistant material that is a good protective layer during subsequent processing to maintain stability of the two-dimensional material layer 12 in the channel region 122 portion during Li intercalation.
Please refer to fig. 6. In a preferred embodiment, the source contact region 121 and the drain contact region 123 are exposed by electron beam lithography, such that a portion of the photoresist 13 covering the source contact region 121 and the drain contact region 123 is removed, and a contact region window 131 is formed on the photoresist 13 to expose the source contact region 121 and the drain contact region 123 on the two-dimensional material layer 12 for subsequent immersion in the Li intercalation reagent.
The area of the contact region window 131 may be larger than the source contact region 121 and the drain contact region123, may include the subsequent formation of metal electrode 14 and may be located at WS 2 The two-dimensional material layer 12 has a partial region other than the source contact region 121 and the drain contact region 123.
WS exposed on source contact region 121 and drain contact region 123 in contact region window 131 2 The two-dimensional material layer 12, since it has not been subjected to Li intercalation treatment, has the material property of WS having 2H phase 2 Two-dimensional material layer 12 (2H-WS) 2 )。
Step S6: and soaking the source contact region and the drain contact region in a reagent for Li intercalation, so that the two-dimensional material layers of the source contact region and the drain contact region are induced to form a 1T phase from a 2H phase through Li intercalation, and form a 2H-1T homojunction with the two-dimensional material layer of the 2H phase of the channel region on an interface.
Please refer to fig. 7. In a preferred embodiment, the system can be filled with N 2 In the glove box of the atmosphere, the above-described formed device structure including the source contact region 121 and the drain contact region 123 exposed in the contact region window 131 on the polymethyl methacrylate (PMMA) resist 13 as a protective layer was entirely immersed in the agent for Li intercalation for immersion.
In a preferred embodiment, the Li intercalation reagent may include a solution of n-butyl lithium in n-hexane.
In one example, the entire substrate 10 and its upper device structure may be immersed in 20mL of a 1.6M solution of n-butyllithium in n-hexane and soaked for 48h. But is not limited thereto.
In the step, the two-dimensional material layer 12 of the 2H phase exposed on the source contact area 121 and the drain contact area 123 of the contact area window 131 is soaked and contacted with the n-butyl lithium, so that a Li intercalation process can be realized on the two-dimensional material of the source contact area 121 and the drain contact area 123, the thin film of the two-dimensional material layer 12 is induced to be converted from the 2H semiconductor phase to the 1T metal phase, and the WS with the 1T metal phase is formed 2 Two-dimensional material layer 12 (1T-WS) 2 ) Source contact region 121 and drain contact region 123, while WS of channel region 122 is protected by photoresist 13 2 The two-dimensional material still maintains the 2H semiconductor phase and can form a 2H phase-1T homojunction at the interface of the 2H semiconductor phase and the 1T metal phase.
Step S7: rinsing after soaking is performed.
In a preferred embodiment, the device after soaking can be washed, and the organic residue and the excess lithium ions during soaking can be washed away by hexane and deionized water, respectively, so as to prevent the residual impurities from affecting the electrical performance test of the device. This procedure is to form a 1T-WS 2 Source contact regions 121 and drain contact regions 123.
The two-dimensional material layer 12 film is immersed into n-butyllithium-n-hexane solution for soaking, so that a Li intercalation process is realized, and the two-dimensional material film is induced to be converted from a 2H semiconductor phase to a 1T metal phase, so that contact is improved, and the performance of a transistor is further improved.
Step S8: and forming a metal electrode on the source contact region and the drain contact region.
Please refer to fig. 8. In a preferred embodiment, electrode metal may be deposited entirely on the protective layer of photoresist 13 and on the source and drain contact regions 121 and 123 exposed through the contact region windows 131; then, a lift-off process may be employed to form the metal electrode 14 on the source contact region 121 and the drain contact region 123.
In one example, a PVD process may be used to integrally deposit 10nm thick Ti and 70nm thick Au (not limited thereto) as electrode metals on the surface of the device obtained above, and a lift-off process may be performed to strip the photoresist 13 and the metal Ti and Au thereon from the substrate 10, which may leave the electrode metal pattern on the contact region window 131 area, thereby forming the metal electrode 14 on the source and drain contact regions 121 and 123.
Finally, the obtained device can be subjected to structural characterization, electrical test and the like.
Devices with 1T contacts exhibit higher mobility, larger on-current and smaller sub-threshold swing than devices with 2H contacts.
For MoS, for example 2 Two-dimensional material, the host lattice MoS of which is subjected to Li intercalation by coordination bonds of Mo atoms 2 Undergoes a first-order phase change from a triangular prism structure (2H-MoS) 2 ) Changed into octahedral structure (1T-MoS) 2 ). Induced formation of metalThe phase 1T can serve as an excellent contact area while the phase 2H serves as a channel to enhance the conduction of the transistor device.
The 2H-1T homojunction is formed by the method, the width of a tunneling potential barrier between homojunctions is reduced, and the contact resistance is well reduced. In addition, the method is compatible with two-dimensional material devices except MoS 2 In addition, the method can also be applied to other two-dimensional materials (such as WS) 2 Etc.), which provides a promising approach for large-scale integration of two-dimensional devices for high-performance and high-reproducibility nanoelectronic applications.
The method of the invention has simple operation and only adds one step of the process of using a chemical method to carry out Li intercalation.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to the embodiments. However, it is to be understood that such modifications and variations fall within the scope and spirit of the present invention as set forth in the appended claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A two-dimensional material transistor structure, comprising:
a semiconductor substrate;
a dielectric layer overlying the substrate;
the two-dimensional material layer is arranged on the surface of the dielectric layer and comprises a source contact area and a drain contact area which are respectively arranged at two ends of the two-dimensional material layer, and a channel area which is positioned between the source contact area and the drain contact area;
and the two-dimensional material layer positioned on the source contact region and the drain contact region is provided with a 1T phase, the part positioned on the channel region is provided with a 2H phase, and a 2H-1T homojunction is formed between the two-dimensional material layer of the 2H phase and the two-dimensional material layer of the 1T phase on an interface.
2. The two-dimensional material transistor structure of claim 1, wherein the two-dimensional material layer of the 1T phase has a metallic phase transition structure induced to form after Li intercalation.
3. The two-dimensional material transistor structure of claim 1, wherein the two-dimensional material layer material comprises MoS 2 Or WS 2 。
4. A method for preparing a two-dimensional material transistor structure, comprising:
providing a semiconductor substrate;
forming a dielectric layer covering the substrate;
forming a two-dimensional material layer on the surface of the dielectric layer;
defining a channel region, a source contact region and a drain contact region on the two-dimensional material layer;
forming a protective layer covering the channel region, and exposing the source contact region and the drain contact region;
immersing the source contact region and the drain contact region in a reagent for Li intercalation, so that the two-dimensional material layers of the source contact region and the drain contact region are induced to form a 1T phase from a 2H phase through Li intercalation, and a 2H-1T homojunction is formed on an interface between the two-dimensional material layers of the 2H phase of the channel region;
performing rinsing after soaking;
and forming a metal electrode on the source contact region and the drain contact region.
5. The method for manufacturing a two-dimensional material transistor structure according to claim 4, wherein the forming of the two-dimensional material layer on the surface of the dielectric layer comprises: and transferring one to more than one two-dimensional material layer films onto the surface of the medium layer by adopting a mechanical stripping method.
6. The method of claim 4, wherein the two-dimensional material layer comprises MoS 2 Or WS 2 。
7. The method of claim 4, wherein forming a protective layer overlying the channel region and exposing the source contact region and the drain contact region comprises:
spin-coating a layer of positive photoresist on the surface of the dielectric layer, and completely covering the two-dimensional material layer;
and exposing the source contact region and the drain contact region by using an electron beam lithography method, so that the photoresist on the source contact region and the drain contact region is removed to expose the source contact region and the drain contact region.
8. The method of claim 4, wherein N is the number of atoms in the two-dimensional material transistor structure 2 And immersing the source contact region and the drain contact region in a reagent for Li intercalation in an atmosphere.
9. The method of claim 4, wherein the Li intercalation reagent comprises n-hexane solution of n-butyllithium.
10. The method of claim 4, wherein forming a metal electrode on the source contact region and the drain contact region comprises:
depositing a metal on the protective layer and on the exposed source and drain contact regions;
and forming metal electrodes on the source contact area and the drain contact area by using a lift-off process.
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