CN115332309A - Dual silicon-on-insulator device and method of fabricating the same - Google Patents

Dual silicon-on-insulator device and method of fabricating the same Download PDF

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CN115332309A
CN115332309A CN202110504675.XA CN202110504675A CN115332309A CN 115332309 A CN115332309 A CN 115332309A CN 202110504675 A CN202110504675 A CN 202110504675A CN 115332309 A CN115332309 A CN 115332309A
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back gate
region
semiconductor layer
substrate
layer
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梁志彬
张松
金炎
王德进
李小红
刘群
过夏雨
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CSMC Technologies Fab2 Co Ltd
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Priority to PCT/CN2022/073107 priority patent/WO2022237231A1/en
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The invention relates to a double silicon-on-insulator device and a manufacturing method thereof, wherein the double silicon-on-insulator device comprises: a substrate; the second insulating buried layer is arranged on the substrate; the second semiconductor layer is arranged on the second insulating buried layer; a first insulating buried layer provided on the second semiconductor layer; the first semiconductor layer is arranged on the first insulating buried layer and comprises an active region; the grid electrode is arranged on the first semiconductor layer; the double silicon-on-insulator device is provided with a first back gate recessed region recessed to the second semiconductor layer and a second back gate recessed region recessed to the substrate; in the first back gate depression region, the second semiconductor layer is led out from the top to serve as a first back gate end; and in the second back gate sunken region, the substrate is led out through the top to serve as a second back gate terminal. The device has stronger design flexibility, and different back bias voltages can be applied according to design requirements so as to achieve the purpose of optimizing the device.

Description

Dual silicon-on-insulator device and method of fabricating the same
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a double-silicon-on-insulator device and a manufacturing method thereof.
Background
A Double Silicon On Insulator (DSOI) device is formed by adding a Silicon dioxide layer (SiO) On the basis of a Silicon On Insulator (SOI) 2 ) And a single crystal silicon layer (Si), which inherits the excellent capability of SOI for resisting single event effect and the like, and has larger improvement in the aspects of back gate effect, total radiation dose effect, electrode crosstalk effect and the like than the bulk silicon process and the SOI process.
Conventional DSOI devices can only be biased by the substrate, with the effect of modulating the device by applying a bias voltage being limited.
Disclosure of Invention
Based on this, there is a need for a dual silicon-on-insulator device with more flexibility in adjusting the bias voltage.
A dual silicon-on-insulator device comprising: a substrate; the second insulating buried layer is arranged on the substrate; the second semiconductor layer is arranged on the second insulating buried layer; a first insulating buried layer provided on the second semiconductor layer; the first semiconductor layer is arranged on the first insulating buried layer and comprises an active region; the grid electrode is arranged on the first semiconductor layer; the double silicon-on-insulator device is provided with a first back gate recessed region recessed to the second semiconductor layer and a second back gate recessed region recessed to the substrate; in the first back gate depression region, the second semiconductor layer is led out from the top to serve as a first back gate end; and in the second back gate recess region, the substrate is led out from the top to serve as a second back gate terminal.
In one embodiment, the shallow trench isolation structure is further included, and the shallow trench isolation structure is formed around the second back gate recessed region.
In one embodiment, the semiconductor device further comprises an interlayer dielectric, and the interlayer dielectric is filled in the first back gate recess region and the second back gate recess region.
In one embodiment, the active region comprises a source region and a drain region, the double silicon-on-insulator device comprises a metal oxide semiconductor field effect transistor, and the gate, the source region and the drain region are the composition structures of the metal oxide semiconductor field effect transistor.
In one embodiment, the double silicon-on-insulator device further comprises a source contact hole on the source region, a drain contact hole on the drain region, and a gate contact hole on the gate.
In one embodiment, the second semiconductor layer and the substrate are led out through respective contact holes to be respectively used as a first back gate end and a second back gate end in sequence.
In one embodiment, the gate comprises a polysilicon gate.
In one embodiment, the double silicon-on-insulator device further comprises a gate dielectric layer located between the polysilicon gate and the first semiconductor layer.
In one embodiment, the double silicon-on-insulator device further comprises a side wall structure located on the side surface of the gate.
In one embodiment, the gate dielectric layer comprises silicon dioxide.
In one embodiment, the first buried insulating layer is a buried oxide layer
In one embodiment, the second buried insulating layer is a buried oxide layer
In one embodiment, the substrate is a silicon layer.
In one embodiment, the first semiconductor layer is a silicon layer.
In one embodiment, the second semiconductor layer is a silicon layer.
In one embodiment, each contact hole is filled with a conductive material.
In one embodiment, the conductive material comprises a metal and/or an alloy.
In one embodiment, each contact hole forms a metal silicide at the bottom where it contacts the underlying structure.
According to the double silicon-on-insulator device, the two back gate ends, namely the first back gate end and the second back gate end, are arranged, and the second back gate recessed region is recessed into the substrate, so that the second semiconductor layer is cut off in the second back gate recessed region to form an independent region, and therefore the back gate voltage of the device on the corresponding independent region can be independently adjusted by applying voltage to the first back gate end, and/or the back gate voltages of a plurality of devices can be adjusted by applying voltage to the second back gate end. Therefore, the design flexibility of the device is stronger, and different back bias voltages can be applied according to the design requirements so as to achieve the purpose of optimizing the device.
It is also desirable to provide a method of fabricating a dual silicon-on-insulator device.
A method of fabricating a dual silicon-on-insulator device, comprising: obtaining a substrate, wherein the substrate comprises a substrate, a second insulating buried layer, a second semiconductor layer, a first insulating buried layer and a first semiconductor layer which are sequentially stacked; patterning the first semiconductor layer to form an active region; forming a gate electrode on the active region; patterning an upper structure of the second semiconductor layer to form a first back gate recess region, wherein the bottom of the first back gate recess region exposes a part of the second semiconductor layer; (ii) a Patterning an upper structure of the substrate to form a second back gate recess region, wherein the bottom of the second back gate recess region exposes a part of the substrate; and leading out the top of the second semiconductor layer at the position of the first back gate recessed region as a first back gate end, and leading out the top of the substrate at the position of the second back gate recessed region as a second back gate end.
In one embodiment, after the step of patterning the first semiconductor layer to form an active region and before the step of forming a gate on the active region, a step of forming a shallow trench isolation structure is further included.
In one embodiment, the step of forming a gate on the active region includes: forming a gate dielectric layer on the active region; and forming a polysilicon gate on the gate dielectric layer.
In one embodiment, before the step of removing the upper structure of the second semiconductor layer in the partial region, a step of forming a sidewall structure on a side surface of the gate electrode is further included.
In one embodiment, after the step of patterning the first semiconductor layer to form the active region and before the step of forming the shallow trench isolation structure, a step of patterning the first buried insulating layer and the second semiconductor layer is further included.
In one embodiment, the step of patterning the upper structure of the second semiconductor layer includes photolithography and etching of the shallow trench isolation structure and the first buried insulating layer of the first back gate recessed region; the step of patterning the upper structure of the substrate comprises photoetching and etching the shallow trench isolation structure and the second insulating buried layer of the second back gate recessed region; the step of patterning the first insulating buried layer and the second semiconductor layer comprises photoetching and etching the first insulating buried layer and the second semiconductor layer, the orthographic projection of the etched and removed region on the substrate is a first region, and the orthographic projection of the etched and removed region of the second back gate recessed region and the orthographic projection of the etched and removed region of the second insulating buried layer on the substrate are located in the first region.
In one embodiment, the step of leading out the top of the second semiconductor layer at the position of the first back gate recessed region as a first back gate terminal comprises the following steps: forming a first back gate contact hole over the second semiconductor layer at the position of the first back gate recess region, thereby leading out the second semiconductor layer; the step of leading out the top of the substrate at the position of the second back gate recess region as a second back gate end comprises the following steps: and forming a second back gate contact hole above the substrate at the position of the second back gate sunken region, so as to lead out the substrate.
In one embodiment, the step of leading out the top of the second semiconductor layer at the position of the first back gate recess region as a first back gate end comprises: carrying out metallization processing on the top of the second semiconductor layer at the position of the first back gate recessed region to form metal silicide; forming the first back gate contact hole by etching, and filling a conductive material in the first back gate contact hole; the step of leading out the top of the substrate at the position of the second back gate recess region as a second back gate end comprises the following steps: carrying out metallization processing on the top of the substrate at the position of the second back gate recessed region to form metal silicide; and forming the second back gate contact hole by etching, and filling a conductive material in the second back gate contact hole.
In one embodiment, the step of patterning the first semiconductor layer to form an active region includes: forming a pad oxide layer on the first semiconductor layer; forming a hard mask layer on the pad oxide layer; and photoetching the hard mask layer, and etching the hard mask layer, the pad oxide layer and the first semiconductor layer to form the active region.
In one embodiment, the hard mask layer is a silicon nitride layer.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the best modes of presently understanding these inventions.
FIG. 1 is a schematic cross-sectional view of a double silicon-on-insulator device in one embodiment;
FIG. 2 is a flow chart of a method of fabricating a dual silicon-on-insulator device in one embodiment;
figures 3a-3d are schematic cross-sectional views of a dual silicon-on-insulator device in the process of being fabricated using the fabrication method shown in figure 2, according to one embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
FIG. 1 is a schematic cross-sectional view of a double silicon-on-insulator device in one embodiment. The dual soi device includes, from bottom to top, a substrate 110, a second buried insulating layer 124, a second semiconductor layer 134, a first buried insulating layer 122, a first semiconductor layer 132, and a gate. The second buried insulating layer 124 is provided on the substrate 110. The second semiconductor layer 134 is disposed on the second buried insulating layer 124. The first buried insulating layer 122 is disposed on the second semiconductor layer 134. The first semiconductor layer 132 is disposed on the first buried insulating layer 122. An active region (not labeled in fig. 1) is disposed in the first semiconductor layer 132. The gate is disposed on the first semiconductor layer 132.
The above-described double silicon-on-insulator device is formed with the first back gate recess region 181 recessed to the second semiconductor layer 134, and the second back gate recess region 183 recessed to the substrate 110. In the first back gate recess region 181, the second semiconductor layer 134 is led out through the top as a first back gate terminal. In the second back gate recess region 183, the substrate 110 is drawn out through the top as a second back gate terminal.
In the above-mentioned double silicon-on-insulator device, two back gate terminals, namely the first back gate terminal and the second back gate terminal, are provided, and since the second back gate recess 183 is recessed into the substrate 110, the second semiconductor layer 134 is cut off at the second back gate recess 183 to form an independent region, so that the back gate voltage of the device on the corresponding independent region can be independently adjusted by applying a voltage to the first back gate terminal, and/or the back gate voltages of a plurality of devices can be adjusted by applying a voltage to the second back gate terminal (because the plurality of devices share the substrate 110). Therefore, the design flexibility of the device is stronger, and different back bias voltages can be applied according to the design requirements so as to achieve the purpose of optimizing the device.
In the embodiment shown in fig. 1, the gate comprises a polysilicon gate 142. A gate dielectric layer 144 is also disposed between the polysilicon gate 142 and the first semiconductor layer 132. The gate dielectric layer 144 may be silicon dioxide. The side of the gate is further provided with a sidewall structure 146.
In one embodiment of the present application, the dual silicon-on-insulator device comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the active region in the first semiconductor layer 132 comprises a source region and a drain region, and the gate, the source region and the drain region are all constituent structures of the MOSFET.
In one embodiment of the present application, the substrate 110, the first semiconductor layer 132 and the second semiconductor layer 134 are all silicon layers. The first buried insulating layer 122 and the second buried insulating layer 124 are buried oxide layers, and may be made of silicon dioxide.
In the embodiment shown in fig. 1, the double silicon-on-insulator device further comprises a shallow trench isolation structure 150. The shallow trench isolation structure 150 is formed around the second back gate recess region 183. As described above, the second semiconductor layer 134 is cut to form the isolated region, a part of the shallow trench isolation structure 150 is formed between one side of the isolated region and the second back gate recess region 183, and the other side of the isolated region is also provided with the shallow trench isolation structure 150 (thereby cutting the other side of the isolated region).
In the embodiment shown in fig. 1, the dual silicon-on-insulator device further includes an interlayer dielectric (ILD) 160 on the first semiconductor layer 132 and on the gate. The interlayer dielectric 160 is filled in both the first back gate recess 181 and the second back gate recess 183.
In the embodiment shown in fig. 1, the top of the second semiconductor layer 134 is drawn out through the first back gate contact hole 171 as a first back gate terminal, and the top of the substrate 110 is drawn out through the second back gate contact hole 173 as a second back gate terminal. The source, drain and gate regions are also brought out through source contact opening 175, drain contact opening 177 and gate contact opening 179, respectively. Each contact hole is filled with a conductive material, and the conductive material can be metal and/or alloy. Further, each contact hole forms a metal silicide 152 at the bottom where it contacts the underlying structure.
In one embodiment of the present application, the second buried insulating layer 124 has a thickness of
Figure BDA0003057891890000071
A second semiconductor layer134 have a thickness of
Figure BDA0003057891890000072
The first buried insulating layer 122 has a thickness of
Figure BDA0003057891890000073
The first semiconductor layer 132 has a thickness of
Figure BDA0003057891890000074
The polysilicon gate 142 has a thickness of
Figure BDA0003057891890000075
The present application accordingly provides a method of fabricating a dual silicon-on-insulator device that may be used to fabricate the dual silicon-on-insulator device described in the corresponding embodiments above. FIG. 2 is a flow chart of a method of fabricating a dual silicon-on-insulator device in one embodiment, including the steps of:
s210, obtaining a substrate.
In the embodiment shown in fig. 3a, the base includes a substrate 110, a second buried insulating layer 124, a second semiconductor layer 134, a first buried insulating layer 122, and a first semiconductor layer 132 stacked in sequence.
S220, patterning the first semiconductor layer to form an active region.
Portions of the first semiconductor layer 132 may be removed by photolithography and etching processes (the removed locations may form shallow trench isolation structures in subsequent processes).
In one embodiment of the present application, step S220 includes: a pad oxide layer 212 is formed on the first semiconductor layer 132. A hard mask layer 214 is then formed on the pad oxide layer 212. Next, a photoresist pattern 222 is formed on the hard mask layer 214 by photolithography, and the hard mask layer 214, the pad oxide layer 212 and the first semiconductor layer 132 are etched using the photoresist pattern 222 as an etching mask layer to form an active region. The cross-section of the device after step S220 is completed is shown in fig. 3b. In one embodiment of the present application, the hard mask layer 214 is a silicon nitride layer.
And S230, forming a grid electrode on the active region.
In one embodiment of the present application, the step S230 further includes a step of patterning the first buried insulating layer 122 and the second semiconductor layer 134. Specifically, the first buried insulating layer 122 and the second semiconductor layer 134 may be patterned and etched to form a plurality of independent regions separated from each other in the second semiconductor layer 134, and each independent region is configured with a first back gate terminal in a subsequent process.
In one embodiment of the present application, after patterning the first buried insulating layer 122 and the second semiconductor layer 134, the shallow trench isolation structure 150 may also be formed. Specifically, the shallow trench isolation structure 150 is formed in a region outside the active region, see fig. 3c.
In one embodiment of the present application, step S230 includes forming a gate dielectric layer 144 on the active region, and forming a polysilicon gate 142 on the gate dielectric layer 144. The gate dielectric layer 144 may be formed by a thermal oxidation or deposition process. The gate polysilicon 142 may be formed by depositing polysilicon on the gate dielectric layer 144. As shown in fig. 3c, the polysilicon gate 142 and the gate dielectric layer 144 may be etched by using the photoresist 224 as an etching mask after the photoresist is formed by photolithography, so as to etch the polysilicon gate 142 and the gate dielectric layer 144.
The hard mask layer 214 and the pad oxide layer 212 are removed prior to forming the gate.
In one embodiment of the present application, the step of forming a sidewall structure 146 on the side of the gate is further included after etching the polysilicon gate 142 and the gate dielectric layer 144.
In one embodiment of the present application, after forming the sidewall structures 146, source and drain regions may be formed in the active region by an ion implantation process. In one embodiment of the present application, a dual silicon-on-insulator device comprises a MOSFET, and the gate, source region and drain region are all constituent structures of the MOSFET.
And S240, forming a first back gate recess region.
The upper structure of the second semiconductor layer 134 is patterned to form a first back gate recess 181, and the bottom of the first back gate recess 181 exposes the second semiconductor layer 134 at a corresponding position. Specifically, the first back gate recess region 181 may be formed by photolithography and etching of the shallow trench isolation structure 150 and the first buried insulating layer 122, as shown in fig. 3d.
And S250, forming a second back gate recess region.
The upper structure of the substrate 110 is patterned to form a second back gate recess 183, and the bottom of the second back gate recess 183 exposes the substrate 100 at the corresponding position. Specifically, the second back gate recess region 183 may be formed by photolithography and etching of the shallow trench isolation structure 150 and the second buried insulating layer 124. Since the partial regions of the first buried insulating layer 122 and the second semiconductor layer 134 have been removed in the foregoing step of patterning the first buried insulating layer 122 and the second semiconductor layer 134, the etching of step S250 is to continue etching the second buried insulating layer 124 downward after the shallow trench isolation structure 150 is etched through the removed regions.
And S260, leading out a first back grid end and a second back grid end.
The top of the second semiconductor layer 134 at the position of the first back gate recess region 181 is led out as a first back gate terminal, and the top of the substrate 110 at the position of the second back gate recess region 183 is led out as a second back gate terminal.
In one embodiment of the present application, the second semiconductor layer 134 is extracted by forming the first back gate contact hole 171 above the second semiconductor layer 134 at the position of the first back gate recess region 181; the first back gate contact hole 171 is filled with a conductive material. By forming the second back gate contact hole 173 above the substrate 110 at the position of the second back gate recess region 183, the substrate 110 is taken out; the second back gate contact hole 173 is filled with a conductive material. Fig. 1 may be referred to as a device structure after step S260 is completed.
In one embodiment of the present application, the step of drawing out the first back gate terminal and the second back gate terminal includes: the top of the second semiconductor layer 134 at the location of the first back gate recess 181 and the top of the substrate 110 at the location of the second back gate recess 183 are metallized to form a metal silicide 152. An interlayer dielectric 160 is then deposited over the front side of the device. The interlayer dielectric 160 is then etched to form a first back gate contact hole 171 and a second back gate contact hole 173. Finally, the first back gate contact hole 171 and the second back gate contact hole 173 are filled with a conductive material.
According to the double silicon-on-insulator device formed by the manufacturing method, the first back gate end and the second back gate end are arranged, and the recess region of the second back gate is recessed into the substrate, so that the second semiconductor layer is cut off in the recess region of the second back gate to form an independent region, and the back gate voltage of the device on the corresponding independent region can be independently adjusted by applying voltage to the first back gate end, and/or the back gate voltages of a plurality of devices can be adjusted by applying voltage to the second back gate end. Therefore, the design flexibility of the device is stronger, and different back bias voltages can be applied according to the design requirements so as to achieve the purpose of optimizing the device.
It should be understood that, although the steps in the flowcharts of the present application are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowchart of the present application may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or the stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or the stages in other steps.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A dual silicon-on-insulator device, comprising:
a substrate;
the second insulating buried layer is arranged on the substrate;
the second semiconductor layer is arranged on the second insulating buried layer;
a first buried insulating layer provided on the second semiconductor layer;
the first semiconductor layer is arranged on the first insulating buried layer and comprises an active region;
the grid electrode is arranged on the first semiconductor layer;
the double silicon-on-insulator device is provided with a first back gate recessed region recessed to the second semiconductor layer and a second back gate recessed region recessed to the substrate; in the first back gate depression region, the second semiconductor layer is led out from the top to serve as a first back gate end; and in the second back gate recess region, the substrate is led out from the top to serve as a second back gate terminal.
2. The double silicon-on-insulator device of claim 1, further comprising a shallow trench isolation structure formed around the second back gate recessed region.
3. The dual silicon-on-insulator device of claim 1, further comprising an interlayer dielectric, the interlayer dielectric filled within the first back gate recess and filled within the second back gate recess.
4. The dual silicon-on-insulator device of claim 1, wherein the active region comprises a source region and a drain region, the dual silicon-on-insulator device comprises a metal oxide semiconductor field effect transistor, and the gate, source region and drain region are constituent structures of the metal oxide semiconductor field effect transistor.
5. The double silicon-on-insulator device of claim 1, wherein the second semiconductor layer and the substrate are led out through respective contact holes to serve as a first back gate terminal and a second back gate terminal, respectively, in sequence.
6. A method of fabricating a dual silicon-on-insulator device, comprising:
obtaining a substrate, wherein the substrate comprises a substrate, a second insulating buried layer, a second semiconductor layer, a first insulating buried layer and a first semiconductor layer which are sequentially stacked;
patterning the first semiconductor layer to form an active region;
forming a gate electrode on the active region;
patterning an upper structure of the second semiconductor layer to form a first back gate depressed region, wherein the bottom of the first back gate depressed region exposes a part of the second semiconductor layer;
patterning an upper structure of the substrate to form a second back gate recess region, wherein the bottom of the second back gate recess region exposes a part of the substrate;
and leading out the top of the second semiconductor layer at the position of the first back gate recessed region as a first back gate end, and leading out the top of the substrate at the position of the second back gate recessed region as a second back gate end.
7. The method of claim 6, further comprising a step of forming a shallow trench isolation structure after the step of patterning the first semiconductor layer to form an active region and before the step of forming a gate on the active region.
8. The method of claim 7, further comprising patterning the first buried insulating layer and the second semiconductor layer after the step of patterning the first semiconductor layer to form the active region and before the step of forming the shallow trench isolation structure.
9. The method according to claim 8, wherein the step of patterning the upper structure of the second semiconductor layer comprises photolithography and etching of the shallow trench isolation structure of the first back gate recessed region and the first buried insulating layer of the first back gate recessed region; the step of patterning the upper structure of the substrate comprises photoetching and etching the shallow trench isolation structure and the second insulating buried layer of the second back gate recessed region; the step of patterning the first insulating buried layer and the second semiconductor layer comprises photoetching and etching the first insulating buried layer and the second semiconductor layer, the orthographic projection of the etched and removed region on the substrate is a first region, and the orthographic projection of the etched and removed region on the substrate of the shallow slot isolation structure of the second back gate sunken region and the step of etching the second insulating buried layer is located in the first region.
10. The method according to claim 6, wherein the step of leading out the top of the second semiconductor layer at the position of the first back gate recess region as a first back gate terminal comprises the steps of: forming a first back gate contact hole over the second semiconductor layer at the position of the first back gate recess region, thereby leading out the second semiconductor layer;
the step of leading out the top of the substrate at the position of the second back gate recess region as a second back gate end comprises the following steps: and forming a second back gate contact hole above the substrate at the position of the second back gate sunken region, so as to lead out the substrate.
CN202110504675.XA 2021-05-10 2021-05-10 Dual silicon-on-insulator device and method of fabricating the same Pending CN115332309A (en)

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