CN115293080A - Chip debugging system based on trace file - Google Patents
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Abstract
The invention relates to a chip debugging system based on a trace file, which realizes the step S1 and is based on a DUT H Acquire each IT k Corresponding description information; step S2, from DUT H Transferring each IT k Corresponding valid bus interface data records; step S3, slave ITC Ln Corresponding all IT k Extracting an excitation signal from the original tracking file and sending the excitation signal to a corresponding simulation model; step S4, transferring and storing ITC Ln Each IT in k Corresponding first effective bus interface data record, generating first tracking file, and transferring ITC Ln Each IT in k Corresponding second effective bus interface data records are recorded, and a second tracking file is generated; step S5, based on DUT Ln All IT in k Corresponding first trace file and second trace file to DUT Ln Trace and debug, and quickly and accurately position DUT Ln The problem in (1). The invention improves the efficiency of verifying and debugging the chip.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a chip debugging system based on a trace file.
Background
The chip is usually designed in multiple levels, the scale is huge, the chip design and the chip verification are important stages in the research and development process, and in the chip design and the chip verification process, chip design problem points need to be tracked and positioned for chip debugging (Debug). When a problem is found in a Design Under Test (DUT) of a High Level (High Level), the DUT Design of a low Level included in the High Level needs to be further verified, and a problem point needs to be located. Because the verification is usually performed in a mode of generating random constraint excitation by a verification platform in the chip verification process, the same excitation verification low-level design cannot be repeatedly adopted, the problem of low-level design is difficult to quickly and accurately position, and the chip debugging efficiency is low.
Disclosure of Invention
The invention aims to provide a chip debugging system based on a trace file, which can debug a low-level design-to-be-tested DUT (device under test) with the same stimulus based on the trace file of a high-level design-to-be-tested DUT dump (dump), thereby quickly and accurately positioning problem points and improving the efficiency of chip verification and debugging.
The invention provides a chip debugging system based on trace files, which comprises a bus interface configuration file and a high-level design-to-be-tested DUT (device under test) H 、DUT H Corresponding N low-level designs under test { DUT L1 ,DUT L2 ,…,DUT Ln ,…,DUT LN DUT, memory storing a computer program, and processor H ={U H1 ,U H2 ,…,U HM }，U H1 ,U H2 ,…,U HM Is a DUT H M is a DUT H Number of constituent modules, U H1 ,U H2 ,…,U HM Setting a hierarchy; { DUT L1 ,DUT L2 ,…, DUT Ln ,…,DUT LN Is { U } H1 ,U H2 ,…,U HM A subset of (a) }; DUT Ln Is a DUT H Corresponding nth low-level design to be tested, wherein the value range of N is 1 to N, and the DUT Ln ={U L1 n ,U L2 n ,…,U Lf(n) n }, U L1 n ,U L2 n ,…,U Lf(n) n Is a DUT Ln F (n) is a DUT Ln Including the number of constituent modules, U L1 n ,U L2 n ,…,U Lf(n) n Setting a hierarchy; { U L1 n ,U L2 n ,…,U Lf(n) n Is { U } H1 ,U H2 ,…,U HM A subset of { C }; u shape i And U j For two constituent modules having an interconnecting relationship, U i And U j All belong to { U H1 ,U H2 ,…,U HM Either all belong to { U } L1 n ,U L2 n ,…,U Lf(n) n }；U i And U j Are interconnected by at least one bus interface, U i And U j The brother modules or the father and son modules are interconnected through at least one bus interface, and the brother modules or the father and son modules have an interconnection relationship; the bus interface configuration file comprises { ITC L1 ,ITC L2 ,…, ITC Ln ,…,ITC LN }，ITC Ln Is a DUT Ln Target bus interface list of, each ITC Ln Including at least one target bus interface IT k The value range of K is 1 to K, and K is the total number of the target bus interfaces;
the processor, when executing the computer program, implements the steps of:
step S1, based on DUT H Acquire each IT k Corresponding description information including IT k Corresponding component module identification, bus interface signal and IT k The bus interface identifier is generated based on the hierarchy information corresponding to the bus interface and the name of the bus interface instance, and the signal description information comprises a signal direction;
step S2, operating the DUT H From DUT H Transferring each IT k A corresponding active bus interface data record comprising IT k The signal value, absolute time and/or clock cycle number corresponding to each signal in the signal table is based on IT k Generating an original tracking file by recording corresponding description information and effective bus interface data;
step S3, according to the signal direction and the signal value, the slave ITC Ln Corresponding all IT k Extracts the excitation signals from the original trace file and sends the corresponding excitation signals to the DUT according to the absolute time and/or the clock cycle sequence number in a preset sequence Ln And DUT Ln A corresponding simulation model;
step S4, slave DUT Ln Transfer memory ITC Ln Each IT in k Corresponding first active bus interface data records, unloading ITC from corresponding simulation model Ln Each IT in k Corresponding second valid bus interface data record based on IT k Generating a first trace file based on the IT using the corresponding description information and the first valid bus interface data record k Generating a second trace file by the corresponding description information and the second effective bus interface data record;
step S5 based on DUT Ln All IT in k Corresponding first trace file and second trace file to DUT Ln Trace debug to locate a DUT Ln The problem in (1).
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the chip debugging system based on the trace file provided by the invention can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:
the invention can debug the low-level DUT to be tested by the same stimulus based on the trace file transferred by the high-level DUT, thereby quickly and accurately positioning the problem point and improving the efficiency of chip verification and debugging.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a diagram illustrating a trace file based chip debugging system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a trace file format according to an embodiment of the present invention;
FIG. 3 is a diagram of a trace file format according to another embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given to a specific implementation and effects of a trace file based chip debugging system according to the present invention with reference to the accompanying drawings and preferred embodiments.
An embodiment of the present invention provides a chip debug system based on trace files, as shown in fig. 1, including a bus interface configuration file, a high-level DUT to be designed H 、DUT H Corresponding N low-level design under test { DUT L1 ,DUT L2 ,…, DUT Ln ,…,DUT LN DUT, memory storing a computer program, and processor H ={U H1 ,U H2 ,…,U HM }，U H1 ,U H2 ,…,U HM Is a DUT H M is a DUT H Number of constituent modules of U H1 ,U H2 ,…,U HM Setting a hierarchy; { DUT L1 ,DUT L2 ,…,DUT Ln ,…,DUT LN Is { U } H1 ,U H2 ,…,U HM A subset of (a) }; DUT Ln Is a DUT H Corresponding nth low-level design to be tested, wherein the value range of N is 1 to N, and the DUT Ln ={U L1 n ,U L2 n ,…,U Lf(n) n }, U L1 n ,U L2 n ,…,U Lf(n) n Is a DUT Ln F (n) is DUT Ln Including the number of constituent modules, U L1 n ,U L2 n ,…,U Lf(n) n Setting a hierarchy; { U L1 n ,U L2 n ,…,U Lf(n) n Is { U } H1 ,U H2 ,…,U HM A subset of { C }; u shape i And U j Two constituent modules in an interconnected relationship. Note that, the DUT H And designing the DUT for the preliminarily selected high-level to-be-tested device with the problem points.
U i And U j All belong to { U H1 ,U H2 ,…,U HM Either all belong to { U } L1 n ,U L2 n ,…,U Lf(n) n }；U i And U j Is passed through toAt least one bus interface, U i And U j Interconnection between sibling modules or parent-child modules having an interconnection relationship, for example, as sibling modules or parent-child modules, through at least one bus interface, is understood to mean that U is a member of the group i And U j Satisfy all belong to { U L1 n ,U L2 n ,…,U Lf(n) n All of them must also satisfy the condition of being { U } H1 ,U H2 ,…,U HM }。U i And U j Satisfy all the belongings to { U H1 ,U H2 ,…,U HM In the case of (U), it is not always satisfied that all of them belong to { U } L1 n ,U L2 n ,…,U Lf(n) n }。
The bus interface configuration file comprises { ITC L1 ,ITC L2 ,…, ITC Ln ,…,ITC LN }，ITC Ln Is a DUT Ln Target bus interface list of, each ITC Ln Including at least one target bus interface IT k And K is the total number of target bus interfaces, and the value range of K is 1 to K. Note that the DUT H For high level chip design to be debugged, it is necessary to test the DUT H The problem points are positioned in the chip design of the low level. The chip design scale is huge, so that it is not suitable to use DUT H The data of all interface information is completely unloaded (Dump), because the complete unloading consumes a great deal of resources, resulting in slow debugging process. In the debugging process, a possible problem point area can be defined, so that a target bus interface IT can be selected by setting a bus interface configuration file k The debugging efficiency is improved, and the resource consumption is reduced.
When the processor executes the computer program, the following steps are realized:
step S1, based on DUT H Acquire each IT k Corresponding description information including IT k Corresponding component module identification, bus interface signal and IT k Signal mapping information, data valid identification constraint information, signal description information, said signal description information including signal direction.
Wherein IT k The corresponding component module may be IT k The initiating terminal constituting module or the receiving terminal constituting module, IT k The corresponding bus interface information is stored in the corresponding component module, and it can be understood that each bus interface information is stored in the corresponding initiating terminal component module or in the corresponding receiving terminal component module. The description information further comprises IT k And identifying the corresponding bus interface type. The signal description information may further include a signal width.
Step S2, operating the DUT H From the DUT H Transferring each IT k A corresponding active bus interface data record comprising IT k The signal value, absolute time and/or clock Cycle (Cycle) number corresponding to each signal in the signal table is based on IT k The corresponding description information and valid bus interface data records generate the raw trace file.
Wherein, pass through the DUT H Corresponding verification platform (Testbench) drives DUT H . The clock cycle sequence number represents the corresponding clock cycle, the absolute time represents the time corresponding to a group of signals corresponding to the data record of an effective bus interface, which is obtained by starting timing from the initial moment.
Step S3, according to the signal direction and the signal value, the slave ITC Ln Corresponding all IT k Extracts the excitation signals from the original trace file and sends the corresponding excitation signals to the DUT according to the absolute time and/or the clock cycle sequence number in a preset sequence Ln And DUT Ln And (4) corresponding to the simulation model.
The method comprises the steps of acquiring excitation signals with signal directions of Input according to signal directions, determining the sending sequence and time of the excitation signals according to absolute time and/or clock cycle sequence numbers, sending the corresponding excitation signals to a DUT (device under test) according to the excitation signals in a preset sequence Ln And DUT Ln The corresponding simulation model can realize playback (Replay) under the same stimulus, so that the problem point can be quickly and accurately determined from the DUT at a low level under the condition of the same stimulus.
Step S4, slave DUT Ln Transfer memory ITC Ln Each IT in k Corresponding first virtual bus interface data records, unloading ITC from corresponding simulation models Ln Each IT in k Corresponding second valid bus interface data record based on IT k Generating a first trace file based on the IT using the corresponding description information and the first valid bus interface data record k Generating a second trace file by the corresponding description information and the second effective bus interface data record;
step S5 based on DUT Ln All IT in k Corresponding first trace file and second trace file to DUT Ln Trace debug to locate a DUT Ln The problem in (1).
As an embodiment, the step S5 is followed by:
step S6, modifying the DUT Ln To return to re-execute step S3 to step S4 to generate IT k Corresponding modified first trace file and modified second trace file, and determining DUT based on the modified first trace file and the modified second trace file Ln Whether the problem point in (1) is repaired.
It should be noted that, in the early stage and the middle stage of chip development, the chip design and the verification platform are not perfect, and when the system of the present invention is used for playback under the same excitation, the problem can be quickly positioned, the chip debugging efficiency is improved, the chip design and the chip verification are assisted, and further the chip verification and the chip design efficiency is also improved.
After the problem point is modified, and the steps S3 to S4 are executed again, the modified DUT can still be run by adopting the same stimulus in the original trace file Ln Thereby rapidly and accurately judging DUT Ln Whether the problem point in (1) is repaired.
As an embodiment, the original trace file, the first trace file, and the second trace file are generated according to a preset trace file format, where the preset trace file format includes a first file area and a second file area, and the first file area is used for storing IT k And the second file area is used for storing effective bus interface data records.The active bus interface data records are stored row by row, i.e. each active bus interface data record occupies one row, as illustrated in the example of fig. 2. The active bus interface data records may also be stored column by column, i.e. each active bus interface data record occupies one column, as illustrated in the example of fig. 3. Target data corresponding to any one target bus interface bus can be quickly and accurately obtained through tracking files, chip performance verification is achieved, Z in both figures 2 and 3 represents the total number of effective bus interface data records, the reference numeral 1 represents a first file area, and the reference numeral 2 represents a second file area.
As an example, a composition module Mod is provided i1 Is { U H1 ,U H2 ,…,U HM } or { U L1 n ,U L2 n ,…,U Lf(n) n Element in (v), mod i1 The atomic unit may be an atomic unit or a module composed of atomic units, the atomic unit is preset with a corresponding RTL code, and the RTL code may be specifically written in hardware programming languages such as Verilog, system Verilog, VHDL, and the like. Setting Mod i1 Including a module unique identifier MID i1 And Mod i1 Z1 (i 1) module internal bus Interface (Interface) list (InI) of interconnection of sub-modules 1 ,InI 2 ,...,InI Z1(i1) ) And with Mod i1 Z2 (i 1) module External bus Interface (External Interface) list (MExI) of sibling module interconnections of 1 ,MExI 2 ,...,MExI Z2(i1) ). The Mod i1 Is positioned at Mod i1 Internal and proportional Mod i1 One level lower. The DUT further comprises a device capable of generating K4 Design Interconnect assemblY DIY (Design Interconnect assemblY) = (X) based on the internal bus interface list and the external bus interface list corresponding to all the component modules 1 _Y 1 _CMD 1 , X 2 _Y 2 _CMD 2 ,...，X i5 _Y i5 _CMD i5 ,...，X K4 _Y K4 _CMD K4 ) Wherein X is i5 And Y i5 Is also { U H1 ,U H2 ,…,U HM } or { U L1 n ,U L2 n ,…,U Lf(n) n The value range of i5 of the elements in the formula is 1 to K4; x i5 And Y i5 Modules of mutual brothers, or X i5 Is Y i5 Or Y, or i5 Is X i5 The parent module of (2).
As an example, X i5 And X i6 May be the same or different; y is i5 And Y i6 May be the same or different; the value of i6 ranges from 1 to K4.CMD i5 Is IDF-ID, and is used for obtaining corresponding bus Interface detail information from bus Interface Description reconstruction library, and the bus Interface Description reconstruction library includes K3 predefined bus Interface reconstruction structures IDF (Interface Description register) = (IDF) 1 ,IDF 2 ,..., IDF i3 ,...,IDF K3 ) And K3 is more than or equal to 0. Wherein, IDF i3 Including bus interface unique identification IDF-ID i3 Z4 (i 3) signals (Sig) i3 1 ,Sig i3 2 ,..., Sig i3 i4 ,...,Sig i3 z4(i3) )，Sig i3 i4 Including signal direction, signal width Wid (i 3, i 4), reSeT (ReSeT) value (RST) i3i4 1 ，RST i3i4 2 ，...，RST i3i4 Wid(i3 ,i4) ) Default (Default) value (Def) i3i4 1 ，Def i3i4 2 ，...，Def i3i4 Wid(i3,i4) ) And data valid identification constraint information. i3 has a value from 1 to K3, i4 has a value from 1 to Z4 (i 3), Z4 (i 3) being a function of i 3.
Preferably, IDF-ID i3 Associated with the bus interface type. The bus interface type is, for example, an AMBA bus, a PCIE bus, a SATA bus, a USB bus, an HBM bus, or a custom bus interface type. The signal directions may be set to an Input direction (Input), an Output direction (Output), and a bidirectional direction (Inout). The signal width Wid (i 3, i 4) is signal Sig i3 i4 The number of signal lines (Wire) used.
As an example, IT k The corresponding signal comprises at least one active markAn identification signal, a tracking id signal and a data signal, the data valid identification constraint information comprising a constraint generated based on all valid identification signals. By IT k The corresponding signal includes { Si 1 ,Si 2 ,…,Si R For example, si may be provided only 1 For valid identification signals, when Si 1 When the signal value of (2) is equal to the preset signal value, the corresponding Si is described 2 ,…,Si R Is valid data. Or a plurality of signals, e.g. Si 1 ,Si 2 , Si 3 Satisfies a predetermined constraint, e.g. Si when the sum equals a predetermined signal value 1 , Si 4 ,…,Si R Is valid data. One of the signals, e.g. Si R For tracking id signals, the id signals may be specifically configured as a structure or a complex, IT should be noted that the id signals are tracked in the same data chain, the same data transmitted is the same, but because signal formats corresponding to different bus interface buses may be different, forms corresponding to the id signals in different bus interface buses may be different, and the signal values of the id signals may be obtained by decoding the id signals through encoding rules corresponding to the bus interfaces, so that the id signals in a plurality of IT's are tracked k And carrying out problem tracking by using the corresponding tracking file. The tracking id signal and the valid identification signal correspond to different signals, IT k All signals except the valid identification signal and the trace id signal in the corresponding signals are data signals.
Based on the U i1 DIY and IDF information can be automatically generated into IT k Corresponding description information.
As an example, IT k The corresponding signals include at least one valid identification signal, a trace id signal, and a data signal, the data valid identification constraint information including a constraint generated based on all valid identification signals. In the step S2, when IT is performed k Executing the slave DUT when the corresponding valid identification signal satisfies the corresponding data valid identification constraint information H Transferring each IT k The corresponding effective bus interface data recording operation; in the step S4, when the DUT Ln Middle IT k The slave DUT when the corresponding valid identification signal satisfies the corresponding data valid identification constraint information Ln Intermediate transfer IT k A corresponding first active bus interface data record; when IT is k When the corresponding effective identification signal in the corresponding simulation model meets the corresponding data effective identification constraint information, the slave IT k Unloading IT in corresponding simulation model k A corresponding second active bus interface data record.
As an example, the step S5 includes:
step S51, based on IT k And acquiring a corresponding first trace file and a corresponding second trace file by the corresponding bus interface identifier.
Step S52, determining IT based on target tracking id k A corresponding first target active bus interface data record and second target active bus interface data record.
Step S53, based on IT k Corresponding first target valid bus interface data record and second target valid bus interface data record to IT k And the corresponding component module performs function verification.
It should be noted that data may be compressed or packed in the simulation model, resulting in data output from the simulation model and from the DUT Ln The corresponding component modules in (1) have different output data sequences, formats and the like. For example, DUT Ln The corresponding component module in (1) outputs 5 data arranged in a certain order, and the simulation model outputs the order of the corresponding 5 data and the DUT Ln The corresponding component modules in (1) have different outputs, or 2 pieces of data are combined together, and the like. Therefore, the first active bus interface data record and the second active bus interface data record need to be converted and compared. As an embodiment, the step S53 includes:
step S531, judging DUT Ln Each IT in k And if so, directly executing the step S533, otherwise, executing the step S532.
Step S532, the second target effective bus interface data record is converted into a data structure identical to the first target effective bus interface data record, or both the first target effective bus interface data record and the second target effective bus interface data record are converted into a preset target data structure identical to each other.
The data structure conversion can be performed in an unambiguous manner by means of a script. It should be noted that any existing implementation that converts the data structures of the first target active bus interface data record and the second target active bus interface data record into the same through a script falls within the scope of the present invention. The extraction of the common portion of the first active bus interface data record and the second active bus interface data record may be achieved by step S532.
Step S533, comparing IT one by one k If the corresponding signal values in the first target effective bus interface data record and the second target effective bus interface data record are consistent, the IT is carried out k The function is verified, otherwise, the IT is determined k Is a DUT Ln The problem in (1).
As an embodiment, the step S5 includes:
step S51' based on DUT Ln Each IT in k Determining IT by signal width, absolute time and/or clock cycle number in corresponding first trace file and selected first effective bus interface data record line number k Corresponding throughput.
Specifically, IT k The corresponding signal list is { Si 1 ,Si 2 ,…, Si ik ,…,Si f(k) }, Si ik Is IT k Corresponding ik signal, ik ranging from 1 to f (k) as a function of k, si ik Corresponding signal width We ik The step S51' includes:
step S511' based on IT k And acquiring a corresponding tracking file by using the corresponding bus interface identifier.
Step S512' Slave IT k Selecting F rows of effective bus interface data records from the corresponding trace file, and recording based on the F rows of effective bus interface data recordsDetermining the time TF required for acquiring the data record of the effective bus interface of the F row based on the corresponding absolute time and/or the clock cycle sequence number ik F determining IT k Corresponding throughput TH k :
Step S513' based on DUT Ln Each IT in k Determining IT by absolute time and/or clock cycle number corresponding to a corresponding set of target request information and target response information k Corresponding to the delay.
Step S514' based on IT k Corresponding delay and throughput with T k Comparing the corresponding preset target delay with the target throughput, if the preset target delay is matched with the target throughput, determining the IT k The performance verification is passed, otherwise, the IT is determined k Is a DUT Ln The problem in (1).
It should be noted that, the target delay and the target throughput may be configured by setting a configuration file, and the target delay and the target throughput may be changed directly by changing the configuration file. The throughput target value and the delay target value may be specific values or may be a range of values, which is specifically determined according to the performance test requirements. If the throughput target value and the delay target value are specific values, IT k And determining that the throughput is matched when the corresponding throughput is equal to the corresponding throughput target value in the configuration file. IT (information technology) device k And determining that the corresponding delay is matched with the corresponding delay target value in the configuration file when the corresponding delay is equal to the corresponding delay target value. If the throughput target value and the delay target value are in the numerical range, IT k When the corresponding throughput is in the numerical range of the throughput target value, determining that the throughput is matched; if IT is k And when the corresponding delay is within the numerical range of the delay target value, determining the delay matching.
To DUT L One possibility is any DUT at the time of debugging Ln All the problem points are not determined, and the problem points are determined by debugging one by one. Another possibility has been to determine some of the DUTs Ln Having a problem point to be locatedThe specific location. For DUTs for which a problem point has been determined Ln DUTs that can be identified as a specified problem, if all DUTs Ln If none of the DUTs is a specified problem, then the step S5 further includes:
step S54, if the DUT Ln All IT in k Is verified, the DUT Ln The verification is passed;
step S55, if all DUTs are available Ln And if the verification is passed, generating integrated early warning information.
Note that, the DUT H There is a problem with each DUT Ln There is no problem in the separate verification, and there is a high possibility that the DUT is Ln There is a problem with the integration between them, and thus integrated early warning information is generated.
As an example, if the DUT Ln To specify the DUT in question, if the DUT is Ln All IT in k If the functions and performances of the system are verified, the following steps are executed:
step S56 based on DUT Ln Corresponding authentication platform TB Ln Generating includes TB Ln And verifying platform early warning information of the identification.
Note that, the DUT Ln To specify a problem DUT, the problem point must be accounted for, and the DUT Ln All IT in k If the verification is passed, the problems of the verification platform can be found in time, so that the early warning information of the verification platform is generated, the verification platform is modified based on the early warning information of the verification platform, and the robustness and the accuracy of the verification platform are improved.
The system provided by the embodiment of the invention can debug the low-level design to be tested based on the trace file transferred by the high-level DUT by the same stimulus, so that the problem point is quickly and accurately positioned, the efficiency of chip verification and debugging is improved, the chip design and chip verification are assisted to find the problem in time for correction, and the efficiency of chip design and verification is further improved.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A trace file based chip debugging system is characterized in that,
the method comprises a bus interface configuration file and a high-level design to be tested DUT H 、DUT H Corresponding N low-level designs under test { DUT L1 ,DUT L2 ,…,DUT Ln ,…,DUT LN DUT, memory storing a computer program, and processor H ={U H1 ,U H2 ,…,U HM }，U H1 ,U H2 ,…,U HM Is a DUT H M is DUT H Number of constituent modules of U H1 ,U H2 ,…,U HM Setting a hierarchy; { DUT L1 ,DUT L2 ,…,DUT Ln ,…,DUT LN Is { U } H1 ,U H2 ,…,U HM A subset of { C }; DUT Ln Is a DUT H Corresponding nth low-level design to be tested, wherein the value range of N is 1 to N, and the DUT Ln ={U L1 n ,U L2 n ,…,U Lf(n) n }, U L1 n ,U L2 n ,…,U Lf(n) n Is a DUT Ln Composition of (2)Module, f (n) is DUT Ln Including the number of constituent modules, U L1 n ,U L2 n ,…,U Lf(n) n Setting a hierarchy; { U L1 n ,U L2 n ,…,U Lf(n) n Is { U } H1 ,U H2 ,…,U HM A subset of { C }; u shape i And U j For two constituent modules having an interconnecting relationship, U i And U j All belong to { U H1 ,U H2 ,…,U HM Or all belong to { U } L1 n ,U L2 n ,…,U Lf(n) n }；U i And U j Are interconnected through at least one bus interface, U i And U j The brother modules or the father and son modules are interconnected through at least one bus interface, and the brother modules or the father and son modules have an interconnection relationship; the bus interface configuration file comprises { ITC L1 ,ITC L2 ,…,ITC Ln ,…,ITC LN }，ITC Ln Is a DUT Ln Target bus interface list of, each ITC Ln Including at least one target bus interface IT k The value range of K is 1 to K, and K is the total number of the target bus interfaces;
when the processor executes the computer program, the following steps are realized:
step S1, based on DUT H Acquire each IT k Corresponding description information including IT k Corresponding component module identification, bus interface signal and IT k The bus interface identifier is generated based on the hierarchy information corresponding to the bus interface and the name of the bus interface instance, and the signal description information comprises a signal direction;
step S2, operating the DUT H From DUT H Transferring each IT k A corresponding active bus interface data record comprising IT k The signal value, absolute time and/or clock cycle number corresponding to each signal in the signal table is based on IT k Corresponding description information and valid sumRecording the line interface data to generate an original tracking file;
step S3, according to the signal direction and the signal value, the slave ITC Ln All corresponding IT k Extracts the excitation signals from the original trace file and sends the corresponding excitation signals to the DUT according to the absolute time and/or the clock cycle sequence number in a preset sequence Ln And DUT Ln A corresponding simulation model;
step S4, slave DUT Ln Transfer memory ITC Ln Each IT in k Corresponding first active bus interface data records, unloading ITC from corresponding simulation model Ln Each IT in k Corresponding second valid bus interface data record based on IT k Generating a first trace file based on the IT using the corresponding description information and the first valid bus interface data record k Generating a second trace file by the corresponding description information and the second effective bus interface data record;
step S5, based on DUT Ln All IT in k Corresponding first trace file and second trace file to DUT Ln Trace debug to locate a DUT Ln The problem in (1).
2. The system of claim 1,
after the step S5, the method further includes:
step S6, modifying the DUT Ln To return to re-execute step S3 to step S4 to generate IT k A corresponding modified first trace file and modified second trace file, and determining the DUT based on the modified first trace file and the modified second trace file Ln Whether the problem point in (1) is repaired.
3. The system of claim 1,
IT k the corresponding signals include at least one valid identification signal, a trace id signal, and a data signal, the data valid identification constraint information including a constraint generated based on all valid identification signals;
said step S2In when IT k Executing the slave DUT when the corresponding valid identification signal satisfies the corresponding data valid identification constraint information H Transferring each IT k The corresponding effective bus interface data recording operation;
in the step S4, when the DUT Ln Middle IT k Slave DUT when corresponding valid identification signal satisfies corresponding data valid identification constraint information Ln Intermediate transfer IT k A corresponding first active bus interface data record;
when IT is k When the corresponding effective identification signal in the corresponding simulation model meets the corresponding data effective identification constraint information, the slave IT k Unloading IT in corresponding simulation model k A corresponding second active bus interface data record.
4. The system of claim 1,
the step S5 includes:
step S51, based on IT k The corresponding bus interface identification obtains a corresponding first tracking file and a second tracking file;
step S52, determining IT based on target tracking id k Corresponding first and second target active bus interface data records;
step S53, based on IT k Corresponding pairs of first target valid bus interface data record and second target valid bus interface data record k And the corresponding component module performs function verification.
5. The system of claim 4,
the step S53 includes:
step S531, judging the DUT Ln Each IT in k Whether the data structures of the corresponding first target effective bus interface data record and the second target effective bus interface data record are consistent or not is judged, if yes, the step S533 is directly executed, and if not, the step S532 is executed;
step S532, converting the second target effective bus interface data record into a data structure same as the first target effective bus interface data record, or converting both the first target effective bus interface data record and the second target effective bus interface data record into a preset target data structure;
step S533, comparing IT one by one k If each signal value in the corresponding first target effective bus interface data record and the corresponding second target effective bus interface data record is consistent, the IT k The function passes the verification, otherwise, the IT is determined k Is a DUT Ln The problem in (1).
6. The system of claim 4,
the signal description information further includes a signal width, and the step S5 includes:
step S51' based on DUT Ln Each IT in k Determining IT by signal width, absolute time and/or clock cycle number in corresponding first trace file and selected first effective bus interface data record line number k A corresponding throughput;
step S52' based on DUT Ln Each IT in k Determining IT by absolute time and/or clock cycle number corresponding to a corresponding set of target request information and target response information k Correspondingly delaying time;
step S53' based on IT k Corresponding delay and throughput to T k Comparing the corresponding preset target delay with the target throughput, and if the preset target delay is matched with the target throughput, determining the IT k The performance verification is passed, otherwise, the IT is determined k Is a DUT Ln The problem in (1).
7. The system of claim 6,
if all DUTs Ln If none of the DUTs is a specified problem, the step S5 further comprises:
step S54, if the DUT Ln All IT in k Is verified, the DUT Ln The verification is passed;
step S55, if allDUT Ln And if the verification is passed, generating integrated early warning information.
8. The system of claim 6,
if DUT Ln To specify the DUT in question, if the DUT is Ln All IT in k If the functions and performances of the system are verified, the following steps are executed:
step S56 based on DUT Ln Corresponding authentication platform TB Ln Generating includes TB Ln And verifying platform early warning information of the identification.
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