CN114780402A - Debugging method and device of chip simulation system and server - Google Patents
Debugging method and device of chip simulation system and server Download PDFInfo
- Publication number
- CN114780402A CN114780402A CN202210422132.8A CN202210422132A CN114780402A CN 114780402 A CN114780402 A CN 114780402A CN 202210422132 A CN202210422132 A CN 202210422132A CN 114780402 A CN114780402 A CN 114780402A
- Authority
- CN
- China
- Prior art keywords
- chip
- configuration file
- code
- signal
- excitation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
- G06F9/4451—User profiles; Roaming
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides a debugging method of a chip simulation system, which relates to the technical field of chip circuit design verification and comprises the following steps: when a monitoring instruction sent by the control terminal is received, reading a target configuration file corresponding to the monitoring control instruction; controlling a chip to be debugged in the chip simulation system, and operating according to the excitation configuration file and the code configuration file to obtain a chip output signal; and performing signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain a chip debugging result. The invention can obviously reduce the time cost of debugging the chip simulation system and can simulate a more real chip using environment, thereby improving the debugging precision of the chip simulation system.
Description
Technical Field
The invention relates to the technical field of chip circuit design verification, in particular to a debugging method and device of a chip simulation system and a server.
Background
The chip simulation system is a system for simulating the functions of a real chip through a computer so as to debug software. At present, the related art provides that a mainstream chip simulation system can provide excitation through a Test Case, provide a program execution code through a memory code Romcode, and compile the excitation and the program execution code together, so as to simulate and output a specific result.
Disclosure of Invention
In view of this, an object of the present invention is to provide a method, an apparatus and a server for debugging a chip simulation system, which can significantly reduce the time cost for debugging the chip simulation system, and can also simulate a more real chip usage environment, thereby improving the debugging accuracy of the chip simulation system.
In a first aspect, an embodiment of the present invention provides a method for debugging a chip simulation system, where the method is applied to the chip simulation system, the chip simulation system is connected to a control terminal, and the method includes: when a monitoring instruction sent by a control terminal is received, reading a target configuration file corresponding to the monitoring control instruction; wherein the target profile comprises one or more of an excitation profile, a code profile, and a signal analysis profile; controlling a chip to be debugged in the chip simulation system, and operating according to the excitation configuration file and the code configuration file to obtain a chip output signal; and performing signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain a chip debugging result.
In one embodiment, the chip simulation system comprises a monitoring module connected with a chip to be debugged, wherein the monitoring module comprises an excitation monitoring unit and a code monitoring unit; controlling a chip to be debugged in the chip simulation system, and operating according to an excitation configuration file and a code configuration file to obtain a chip output signal, wherein the step comprises the following steps of: sending a first excitation signal to a chip to be debugged based on an excitation configuration file through an excitation monitoring unit; sending a first code downloading signal to a chip to be debugged based on the code configuration file through a code monitoring unit; wherein, the first code download signal carries a first code program; when the chip to be debugged receives the first code download signal, the first code program is operated through the chip to be debugged, and a first chip output signal corresponding to the first excitation signal is generated.
In one embodiment, the method further comprises: monitoring whether an excitation configuration file is updated or not through an excitation monitoring unit in the process that a chip to be debugged runs a first code program, and sending an updated second excitation signal to the chip to be debugged through the excitation monitoring unit when the excitation configuration file is updated; and when the chip to be debugged receives the second excitation signal, the first code program is rerun through the chip to be debugged, and a second chip output signal corresponding to the second excitation signal is generated.
In one embodiment, the method further comprises: monitoring whether a code configuration file is updated or not through a code monitoring unit in the process that a chip to be debugged runs a first code program, and monitoring a second code downloading signal after updating to be sent to the chip to be debugged through the code monitoring unit when the code configuration file is updated; wherein the second code download signal carries the second code program; and when the chip to be debugged receives the second code downloading signal, the chip to be debugged stops running the first code program and runs the second code program to generate a third chip output signal corresponding to the first excitation signal.
In one embodiment, the monitoring module further comprises a signal analysis monitoring unit; the method comprises the steps of carrying out signal analysis processing on chip output signals based on a signal analysis configuration file to obtain a chip debugging result, and comprises the following steps: and determining a signal to be analyzed from the output signals of the chip through the signal analysis monitoring unit based on the signal analysis configuration file, and performing signal analysis processing on the signal to be analyzed to obtain a chip debugging result.
In one embodiment, the excitation monitoring unit is connected with the control terminal through a first interface, the code monitoring unit is connected with the control terminal through a second interface, and the signal analysis monitoring unit is connected with the control terminal through a third interface; when receiving a monitoring instruction sent by a control terminal, reading a target configuration file corresponding to the monitoring control instruction, wherein the step comprises the following steps: when the first interface receives a monitoring instruction sent by the control terminal, the excitation monitoring unit reads an excitation configuration file; or, when the second interface receives a monitoring instruction sent by the control terminal, the code configuration file is read through the code monitoring unit; or when the third interface receives a monitoring instruction sent by the control terminal, the signal analysis configuration file is read through the signal analysis monitoring unit.
In one embodiment, the method further comprises: when a control instruction sent by a control terminal is received, controlling the monitoring module and/or the chip to be debugged to execute an action corresponding to the control instruction; the control instruction comprises a pause instruction and/or a stop instruction, the pause instruction is used for indicating the monitoring module and/or the chip to be debugged to stop working and storing the working state to the target configuration file, and the stop instruction is used for indicating the monitoring module and/or the chip to be debugged to stop working and restoring the target configuration file to a default value.
In a second aspect, an embodiment of the present invention further provides a debugging apparatus for a chip simulation system, where the apparatus is applied to the chip simulation system, the chip simulation system is connected to a control terminal, and the apparatus includes: the configuration file query module is used for reading a target configuration file corresponding to a monitoring control instruction when receiving the monitoring instruction sent by the control terminal; wherein the target profile comprises one or more of an excitation profile, a code profile, and a signal analysis profile; the chip debugging module is used for controlling a chip to be debugged in the chip simulation system and operating according to the excitation configuration file and the code configuration file to obtain a chip output signal; and the signal analysis module is used for carrying out signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain a chip debugging result.
In a third aspect, an embodiment of the present invention further provides a server, including a processor and a memory, where the memory stores computer-executable instructions capable of being executed by the processor, and the processor executes the computer-executable instructions to implement any one of the methods provided in the first aspect.
In a fourth aspect, embodiments of the present invention also provide a computer-readable storage medium storing computer-executable instructions that, when invoked and executed by a processor, cause the processor to implement the method of any one of the aspects provided by the first aspect.
The embodiment of the invention brings the following beneficial effects:
the method is applied to a chip simulation system, the chip simulation system is connected with a control terminal, when the chip simulation system receives a monitoring instruction, a target configuration file corresponding to the monitoring control instruction is read, so that a chip to be debugged in the chip simulation system is controlled, a chip output signal is obtained by running according to an excitation configuration file and a code configuration file, and the chip output signal is subjected to signal analysis processing based on a signal analysis configuration file, so that a chip debugging result is obtained. The method can debug the chip simulation system by changing the excitation file in the operation process of the simulation system, compared with the technical problems that in the related technology, the simulation needs to be completely compiled again when excitation or codes change, and the whole process is refreshed again.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a chip simulation system according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a debugging method of a chip emulation system according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of another debugging method for a chip emulation system according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a debugging apparatus of a chip emulation system according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the embodiments, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
At present, a mainstream chip simulation system provides excitation through a Test Case, provides a program execution code through a memory code Romcode, and compiles the excitation and the program execution code together, so as to simulate and output a specific result. Based on this, the embodiment of the invention provides a debugging method, a debugging device and a server for a chip simulation system, which can significantly reduce the time cost of debugging the chip simulation system and can simulate a more real chip using environment, thereby improving the debugging precision of the chip simulation system.
For facilitating understanding of the present embodiment, first, a detailed description is given to a debugging method of a chip simulation system disclosed in the present embodiment, the method is applied to a chip simulation system for simulating functions of a real chip, and for facilitating understanding of the chip simulation system, the present embodiment provides a structural schematic diagram of the chip simulation system, as shown in fig. 1, the chip simulation system is configured with a chip to be debugged and a monitoring module connected with the chip to be debugged, the monitoring module includes an excitation monitoring unit, a code monitoring unit and a signal analysis monitoring unit, the monitoring module and the chip to be debugged are respectively connected with a control terminal (i.e. a man-machine interaction interface), the monitoring module and the working state of the chip to be debugged are controlled based on a start signal, a pause signal and an end signal of the control terminal, the excitation monitoring unit can query and read an excitation configuration file to send an excitation signal to the chip to be debugged, the code monitoring unit can inquire and read the code configuration file to send a code downloading signal to the chip to be debugged, the chip to be debugged receives the excitation signal and the downloading signal to send an output signal to the signal analysis monitoring unit, the signal analysis monitoring unit can look up and read the signal analysis configuration file, the signal to be analyzed is determined from the output signal, the signal to be analyzed is processed to obtain a chip debugging result, and the chip debugging result is printed on the display.
Based on the schematic structural diagram of the chip simulation system shown in fig. 1, the embodiment of the present invention introduces a debugging method of the chip simulation system in detail, referring to a flow diagram of the debugging method of the chip simulation system shown in fig. 2, and the method mainly includes the following steps S202 to S206:
step S202, when receiving the monitoring instruction sent by the control terminal, reading a target configuration file corresponding to the monitoring control instruction. The control terminal is connected with the chip simulation system through a man-machine interaction interface, the control terminal is used for sending signals of starting, pausing, ending and the like to the chip simulation information system through the man-machine interaction interface so as to control the working state of each module in the chip simulation system, the target configuration file comprises one or more of an excitation configuration file, a Code configuration file and a signal analysis configuration file, and the Code configuration file can comprise Rom Code memory codes.
In one embodiment, the target configuration file is configured in the excitation monitoring unit, one end of the excitation monitoring unit is connected with the chip simulation system, and the other end of the excitation monitoring unit is connected with the device to be measured, the experimental equipment and the like, and the target configuration file is used for feeding back the variation condition of the device/experimental equipment to the chip simulation system after being screened and compiled in the target configuration file.
And step S204, controlling a chip to be debugged in the chip simulation system, and operating according to the excitation configuration file and the code configuration file to obtain a chip output signal. The code configuration file is used for updating a program in the chip to be debugged, and the excitation configuration file is used for limiting the transmitted digital signal (namely excitation), so that the chip to be debugged can transmit a corresponding output signal to the signal analysis monitoring unit.
In one embodiment, the code download signal received by the chip to be debugged and the last configuration change/the received excitation signal and the last configuration change both generate new output signals, and the obtained new output signals are different.
And step S206, performing signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain a chip debugging result. The signal analysis profile may include, among other things, an identification of the signals to be grabbed, such as the grab voltage signal.
In one embodiment, the signal to be analyzed is determined from the chip output signals by the signal analysis monitoring unit based on the signal analysis configuration file, and the signal to be analyzed is subjected to signal analysis processing: and filtering, classifying and the like the captured part output to the signal to obtain a chip debugging result, and printing the chip debugging result obtained in the chip debugging process to a display in real time to obtain the debugging result change condition of the simulation chip.
The debugging method of the chip simulation system provided by the embodiment of the invention can finish debugging the chip simulation system in the running process of the chip simulation system by changing the corresponding excitation file, can obviously reduce the time cost of debugging the chip simulation system, and can simulate a more real chip using environment, thereby improving the debugging precision of the chip simulation system.
For the foregoing step S202, an embodiment of the present invention further provides an implementation manner for controlling the operating state of the chip simulation system through the control terminal, specifically refer to the following (1) to (3):
(1) and when the first interface receives a monitoring instruction sent by the control terminal, the excitation monitoring unit reads the excitation configuration file.
(2) And when the second interface receives a monitoring instruction sent by the control terminal, reading the code configuration file through the code monitoring unit.
(3) And when the third interface receives a monitoring instruction sent by the control terminal, reading the signal analysis configuration file through the signal analysis monitoring unit. Wherein the signal analysis profile is used to determine the type of signal captured (such as capture length signal, accuracy signal, voltage signal, current signal, etc.).
In one embodiment, when a control instruction sent by a control terminal is received, the monitoring module and/or the chip to be debugged is controlled to execute an action corresponding to the control instruction. The control instruction comprises a pause instruction and/or a stop instruction, the pause instruction is used for indicating the monitoring module and/or the chip to be debugged to stop working and storing the working state to a target configuration file, the stop instruction is used for indicating the monitoring module and/or the chip to be debugged to stop working and recovering the target configuration file to a default value, when the module receives a start signal, the module reads data of an internal initialization value area and starts working, when the received control signal is pause, the module stops working and stores the current state to the initialization value area, and when the module receives the control signal which is stop, the initialization value area is recovered to the default value and stops working.
For the foregoing step S204, an embodiment of the present invention further provides an implementation manner of obtaining a chip output signal, which specifically refers to the following (1) to (3):
(1) sending a first excitation signal to a chip to be debugged based on an excitation configuration file through an excitation monitoring unit; the excitation configuration file is used for simulating the operation environment of the chip, when the actual working environment of the instrument changes, a changed signal is generated and is input into the file (for example, the angle of a working device connected with the end of the excitation configuration file inclines, a sensor in the device generates voltage, the generated voltage is sent to the chip in the device, and the chip in the device translates the voltage into a digital signal through operation and stores the signal into the excitation configuration file).
(2) Sending a first code downloading signal to a chip to be debugged based on the code configuration file through a code monitoring unit; the first code downloading signal carries a first code program, wherein the code configuration file comprises the code program, the code program in the code position file is sent to the chip to be debugged, and the program running in the chip to be debugged is updated.
(3) When the chip to be debugged receives the first code download signal, the first code program is operated through the chip to be debugged, and a first chip output signal corresponding to the first excitation signal is generated. For example, the embodiment of the present invention provides an implementation manner for determining an output signal in a code debugging process, see the following steps a1 to a 2:
step a1, in the process of running the first code program by the chip to be debugged, acquiring the excitation signal stored in the excitation configuration file initialization value area, comparing the acquired excitation signal with the excitation signal acquired last time, and monitoring whether the excitation configuration file is updated or not by the excitation monitoring unit. By way of example, the present application provides an embodiment in which the output signal is determined from the result of the update of the excitation signal, see steps a1.1 to a1.2 as follows:
a1.1, when the excitation configuration file is updated, monitoring a second excitation signal which is sent to the chip to be debugged after updating through an excitation monitoring unit.
In an embodiment, when the chip to be debugged receives the second excitation signal, the first code program is re-run by the chip to be debugged, and a second chip output signal corresponding to the second excitation signal is generated.
a1.2, when the excitation configuration file is not updated, continuously generating the excitation signal according to the last configuration.
Step a2, in the process of running the first code program on the chip to be debugged, acquiring the download signal stored in the initialization value area of the code configuration file, comparing the acquired download signal with the download signal acquired last time, and the code monitoring unit will monitor whether the code configuration file is updated. By way of example, the present application provides an embodiment of determining an output signal according to an update result of a download signal, see steps a2.1 to a2.2 as follows:
a2.1, monitoring a second code downloading signal after updating is sent to a chip to be debugged through a code monitoring unit when the code configuration file is updated; wherein the second code download signal carries the second code program;
in one embodiment, when the chip to be debugged receives the second code download signal, the chip to be debugged stops running the first code program and runs the second code program, and a third chip output signal corresponding to the first excitation signal is generated.
a2.2, when the code configuration file is not updated, continuously generating a downloading signal according to the last configuration.
To facilitate understanding of the debugging method of the chip simulation system provided in the foregoing embodiment, an application example of the debugging method of the chip simulation system is provided in the embodiment of the present invention, referring to a flow diagram of another debugging method of the chip simulation system shown in fig. 3, where the method mainly includes the following steps S302 to S314:
step S302: and receiving a monitoring instruction sent by the control terminal, and enabling each unit to monitor the corresponding target configuration file. The control terminal is a man-machine interaction interface and is used for controlling the working state of each module by selecting a start button, a pause button and an end button of each module in the man-machine interaction interface.
Step S304: and monitoring the excitation configuration file through the excitation monitoring unit, and sending an excitation signal to the chip to be debugged. The excitation configuration file is used for simulating the operation environment of the chip, when the actual working environment of the instrument changes, a changed signal is generated and input into the file (for example, the angle of a working device connected with the end of the excitation configuration file is inclined, a sensor in the device generates voltage, the generated voltage is sent to the chip in the device, and the chip in the device translates the voltage into a digital signal through operation and stores the signal into the excitation configuration file).
Step S306: and sending a code downloading signal to the chip to be debugged based on the code configuration file through the code monitoring unit. The code downloading signal carries a code program, and the code program is sent to the chip to be debugged and updates the program running in the chip to be debugged.
Step S308: and the chip to be debugged receives the code downloading signal, and runs the code program through the chip to be debugged to generate a chip output signal corresponding to the excitation signal. The chip to be debugged receives a code download signal and a last configuration change/receives an excitation signal and a last configuration change, and new output signals are generated and are different.
Step S310: and performing signal analysis processing on the chip output signal through the signal analysis monitoring unit based on the signal analysis configuration file to determine a signal to be analyzed. Wherein the signal analysis profile is used to determine the type of signal captured (such as capture length signal, accuracy signal, voltage signal, current signal, etc.).
Step S312: and carrying out signal analysis processing on the signal to be analyzed to obtain a chip debugging result. And printing the chip debugging result obtained in the chip debugging process to a display in real time to obtain the debugging result change condition of the simulation chip.
In summary, the present invention can ensure the normal operation of the chip emulation system, and simultaneously, control the plurality of units of the chip emulation system respectively through the control terminal, and further control each unit to monitor the corresponding target configuration file, thereby completing the debugging of the chip emulation system in the operation process, significantly reducing the time cost of the debugging of the chip emulation system, and also simulating a more real chip use environment, thereby improving the debugging precision of the chip emulation system.
As for the debugging method of the chip simulation system provided in the foregoing embodiment, an embodiment of the present invention provides a debugging apparatus for a chip simulation system, where the debugging apparatus is applied to a chip simulation system, and the chip simulation system is connected to a control terminal, as shown in fig. 4, a schematic structural diagram of the debugging apparatus for a chip simulation system is provided, and the debugging apparatus includes the following components:
a configuration file query module 402, configured to, when receiving a monitoring instruction sent by a control terminal, read a target configuration file corresponding to the monitoring control instruction; wherein the target profile comprises one or more of an excitation profile, a code profile, and a signal analysis profile;
the chip debugging module 404 is used for controlling a chip to be debugged in the chip simulation system and operating according to the excitation configuration file and the code configuration file to obtain a chip output signal;
and the signal analysis module 406 is used for performing signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain a chip debugging result.
The data processing device provided by the embodiment of the application can finish debugging the chip simulation system in the running process of the chip simulation system by changing the corresponding excitation file, can obviously reduce the time cost of debugging the chip simulation system, and can simulate a more real chip use environment, thereby improving the debugging precision of the chip simulation system.
In one embodiment, when the step of controlling the chip to be debugged in the chip simulation system to obtain the chip output signal according to the excitation configuration file and the code configuration file is performed, the chip debugging module 404 is further configured to: sending a first excitation signal to a chip to be debugged based on an excitation configuration file through an excitation monitoring unit; sending a first code downloading signal to a chip to be debugged based on the code configuration file through a code monitoring unit; wherein, the first code download signal carries a first code program; when the chip to be debugged receives the first code download signal, the first code program is operated through the chip to be debugged, and a first chip output signal corresponding to the first excitation signal is generated.
In an embodiment, the chip debugging module 404 is further configured to: monitoring whether an excitation configuration file is updated or not through an excitation monitoring unit in the process that a chip to be debugged runs a first code program, and sending an updated second excitation signal to the chip to be debugged through the excitation monitoring unit when the excitation configuration file is updated; and when the chip to be debugged receives the second excitation signal, the first code program is rerun through the chip to be debugged, and a second chip output signal corresponding to the second excitation signal is generated.
In an embodiment, the chip debugging module 404 is further configured to: monitoring whether a code configuration file is updated or not through a code monitoring unit in the process that a chip to be debugged runs a first code program, and monitoring a second code downloading signal which is sent to the chip to be debugged after updating through the code monitoring unit when the code configuration file is updated; wherein the second code download signal carries the second code program; and when the chip to be debugged receives the second code downloading signal, the chip to be debugged stops running the first code program and runs the second code program to generate a third chip output signal corresponding to the first excitation signal.
In one embodiment, when performing the step of performing signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain the chip debugging result, the chip debugging module 404 is further configured to: the method comprises the steps of carrying out signal analysis processing on chip output signals based on a signal analysis configuration file to obtain a chip debugging result, and comprises the following steps: and determining a signal to be analyzed from the signal output by the chip through the signal analysis monitoring unit based on the signal analysis configuration file, and performing signal analysis processing on the signal to be analyzed to obtain a chip debugging result.
In one embodiment, the excitation monitoring unit is connected with the control terminal through a first interface, the code monitoring unit is connected with the control terminal through a second interface, and the signal analysis monitoring unit is connected with the control terminal through a third interface; when receiving a monitoring instruction sent by the control terminal, and when reading a target configuration file corresponding to the monitoring control instruction, the chip debugging module 404 is further configured to: when the first interface receives a monitoring instruction sent by the control terminal, the excitation monitoring unit reads the excitation configuration file; or, when the second interface receives a monitoring instruction sent by the control terminal, the code configuration file is read through the code monitoring unit; or when the third interface receives a monitoring instruction sent by the control terminal, the signal analysis monitoring unit reads the signal analysis configuration file.
In an embodiment, the chip debugging module 404 is further configured to: when a control instruction sent by a control terminal is received, controlling the monitoring module and/or the chip to be debugged to execute an action corresponding to the control instruction; the control instruction comprises a pause instruction and/or a stop instruction, the pause instruction is used for indicating the monitoring module and/or the chip to be debugged to stop working and storing the working state to the target configuration file, and the stop instruction is used for indicating the monitoring module and/or the chip to be debugged to stop working and restoring the target configuration file to a default value.
The device provided by the embodiment of the present invention has the same implementation principle and technical effect as the method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the method embodiments without reference to the device embodiments.
The embodiment of the invention provides electronic equipment, which particularly comprises a processor and a storage device, wherein the processor is used for processing a plurality of data files; the storage means has stored thereon a computer program which, when executed by the processor, performs the method of any of the above described embodiments.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, where the electronic device 100 includes: the device comprises a processor 50, a memory 51, a bus 52 and a communication interface 53, wherein the processor 50, the communication interface 53 and the memory 51 are connected through the bus 52; the processor 50 is used to execute executable modules, such as computer programs, stored in the memory 51.
The memory 51 may include a high-speed Random Access Memory (RAM) and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 53 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like can be used.
The bus 52 may be an ISA bus, a PCI bus, an EISA bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 5, but this does not indicate only one bus or one type of bus.
The memory 51 is used for storing a program, the processor 50 executes the program after receiving an execution instruction, and the method performed by the apparatus defined by the flow program disclosed in any of the foregoing embodiments of the present invention may be applied to the processor 50, or implemented by the processor 50.
The processor 50 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 50. The Processor 50 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in ram, flash, rom, prom, or eprom, registers, etc. as is well known in the art. The storage medium is located in the memory 51, and the processor 50 reads the information in the memory 51 and completes the steps of the method in combination with the hardware thereof.
The computer program product of the readable storage medium provided in the embodiment of the present invention includes a computer readable storage medium storing a program code, where instructions included in the program code may be used to execute the method described in the foregoing method embodiment, and specific implementation may refer to the foregoing method embodiment, which is not described herein again.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present invention or a part thereof which substantially contributes to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the following descriptions are only illustrative and not restrictive, and that the scope of the present invention is not limited to the above embodiments: those skilled in the art can still make modifications or changes to the embodiments described in the foregoing embodiments, or make equivalent substitutions for some features, within the scope of the disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A debugging method of a chip simulation system is characterized in that the method is applied to the chip simulation system, the chip simulation system is connected with a control terminal, and the method comprises the following steps:
when a monitoring instruction sent by the control terminal is received, reading a target configuration file corresponding to the monitoring control instruction; wherein the target profile comprises one or more of an excitation profile, a code profile, and a signal analysis profile;
controlling a chip to be debugged in the chip simulation system, and operating according to the excitation configuration file and the code configuration file to obtain a chip output signal;
and performing signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain a chip debugging result.
2. The method according to claim 1, wherein the chip emulation system comprises a snooping module connected with the chip to be debugged, wherein the snooping module comprises an excitation snooping unit and a code snooping unit;
the step of controlling the chip to be debugged in the chip simulation system and obtaining the chip output signal according to the excitation configuration file and the code configuration file comprises the following steps:
sending a first excitation signal to the chip to be debugged based on the excitation configuration file through the excitation monitoring unit;
sending a first code downloading signal to the chip to be debugged based on the code configuration file through the code monitoring unit; wherein, the first code download signal carries a first code program;
and when the chip to be debugged receives the first code downloading signal, running the first code program through the chip to be debugged to generate a first chip output signal corresponding to the first excitation signal.
3. The method of claim 2, further comprising:
monitoring whether the excitation configuration file is updated or not through the excitation monitoring unit in the process that the chip to be debugged runs the first code program, and sending an updated second excitation signal to the chip to be debugged through the excitation monitoring unit when the excitation configuration file is updated;
when the chip to be debugged receives the second excitation signal, the first code program is operated again through the chip to be debugged, and a second chip output signal corresponding to the second excitation signal is generated.
4. The method of claim 2, further comprising:
monitoring whether the code configuration file is updated or not through the code monitoring unit in the process that the chip to be debugged runs the first code program, and monitoring a second code downloading signal after updating is sent to the chip to be debugged through the code monitoring unit when the code configuration file is updated; wherein the second code download signal carries a second code program;
and when the chip to be debugged receives the second code downloading signal, stopping running the first code program through the chip to be debugged and running the second code program to generate a third chip output signal corresponding to the first excitation signal.
5. The method of claim 2, wherein the listening module further comprises a signal analysis listening unit;
the step of performing signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain a chip debugging result includes:
and determining a signal to be analyzed from the chip output signals through the signal analysis monitoring unit based on the signal analysis configuration file, and performing signal analysis processing on the signal to be analyzed to obtain a chip debugging result.
6. The method according to claim 5, wherein the excitation monitoring unit is connected to the control terminal through a first interface, the code monitoring unit is connected to the control terminal through a second interface, and the signal analysis monitoring unit is connected to the control terminal through a third interface;
the step of reading the target configuration file corresponding to the monitoring control instruction when receiving the monitoring instruction sent by the control terminal comprises the following steps:
when the first interface receives a monitoring instruction sent by the control terminal, an excitation configuration file is read through the excitation monitoring unit;
or, when the second interface receives a monitoring instruction sent by the control terminal, the code configuration file is read through the code monitoring unit;
or, when the third interface receives a monitoring instruction sent by the control terminal, the signal analysis monitoring unit reads a signal analysis configuration file.
7. The method according to any one of claims 1-6, further comprising:
when a control instruction sent by the control terminal is received, controlling the monitoring module and/or the chip to be debugged to execute an action corresponding to the control instruction;
the control instruction comprises a pause instruction and/or a stop instruction, the pause instruction is used for indicating the monitoring module and/or the chip to be debugged to stop working and saving the working state to the target configuration file, and the stop instruction is used for indicating the monitoring module and/or the chip to be debugged to stop working and restoring the target configuration file to a default value.
8. The debugging device of a chip simulation system is characterized in that the device is applied to the chip simulation system, the chip simulation system is connected with a control terminal, and the device comprises:
the configuration file query module is used for reading a target configuration file corresponding to the monitoring control instruction when receiving the monitoring instruction sent by the control terminal; wherein the target profile comprises one or more of an excitation profile, a code profile, and a signal analysis profile;
the chip debugging module is used for controlling a chip to be debugged in the chip simulation system and operating according to the excitation configuration file and the code configuration file to obtain a chip output signal;
and the signal analysis module is used for carrying out signal analysis processing on the chip output signal based on the signal analysis configuration file to obtain a chip debugging result.
9. A server comprising a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement the method of any one of claims 1 to 7.
10. A computer-readable storage medium having computer-executable instructions stored thereon which, when invoked and executed by a processor, cause the processor to perform the method of any of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210422132.8A CN114780402A (en) | 2022-04-21 | 2022-04-21 | Debugging method and device of chip simulation system and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210422132.8A CN114780402A (en) | 2022-04-21 | 2022-04-21 | Debugging method and device of chip simulation system and server |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114780402A true CN114780402A (en) | 2022-07-22 |
Family
ID=82431838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210422132.8A Pending CN114780402A (en) | 2022-04-21 | 2022-04-21 | Debugging method and device of chip simulation system and server |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114780402A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115293080A (en) * | 2022-09-22 | 2022-11-04 | 沐曦科技(北京)有限公司 | Chip debugging system based on trace file |
-
2022
- 2022-04-21 CN CN202210422132.8A patent/CN114780402A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115293080A (en) * | 2022-09-22 | 2022-11-04 | 沐曦科技(北京)有限公司 | Chip debugging system based on trace file |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109800159B (en) | Program debugging method, program debugging device, terminal device, and storage medium | |
| JP7270764B2 (en) | artificial intelligence chip verification | |
| CN110580226B (en) | Object code coverage rate testing method, system and medium for operating system level program | |
| CN107783898B (en) | Test method and test equipment for mobile application | |
| US7533302B2 (en) | Trace and debug method and system for a processor | |
| CN110704304B (en) | Application program testing method and device, storage medium and server | |
| US9208451B2 (en) | Automatic identification of information useful for generation-based functional verification | |
| CN112286825A (en) | Screen testing method and device for intelligent cabin and electronic equipment | |
| CN109634822B (en) | Function time consumption statistical method and device, storage medium and terminal equipment | |
| US20200183809A1 (en) | Usage amount monitoring method and monitoring unit of electronic control unit for vehicle | |
| CN111427771A (en) | Code coverage rate analysis method, equipment, server and readable storage medium | |
| JP2022522474A (en) | Machine learning-based anomaly detection for embedded software applications | |
| CN114780402A (en) | Debugging method and device of chip simulation system and server | |
| CN110580220A (en) | method for measuring execution time of code segment and terminal equipment | |
| CN105912467B (en) | Performance test method and device | |
| EP3486811A1 (en) | Simulation device, simulation system, simulation method and simulation program | |
| CN111949510B (en) | Test processing method, device, electronic equipment and readable storage medium | |
| US20110022373A1 (en) | Model checking of liveness property in a phase abstracted model | |
| CN115964237A (en) | Method and device for testing functions and performance of Central Processing Unit (CPU) | |
| CN112527571B (en) | CPU instruction set coverage rate calculation method and device | |
| CN113342600A (en) | Method and device for monitoring program dependent plug-in | |
| CN118093446B (en) | Heterogeneous program debugging method, system, device, electronic equipment and storage medium | |
| CN115510782B (en) | Method for locating verification errors, electronic device and storage medium | |
| CN115032971B (en) | Updating method and device of vehicle diagnosis equipment and server | |
| CN109542793B (en) | Program performance analysis method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |