CN115277297A - Portable MVB bus analyzer and bus debugging method - Google Patents
Portable MVB bus analyzer and bus debugging method Download PDFInfo
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- CN115277297A CN115277297A CN202210916001.5A CN202210916001A CN115277297A CN 115277297 A CN115277297 A CN 115277297A CN 202210916001 A CN202210916001 A CN 202210916001A CN 115277297 A CN115277297 A CN 115277297A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40026—Details regarding a bus guardian
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/40293—Bus for use in transportation systems the transportation system being a train
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Abstract
The invention relates to a portable MVB bus analyzer and an analysis method, wherein the analyzer comprises: the data analysis unit is connected with the MVB bus and used for carrying out signal conversion between the MVB bus and the analyzer; the FPGA is used for analyzing the bus data sent by the data analysis unit and carrying out time sequence processing on the bus data; ARM, interior: the GPIO module is used for bidirectionally transmitting ARM and FPGA data and issuing a control command to the FPGA; the EXTI module is used for sending an interrupt signal to the ARM by the FPGA; a master management unit for managing the bus; the working thread and scheduling module is connected with the main management unit and used for carrying out data interaction with an upper computer; the interrupt processing unit is used for carrying out synchronization and frame processing on the analyzer; and the power supply unit is used for supplying power to the FPGA and the ARM. The invention can not only analyze the bus data and realize the total monitoring, but also accurately, conveniently and flexibly send the MVB bus data to carry out bus management.
Description
Technical Field
The invention belongs to the technical field of rail transit, relates to a rail train communication technology, and particularly relates to a portable MVB bus analyzer and a bus debugging method.
Background
The MVB is widely applied to the field of rail transit at a high-speed communication rate and with excellent anti-interference capability, and the MVB still occupies a central position in train communication at present.
The conventional MVB adopts a bus type topological architecture, the MVB penetrates through the whole train, all vehicle controllers are connected in series, and all MVB devices are all mounted on one MVB bus. In this bus, there is one MVB master device CCU (generally called central control unit), and the rest are slave devices, and the transmission and reception scheduling of all data depends on the MVB master device management.
Due to the topology of the MVB bus and the characteristics of the main device, in the vehicle debugging process, the MVB of the whole vehicle needs to be adjusted and connected, and the function debugging of the CCU needs to be completed in advance. This results in a less efficient debugging process. Firstly, all communication devices are connected in series with the MVB of the whole vehicle, a repeater needs to be connected inside a carriage, and a vehicle end connector needs to be connected between the carriage and the carriage in a crossing mode. On the one hand, this serial communication architecture results in that all connections must be correct for debugging of the entire system. On the other hand, the transceiving of the MVB bus requires the unified scheduling of the CCU, and the CCU needs to run the control logic of the whole vehicle in addition to the communication scheduling, so that the transceiving of each port on the MVB is limited by the control logic, and the transceiving cannot be performed at will. Secondly, the CCU and the sub-equipment generally belong to different suppliers, and when the sub-equipment fails, the CCU end is required to be matched, and due to the existence of manufacturer barriers, the failure processing of the sub-equipment is not easy to be performed. And thirdly, the CCU is used as an independent system, belongs to core equipment of the MVB, is large in size and is not easy to carry and move, so that the CCU and the sub-equipment cannot be directly communicated under the condition that an MVB line is uncertain. Finally, the MVB protocol analyzers currently on the market only have bus data analysis (for example, an MVB protocol analyzer and a working method thereof disclosed in chinese patent application publication No. CN103684891A, an MVB protocol analysis device and a method disclosed in chinese patent application publication No. CN110830345A, a portable MVB protocol analysis device and an MVB data processing method disclosed in chinese patent publication No. CN 106341294B), but do not have a bus management function and cannot be used as a mode CCU master device.
Disclosure of Invention
The invention provides a portable MVB bus analyzer and a debugging method aiming at the problems that bus data can only be analyzed and bus management cannot be carried out when the existing MVB bus is debugged, the bus data can be analyzed, the total monitoring is realized, the MVB bus data can be accurately, conveniently and flexibly sent to carry out bus management, the problem that the conventional equipment can only monitor and cannot manage the bus is solved, the vehicle environment is not relied on, the point-to-point test can be independently carried out on each piece of sub-equipment, and the debugging efficiency is high.
In order to achieve the above object, the present invention provides a portable MVB bus analyzer, comprising:
the data analysis unit is connected with the MVB bus and is used for carrying out signal conversion between the MVB bus and the analyzer;
the FPGA is used for analyzing the bus data sent by the data analysis unit and performing time sequence processing on the bus data;
ARM, interior establishes:
the GPIO module is used for the data bidirectional transmission of the ARM and the FPGA and the ARM sends a control command to the FPGA;
the EXTI module is used for sending an interrupt signal to the ARM by the FPGA;
a primary management unit comprising: the device scanning module is used for checking whether the bus device is on line or not by sending a device scanning frame according to the state of the scanning bus device set in the upper computer configuration file when the analyzer is used as the main device, and sending the corresponding state to other devices through monitoring data; the master right transfer module is used for transferring the master right to other backup bus master devices by the current bus master device, and when the current bus master device transfers the master right to the other backup bus master devices, if the current bus master device or the backup bus master devices cannot accept authorization due to the device state, the current master device reserves the master right; the event arbitration module is used for the main equipment to sequentially inquire the events of each equipment in the address range of the equipment with the message capability, carry out state arbitration according to the state frame returned by each equipment and determine the subsequent behavior of each slave equipment;
the working thread and scheduling module is connected with the main management unit and used for performing data interaction with an upper computer and directly managing the analyzer;
the interrupt processing unit is used for synchronizing and processing frames of the analyzer after the ARM receives an interrupt signal sent by the EXTI module;
and the power supply unit is used for supplying power to the FPGA and the ARM.
Further, the upper computer is internally provided with:
a mode configuration module for selecting whether the analyzer is in a monitor mode or a CCU mode;
the data visualization module is used for displaying data acquired by the analyzer from the MVB bus in real time according to the port, the frame type, the sending time and the communication state;
the data sending module is used for directly writing the time interval of the MVB data to be sent into the analyzer through the PC end window, and the analyzer receives the instruction and then sends the instruction through the MVB bus;
and the CCU logic module loads the logic operated by the CCU to the ARM through the upper computer and simulates the logic operation through the ARM.
Further, an initialization module is further arranged in the ARM and used for initializing bus parameters according to the user configuration information of the analyzer when the analyzer is initialized, analyzing the initialized bus parameters and then sending the analyzed initialized bus parameters to the GPIO module, and the GPIO module sends the analyzed initialized bus parameters to the FPGA, and the FPGA initializes the MVB bus according to the initialized bus parameters.
Furthermore, a hardware interface module is also arranged in the ARM, the hardware interface module is connected between the ARM operating system and the GPIO module, and the hardware interface module is called to notify the FGPA after the ARM carries out main management, interrupt processing and initialization.
Furthermore, the analyzer further comprises a shell, and the data analysis unit, the FPGA, the ARM and the power supply unit are all arranged in the shell.
Preferably, the data analysis unit includes:
the bus interface module is connected with the MVB bus and is used for isolating and protecting the analyzer and the bus;
a frame transceiver connected to the bus interface module, the frame transceiver comprising:
the decoder is used for analyzing the single-ended signal and the digital signal received by the frame transceiver from the FPGA cache;
and the encoder is used for encoding the differential signals and the bus electric appliance signals received by the frame transceiver from the MVB and sending the encoded differential signals and the bus electric appliance signals to the FPGA for caching.
Preferably, the FPGA is internally provided with:
the protocol analysis module is used for carrying out frame identification on data collected on an MVB bus sent by the frame transceiver according to the MVB bus standard and sending effective data to the ARM; the frame identification comprises identification and data extraction of a starting delimiter, frame data, a check sequence and an ending delimiter;
the state control module is used for analyzing and sending the bus state information to the ARM according to the state frame data analyzed by the protocol analysis module;
and the bus management module is used for carrying out time sequence processing on MVB bus data sent by the frame transceiver according to the MVB bus standard and controlling the transceiving of the data according to the time sequence.
Preferably, the power supply unit includes:
the USB interface module is connected with a USB interface of the upper computer, and the USB interface of the upper computer provides a 5V power supply for the USB interface module;
and the DC/DC module is connected with the USB interface module, converts a 5V power supply provided by the USB interface module by the upper computer into a voltage level required by the FPGA and the ARM, and supplies power for the FPGA and the ARM.
Preferably, the GPIO module is provided with:
the data signal interface is used for the data bidirectional transmission of the ARM and the FPGA;
and the control signal interface is used for transmitting a control command to the FPGA by the ARM.
Preferably, the interrupt processing module includes:
a synchronous processing module for analyzer status and configuration word changes;
and the frame processing module is used for processing and responding MVB link data and calling the main management unit to perform bus management under the condition that the analyzer is used as the main device.
In order to achieve the above object, the present invention further provides an MVB bus analysis method, which adopts the portable MVB bus analyzer, and comprises the following specific steps:
when the upper computer sets the analyzer to be in a master device mode, the upper computer configures bus management parameters to the analyzer, the analyzer replaces a CCU (central control unit) to serve as a master device to manage bus data, if the slave device is required to send data, the upper computer configures MVB port parameters and control instructions of the slave device to be sent to the analyzer, the analyzer sends the control instructions to corresponding slave devices, the slave devices send self information to MVB buses through MVB ports and send the information to the analyzer through MVB buses, the analyzer analyzes the bus data and sends the bus data to the upper computer to display the bus data, and the upper computer counts bus communication quality;
when the upper computer sets the analyzer to be in a monitoring mode, the slave device sends self information to the MVB through the MVB port, the information is sent to the analyzer through the MVB, the analyzer analyzes bus data and sends the bus data to the upper computer to display the bus data, and the upper computer counts bus communication quality.
Compared with the prior art, the invention has the advantages and positive effects that:
(1) The invention adopts an FPGA + ARM architecture and is provided with a main management unit, so that the CCU function can be simulated, the MVB bus analysis, data transmission and bus management can be realized, the MVB bus data can be accurately, conveniently and flexibly transmitted under the condition that a network is not established, and the problem that the conventional analyzer can only monitor and cannot manage the bus is solved.
(2) The portable power supply device is simple in structure, small in size and convenient to carry, the whole device is powered by USB (universal serial bus), the environment of a vehicle is not depended on, DC/DC isolated power supply is adopted, the power utilization efficiency is improved, and the rated power of the whole device is 2W.
(3) The upper computer is provided with the CCU logic module, the logic of the CCU operation is loaded to the ARM through the upper computer, the ARM simulates the logic operation, the optional function and the optional communication of the whole vehicle can be simulated, the point-to-point test of each sub-device can be independently carried out, the problem that each sub-device must depend on a network line and a debugging mode of the CCU is solved, and the debugging efficiency is improved.
(4) The invention accesses the upper computer through the standard Ethernet protocol, displays the data of the real-time receiving slave equipment through the upper computer, and does not need to additionally access equipment such as a display screen and the like.
(5) After the system is accessed to the MVB network, the system can automatically monitor bus data, analyzes the bus data according to a bus protocol, uploads the data such as the state of a bus port, port data, bus occupancy rate, packet loss rate and the like to an upper computer of a PC (personal computer) end in real time through the Ethernet, simulates port data receiving and sending in real time through the upper computer, can be configured to be in a monitoring mode, monitors the bus data and communication quality, and solves the problem of unstable communication fault positioning in the debugging process.
Drawings
Fig. 1 is a block diagram of a portable MVB bus analyzer according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of a portable MVB bus analyzer according to an embodiment of the present invention;
fig. 3 is a flowchart of an MVB bus analysis method according to an embodiment of the present invention.
In the figure, 1, an MVB bus, 2, an analyzer, 3, an FPGA,4, an ARM,5, an upper computer, 6, a DC/DC module, 71, a bus interface module, 72 and a frame transceiver.
Detailed Description
The invention is described in detail below by way of exemplary embodiments. It should be understood, however, that elements, structures and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
Example 1: referring to fig. 1 and 2, the present embodiment provides a portable MVB bus analyzer, including:
a data analysis unit connected to the MVB bus 1 and configured to perform signal conversion between the MVB bus 1 and the analyzer 2;
the FPGA 3 is used for analyzing the bus data sent by the data analysis unit and performing time sequence processing on the bus data;
the GPIO module is used for the data bidirectional transmission of the ARM and the FPGA and the ARM sends a control command to the FPGA;
the EXTI module is used for sending an interrupt signal to the ARM by the FPGA;
a primary management unit comprising: the device scanning module is used for checking whether the bus device is on line or not by sending a device scanning frame according to the state of the scanning bus device set in the upper computer configuration file when the analyzer is used as the main device, and sending the corresponding state to other devices through monitoring data; the master right transfer module is used for transferring the master right to other backup bus master devices by the current bus master device, and when the current bus master device transfers the master right to the other backup bus master devices, if the backup bus master device or the backup bus master device does not receive authorization due to the device state, the current master device reserves the master right; the event arbitration module is used for the master equipment to sequentially inquire the events of each equipment in the address range of the equipment with the message capability, carry out state arbitration according to the state frame returned by each equipment and determine the subsequent behaviors of each slave equipment;
the working thread and scheduling module is connected with the main management unit, is connected with the upper computer through the Ethernet and is used for carrying out data interaction with the upper computer and directly managing the analyzer;
the interrupt processing unit is used for synchronizing and frame processing the analyzer after the ARM receives the interrupt signal sent by the EXTI module;
and the power supply unit is used for supplying power to the FPGA and the ARM.
With continued reference to fig. 1, the data analysis unit includes:
the bus interface module 71 is connected with the MVB bus 1 and used for isolating and protecting the analyzer 2 and the MVB bus 1;
a frame transceiver 72, connected to the bus interface module 71, including: the decoder is used for analyzing the single-ended signal and the digital signal received by the frame transceiver from the FPGA cache; and the encoder is used for encoding the differential signals and the bus electric appliance signals received by the frame transceiver from the MVB and sending the encoded differential signals and the bus electric appliance signals to the FPGA for caching.
Specifically, in this embodiment, the bus interface module is provided with a transformer and a bus protection device, where the transformer realizes isolation between the analyzer and the MVB bus, and the bus protection device (e.g., a fuse) realizes protection between the analyzer and the MVB bus.
With continued reference to fig. 2, the FPGA is internally provided with:
the protocol analysis module is used for carrying out frame identification on data collected on an MVB bus sent by the frame transceiver according to the MVB bus standard and sending effective data to the ARM; the frame identification comprises identification and data extraction of a starting delimiter, frame data, a check sequence and an ending delimiter;
the state control module is used for analyzing and sending the bus state information to the ARM according to the state frame data analyzed by the protocol analysis module;
and the bus management module is used for carrying out time sequence processing on the MVB bus data sent by the frame transceiver according to the MVB bus standard and controlling the transceiving of the data according to the time sequence.
Specifically, the GPIO module is provided with:
the data signal interface is used for the data bidirectional transmission of the ARM and the FPGA;
and the control signal interface is used for transmitting a control command to the FPGA by the ARM.
Specifically, the interrupt processing module includes:
a synchronous processing module for analyzer status and configuration word changes;
and the frame processing module is used for processing and responding MVB link data (including the process data, the message data and the monitoring data) and calling the main management unit to perform bus management under the condition that the analyzer is used as the main device.
Specifically, the upper computer is internally provided with:
a mode configuration module for selecting whether the analyzer is in a monitor mode or a CCU mode;
the data visualization module is used for displaying the data acquired by the analyzer from the MVB bus in real time according to the port, the frame type, the sending time and the communication state;
the data sending module is used for directly writing the time interval of the MVB data to be sent into the analyzer through the PC end window, and the analyzer sends the time interval of the MVB data through the MVB bus after receiving the command;
and the CCU logic module loads the logic operated by the CCU to the ARM through the upper computer and simulates the logic operation through the ARM.
With continued reference to fig. 1, the power supply unit includes:
the USB interface module is connected with a USB interface of the upper computer 5, and the USB interface of the upper computer 5 provides a 5V power supply for the USB interface module;
and the DC/DC module 6 is connected with the USB interface module, converts a 5V power supply provided by the USB interface module by the upper computer 5 into a voltage grade (such as 3.3V, 1.8V and the like) required by the FPGA and the ARM, and supplies power for the FPGA and the ARM.
With reference to fig. 2, in a specific embodiment, an initialization module is further disposed in the ARM, and is configured to initialize the bus parameters according to the analyzer user configuration information when the analyzer is initialized, analyze the initialization bus parameters, send the analyzed initialization bus parameters to the GPIO module, and send the analyzed initialization bus parameters to the FPGA by the GPIO module, where the FPGA initializes the MVB bus according to the initialization bus parameters. Specifically, the initialization bus parameters specifically include information such as the number of devices of the MVB bus, the address of a port, the data length, and the training period. And selecting according to actual requirements.
Specifically, with reference to fig. 2, in a specific embodiment, a hardware interface module is further disposed in the ARM, and the hardware interface module is connected between the ARM operating system and the GPIO module, and the hardware interface module is called to notify the FGPA after the ARM performs main management, interrupt processing, and initialization. It should be noted that the hardware interface module is an intermediate layer between the ARM operating system and the GPIO module, pins of the GPIO module in the same group as the ARM terminal are connected to the same register, and similar functions are allocated in the same group when the pin roles are allocated, so that the operating speed can be greatly increased.
Specifically, the ARM is provided with an Ethernet interface, one end of the Ethernet interface is provided with a working thread and a scheduling module, and the other end of the Ethernet interface is connected with an upper computer through the Ethernet. In this embodiment, the ethernet structure uses a standard RJ45 connector. It should be noted that, the working thread and the scheduling module perform data interaction with the upper computer through the ethernet, so as to implement direct management of the analyzer, and enable a user to directly configure the MVB bus analyzer flexibly through the visual upper computer.
Specifically, the analyzer further comprises a shell, and the data analysis unit, the FPGA, the ARM and the power supply unit are all arranged in the shell. In this embodiment, the casing adopts the plastics shell, and length and width height is 100 × 55 × 35mm, has miniaturized portable characteristics.
Specifically, the FPGA adopts Xilinx FPGA. The ARM adopts an ARM A8 processor with low power consumption, an RTOS (remote terminal operating system) is embedded, the embedded RTOS supports thread management and thread synchronization, a working thread is a top-priority thread running on the ARM operating system, and the working thread provides a system kernel and a device driver to realize the scheduling of software functions. The USB interface module is a Type C interface, is compatible with USB2.0 and USB3.0, and adopts an embedded low-power design. The analyzer adopts a DC/DC module to isolate power supply, so that the power utilization efficiency is improved, and the rated power consumption of the whole analyzer is 2W.
When the MVB bus analyzer analyzes through the embodiment, the analyzer is set to be in a main device mode through the upper computer (when the main device mode is adopted, the whole analyzer has the function of MVB bus management and is not a part of the analyzer), a corresponding MVB port address, a port size and a refreshing period are input into the analyzer, data to be sent by a designated port are set, and therefore the CCU can be replaced to be used as main equipment to conduct bus data management. The analyzer can monitor data transmission and reception of the slave device in the mode that the analyzer is the master device, can receive all data of the bus, and can observe data transmission. Therefore, the analyzer can be directly interconnected with the MVB slave equipment in a point-to-point mode, data to be sent to the slave equipment by the CCU are directly sent to the slave equipment through the analyzer, the data of the slave equipment are received in real time, and then the data are sent to an upper computer through an Ethernet interface arranged by an ARM and displayed. For example: in a certain section of motor car carriage, the MVB function of CCU debugs the door and the function of air conditioner under the condition that does not transfer, adopts this embodiment the analysis appearance, with this section of carriage of this section of bus access of MVB bus access with the analysis appearance. Set up this analysis appearance into the master unit mode through the host computer, dispose this section carriage door controller and air conditioner controller's MVB port, data information to the analysis appearance through the host computer to send the switching instruction of door, the instruction that adjusts the temperature of air conditioner for corresponding controller through the analysis appearance, door and air conditioning system carry out corresponding action after receiving the instruction, and give the analysis appearance with self information transmission, just so realized the communication function analysis of MVB subset under the no CCU condition.
The above-mentioned analysis appearance of this embodiment, simple structure, it is small, portable adopts FPGA + ARM architectural design, establish main management unit in the ARM, make the analysis appearance have MVB bus management's function, not only can realize MVB bus analysis, data transmission, bus management, can also simulate the CCU function, in the condition that the network is not established, accurate convenient nimble MVB bus data of sending, the problem of equipment can only monitor can not manage the bus in the past has been solved. And point-to-point testing can be performed on each MVB sub-device independently, so that the debugging efficiency is improved. The analyzer is connected to the upper computer through a standard Ethernet protocol, and bus data can be displayed without additionally connecting devices such as a display screen.
Example 2: referring to fig. 3, the present embodiment provides an MVB bus analysis method, which adopts the portable MVB bus analyzer, and includes the following specific steps:
when the upper computer sets the analyzer to be in a master device mode, the upper computer configures bus management parameters to the analyzer, the analyzer replaces a CCU (central control unit) to serve as a master device to manage bus data, if the slave device is required to send data, the upper computer configures MVB port parameters and control instructions of the slave device to be sent to the analyzer, the analyzer sends the control instructions to corresponding slave devices, the slave devices send self information to MVB buses through MVB ports and send the information to the analyzer through MVB buses, the analyzer analyzes the bus data and sends the bus data to the upper computer to display the bus data, and the upper computer counts bus communication quality;
when the upper computer sets the analyzer to be in a monitoring mode, the slave device sends self information to the MVB through the MVB port, the information is sent to the analyzer through the MVB, the analyzer analyzes bus data and sends the bus data to the upper computer to display the bus data, and the upper computer counts bus communication quality.
The analysis method is based on an analyzer capable of realizing a bus management function, the upper computer can load the logic of CCU operation to the ARM through the upper computer, the ARM simulates the logic operation, can simulate any function and any communication of the whole automobile, can independently test each sub-device in a point-to-point mode, solves the problem that each sub-device must depend on a network line and a debugging mode of the CCU, and improves the debugging efficiency. The analyzer is connected to the upper computer through a standard Ethernet protocol, and bus data can be displayed without additionally connecting equipment such as a display screen.
The above-described embodiments are intended to illustrate rather than to limit the invention, and any modifications and variations of the present invention are possible within the spirit and scope of the claims.
Claims (10)
1. A portable MVB bus analyzer, comprising:
the data analysis unit is connected with the MVB bus and is used for carrying out signal conversion between the MVB bus and the analyzer;
the FPGA is used for analyzing the bus data sent by the data analysis unit and carrying out time sequence processing on the bus data;
ARM, interior:
the GPIO module is used for the data bidirectional transmission of the ARM and the FPGA and the ARM sends a control command to the FPGA;
the EXTI module is used for sending an interrupt signal to the ARM by the FPGA;
a primary management unit comprising:
the device scanning module is used for checking whether the bus device is on line or not by sending a device scanning frame according to the state of the scanning bus device set in the upper computer configuration file when the analyzer is used as the main device, and sending the corresponding state to other devices through monitoring data;
the master right transfer module is used for transferring the master right to other backup bus master devices by the current bus master device, and when the current bus master device transfers the master right to the other backup bus master devices, if the current bus master device or the backup bus master devices cannot accept authorization due to the device state, the current master device reserves the master right;
the event arbitration module is used for the master equipment to sequentially inquire the events of each equipment in the address range of the equipment with the message capability, carry out state arbitration according to the state frame returned by each equipment and determine the subsequent behaviors of each slave equipment;
the working thread and scheduling module is connected with the main management unit and used for performing data interaction with an upper computer and directly managing the analyzer;
the interrupt processing unit is used for synchronizing and processing frames of the analyzer after the ARM receives an interrupt signal sent by the EXTI module;
and the power supply unit is used for supplying power to the FPGA and the ARM.
2. The portable MVB bus analyzer of claim 1, wherein the upper computer is internally provided with:
a mode configuration module for selecting whether the analyzer is in a monitor mode or a CCU mode;
the data visualization module is used for displaying data acquired by the analyzer from the MVB bus in real time according to the port, the frame type, the sending time and the communication state;
the data sending module is used for directly writing the time interval of the MVB data to be sent into the analyzer through the PC end window, and the analyzer sends the time interval of the MVB data through the MVB bus after receiving the command;
and the CCU logic module loads the logic operated by the CCU to the ARM through the upper computer and simulates the logic operation through the ARM.
3. The portable MVB bus analyzer of claim 2, wherein the ARM is further provided with an initialization module, and the initialization module is configured to initialize the bus parameters according to the configuration information of the analyzer user when the analyzer is initialized, analyze the initialized bus parameters, send the analyzed initialized bus parameters to the GPIO module, and send the analyzed initialized bus parameters to the FPGA, and the FPGA initializes the MVB bus according to the initialized bus parameters.
4. The portable MVB bus analyzer of claim 3, wherein a hardware interface module is further disposed in the ARM, the hardware interface module is connected between the ARM operating system and the GPIO module, and the hardware interface module is called to notify the FGPA after the ARM performs the main management, the interrupt processing and the initialization.
5. The portable MVB bus analyzer of any of claims 1 to 4, wherein the data analysis unit comprises:
the bus interface module is connected with the MVB and used for isolating and protecting the analyzer and the MVB;
a frame transceiver connected to the bus interface module, the frame transceiver comprising:
the decoder is used for analyzing the single-ended signal and the digital signal which are received by the frame transceiver from the FPGA cache;
and the encoder is used for encoding the differential signals and the bus electric appliance signals received by the frame transceiver from the MVB and sending the encoded differential signals and the bus electric appliance signals to the FPGA for caching.
6. The portable MVB bus analyzer of claim 5, wherein the FPGA has built therein:
the protocol analysis module is used for carrying out frame identification on data collected on the MVB bus sent by the frame transceiver according to the MVB bus standard and sending effective data to the ARM; the frame identification comprises identification and data extraction of a starting delimiter, frame data, a check sequence and an ending delimiter;
the state control module is used for analyzing and sending the bus state information to the ARM according to the state frame data analyzed by the protocol analysis module;
and the bus management module is used for carrying out time sequence processing on the MVB bus data sent by the frame transceiver according to the MVB bus standard and controlling the transceiving of the data according to the time sequence.
7. The portable MVB bus analyzer of any of claims 1 to 4, wherein the power supply unit comprises:
the USB interface module is connected with a USB interface of the upper computer, and the USB interface of the upper computer provides a 5V power supply for the USB interface module;
and the DC/DC module is connected with the USB interface module, converts a 5V power supply provided by the USB interface module by the upper computer into a voltage level required by the FPGA and the ARM, and supplies power for the FPGA and the ARM.
8. The portable MVB bus analyzer of any one of claims 1 to 4, wherein the GPIO module is provided with:
the data signal interface is used for the data bidirectional transmission of the ARM and the FPGA;
and the control signal interface is used for transmitting a control command to the FPGA by the ARM.
9. The portable MVB bus analyzer of any of claims 1-4, wherein the interrupt handling module comprises:
a synchronous processing module for analyzer status and configuration word changes;
and the frame processing module is used for processing and responding MVB link data and calling the main management unit to perform bus management under the condition that the analyzer is used as the main device.
10. A MVB bus analysis method using the portable MVB bus analyzer according to any one of claims 2 to 9, comprising the following specific steps:
when the upper computer sets the analyzer to be in a master device mode, the upper computer configures bus management parameters to the analyzer, the analyzer replaces a CCU (central control unit) to serve as a master device to manage bus data, if the slave device is required to send data, the upper computer configures MVB port parameters and control instructions of the slave device to be sent to the analyzer, the analyzer sends the control instructions to corresponding slave devices, the slave devices send self information to MVB buses through MVB ports and send the information to the analyzer through MVB buses, the analyzer analyzes the bus data and sends the bus data to the upper computer to display the bus data, and the upper computer counts bus communication quality;
when the upper computer sets the analyzer to be in a monitoring mode, the slave device sends self information to the MVB through the MVB port, the information is sent to the analyzer through the MVB, the bus data are analyzed and sent to the upper computer through the MVB, the bus data are displayed by the analyzer, and the upper computer counts bus communication quality.
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| CN114884766A (en) * | 2022-03-29 | 2022-08-09 | 机械工业仪器仪表综合技术经济研究所 | Device for realizing integration of various industrial buses and 5G communication |
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