CN103513596A - MVB management function implementation system based on ARM - Google Patents

Abstract

The invention relates to an MVB management function implementation system based on an ARM. The MVB management function implementation system comprises a hardware interface and abstraction layer, a master control module, an interrupt processing module and a bus management module, wherein the hardware interface and abstraction layer is used as a channel for communication between the ARM and an FPGA; the master control module is used for starting an MVB board card, configuring an external interrupt register, hooking an interrupt processing routine and controlling an indicator light to display and report the operating state; the interrupt processing module is used for processing and responding different hardware interrupts from the FPGA; the bus management module is used for achieving the functions of master equipment scanning, sovereignty transferring, event arbitration and the like of a bus on the basis of the interrupt processing module. The MVB management function implementation system serves as the core of bus management, and can achieve the functions of MVB management, on-site process control and the like; a modular structure is adopted, so the structure of the system is simplified, meanwhile functional redundancy and extension can be conducted flexibly and efficiently, and overall performance of a control system is remarkably improved.

Description

MVB bus management function based on ARM realizes system

Technical field

The present invention relates to track traffic control technology field, be specifically related to a kind of MVB bus management function based on ARM and realize system.

Background technology

Development along with embedded Control technology and communication network technology, by (the International Electrotechnical Commission of International Electrotechnical Commission, being abbreviated as IEC) train data communication network (Train Communication Network, is abbreviated as TCN) the standard IEC 61375-1 that formulates has been subject to extensive attention.TCN standard architecture has defined wired train bus (Wire Train Bus, is abbreviated as WTB) and MVB (Multifunction Vehicle Bus, is abbreviated as MVB) two-stage bus.Wherein, MVB bus is for connecting the equipment of vehicle interior, or the equipment between each vehicle in integral train group, is responsible for the data communication of equipment room.

China's train data communications network system also adopts IEC61375-1 standard at present, and has introduced accordingly some products as TCN gateway, MVB board etc.

MVB board can be used MVBC(Multifunction Vehicle Bus Controller, MVB controller) chip also can be used the FPGA(Field-Programmable Gate Array of independent development, i.e. field programmable gate array) realize.But use all functions of the MVB bus defining in FPGA exploitation IEC61375-1 agreement to have the shortcomings such as exploitation is loaded down with trivial details, debugging is complicated, developer has to great effort to be placed on hardware identification code, has increased to a certain extent the complexity of exploitation and has developed the needed time.

Summary of the invention

(1) technical matters that will solve

The object of the present invention is to provide a kind of MVB bus management function based on ARM to realize system, thus can simplied system structure, can carry out functional redundancy and expansion flexibly, efficiently simultaneously, significantly improve the overall performance of control system.

(2) technical scheme

Technical solution of the present invention is as follows:

The MVB bus management function of ARM realizes a system, comprising:

Hardware interface and level of abstraction: for the channel of communicating by letter with FPGA as ARM;

Main control module: show the state of reporting for being responsible for startup, the configuring external interrupt register of MVB board and articulating interrupt handling program and control pilot lamp;

Interruption processing module: interrupt carrying out processing response for the different hardware to from FPGA;

Bus management module: shift and event arbitration function for realize bus master's device scan, sovereignty on the basis of interruption processing module.

Preferably, in described hardware interface and level of abstraction, between ARM and FPGA, by GPIO, interconnect and communicate by letter.

Preferably, application program by GPIO by ARM to FPGA transmitted signal; FPGA by EXTI to ARM transmitted signal.

Preferably, between ARM and FPGA, by GPIO line, realizing GPIO interconnects; Described GPIO line comprises:

Data line: for the data transmission intercoming;

Control signal wire: for assigning instruction for ARM to FPGA;

Sign bit line: for marker frame type, wheel synchronization type and action type;

Interrupt line: for the external interrupt for FPGA notice ARM;

Preferably, described GPIO line also comprises:

Layout line: for configuring FPGA program;

LED line: be used to indicate running status.

Preferably, the interruption of described interruption processing module processing response comprises:

Prime frame is interrupted, from frame interruption, monitored item, is started interruption, sync break, deficiency interruption excess time, overtime interrupt and erroneous frame interruption.

Preferably, also comprise:

At the beginning of initial module, for the initialization of being responsible for all devices to carry out.

Preferably, described initialization comprises storage allocation space, definition data structure, reads configuration signal, initialization apparatus context and a synchronous next state be to FPGA.

Preferably, also comprise:

Worker thread; Described worker thread runs on all modules, realizes the operation conditions of system for supervising described MVB bus management function.

(3) beneficial effect

The MVB bus management function based on ARM that the embodiment of the present invention provides realizes system, the channel that utilizes hardware interface to communicate by letter with FPGA as ARM with level of abstraction, utilize main control module to be responsible for the startup of MVB board, configuring external interrupt register and articulate interrupt handling program and control pilot lamp to show the state of reporting, utilize interruption processing module to from

The different hardware of FPGA interrupts carrying out processing response, and device scan, the sovereignty of utilizing bus management module on the basis of interruption processing module, to realize bus master shift and event arbitration function; This MVB bus management function realizes system as the core of bus management, can complete the functions such as MVB bus management, field process control; And owing to having adopted modular framework, simplified system architecture, can carry out flexibly, efficiently functional redundancy and expansion, thereby significantly improve the overall performance of control system simultaneously.

Accompanying drawing explanation

Fig. 1 is a kind of basic ARM operating system configuration diagram in the embodiment of the present invention;

Fig. 2 is the configuration diagram that in the embodiment of the present invention, the MVB bus management function based on ARM realizes system.

Embodiment

Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described further.Following examples are only for the present invention is described, but are not used for limiting the scope of the invention.

The MVB bus management function based on ARM providing in the present embodiment realize system can be a kind of can be in arm processor embedded real time operation system (Real-Time Operating System, is abbreviated as RTOS), for example system of the upper operation of eCos.

Above-mentioned embedded real time operation system need to support project have driver, memory management, abnormality processing, interruption processing, thread, counter, timer etc., for instant support, requires to have completely preferential, minimal disruption delay, thread synchronization and can make dispatching principle by oneself; For example, concrete:

Above-mentioned embedded real time operation system should comprise with lower module:

Driver (Device Driver): operating system possesses necessary driver, so that the work of control hardware equipment;

Memory management (Memory management): operating system possesses the concerted effort to the distribution of memory source, use, recovery under multitask;

Abnormality processing (Exception handling): the disposal route of accident or abnormal conditions appears in operating system when program operation is provided, refer in particular to hardware anomalies here;

Interrupt processing (Interrupt handling): operating system provides safe handling CPU to interrupt and preserves contextual function;

Thread is supported (Thread support): operating system provides multithreading debug function;

Timer (Timer): operating system provides the function relevant to hardware timer;

Counter (Counter): operating system provides the function relevant to hardware counter;

Meanwhile, this operating system should guarantee following character:

Completely preferential (Full preemptability): the interruption through configuration can be seized the current processor time completely;

Minimal disruption postpones (Minimal interrupt latencies): the shortest interrupt response time, main, the most representative performance index of real time operating system;

Thread synchronization (synchronization primitive): provide inter-thread data synchronous function;

Can make dispatching principle (Schedule policies) by oneself: have interrupt mechanism, thread priority mechanism, provides multiple configurable scheduling strategy and algorithm.

As shown in fig. 1, be the embedded real time operation system architecture of a kind of basic ARM in the present embodiment.From top to bottom, represent the operating system framework from high level to low layer; The bottom is our hardware components, on hardware components, there is hardware abstraction layer (Hardware Abstraction Laye, be abbreviated as HAL) and device driver, some customizable operating systems can be used and carry instrument configure middle kernel, network stack, file system and storehouse, only leave the part needing.The application program of the superiors is partly the part that can write voluntarily, for setting up MVB bus management function, realizes system.

The MVB bus management function based on ARM providing in the present embodiment realizes in system operation and above-mentioned embedded real time operation system, and this MVB bus management function realizes system and mainly comprises hardware interface and level of abstraction, main control module, interruption processing module and bus management module;

Hardware interface and level of abstraction: for important and unique channel of communicating by letter with FPGA as ARM, other ARM application program module operating in embedded real time operation system is not answered direct control register, but a series of grand and predefine of calling hardware interface and level of abstraction and providing completes needed operation;

Main control module: ARM program be take interruption as main, and thread is auxiliary, and this main control module is comprised of three threads, shows for being responsible for startup, the configuring external interrupt register of MVB board and articulating interrupt handling program and control pilot lamp the state of reporting;

Interruption processing module: interrupt carrying out processing response for the different hardware to from FPGA, thereby realize basic MVB function;

Bus management module: process especially for the situation of on the basis of interruption processing module, MVB tetra-kind equipments (four kind equipments have process data, message data, user-programmable ability and bus management ability) being done to bus master, the device scan, the sovereignty that realize bus master shift and event arbitration function.

The configuration diagram of system is provided for the MVB bus management function based on ARM providing in the present embodiment shown in Fig. 2.In hardware interface and abstract aspect, between ARM and FPGA, by GPIO line, realize GPIO(General Purpose Input Output, universal input/output) interconnect communication.For application program, ARM communication line shows as GPIO and EXTI(External Interrupt, and external interrupt is in fact also a kind of special GPIO signal).Application program by general GPIO by ARM to FPGA transmitted signal, and FPGA by EXTI to ARM transmitted signal.Application program is to carry out general GPIO operation by hardware interface, and the EXTI receiving is processed and carried out subsequent operation by interruption.Interrupt processing and can roughly be divided into synchronous processing and frame processing, wherein synchronous processing is mainly used in equipment state, configuration words change, and the frame that frame process to be responsible for is processed on MVB link is replied, the situation of being bus master at equipment is also called main management module and is carried out bus management.The major function of main management module comprises that device scan, sovereignty shift and event arbitration, all need to call hardware interface notice FPGA after corresponding function is disposed.Preferably, can also comprise initialization module and worker thread, initialization module calls the initialization that hardware interface carries out FPGA when device initialize.Worker thread runs on all modules, realizes the operation conditions of system for supervising described MVB bus management function.

Further, the GPIO line being connected between ARM and FPGA can be divided into haply:

Data line: for the data transmission of intercommunication news, the suggested quantity of data line is 16,32,64,128 or 256 etc.;

Control signal wire: for assigning instruction for ARM to FPGA, comprise initialization operation, frame operation, synchronous operation and redundant line;

Sign bit line: for marker frame type, wheel synchronization type, action type etc.;

Interrupt line: for the external interrupt for FPGA notice ARM, comprise that valid frame receives that interruptions, monitored item start in the middle of interruption, sync break, deficiency of time, overtime interrupt and wrong interruption etc.;

Layout line: optional, for configuring FPGA program;

LED line: optional, be used to indicate running status.

Further, in interruption processing module, require the hardware can be to be subject to hardly any speed interrupting to pass to ISR(Interrupt Service Routines, interrupt service routine), ISR can operational hardware and is called some core A PI.In the present embodiment, interruption processing module processing response is interrupted below:

Prime frame is interrupted: on link, receive the prime frame of monitoring data and message data, FPGA sends prime frame to ARM and interrupts, and by ARM, processes this interruptions, and interruption should comprise following functions: frames received certificate, judged whether main conflict, prime frame is processed and replied;

From frame, interrupt: when link receive monitoring data and message data from frame, FPGA sends and interrupts from frame to ARM, by ARM, process this interruption, interruption should comprise following functions: have the equipment frames received certificate of main ability, current chief commander's frame to submit to bus management resume module;

Monitored item starts to interrupt: when the monitored item of current master in one-period starts, FPGA sends this interruption to ARM, notifies the function of current main beginning bus management module;

Sync break: when the state of current device or configuration words change, FPGA reports this interruption to ARM, ARM processes this interruption, should comprise following functions: read new state or configuration words, reconstituted state table, reconfigure main ability, return to new equipment state etc.;

Excess time is not enough interrupts: when last deficiency of time of basic cycle also normally receives a 256bits from frame to send a prime frame, FPGA reports this interruption to ARM, conventionally the event arbitration submodule of this interruption in bus management module processed, because this module is the module of last work in the whole basic cycle;

Overtime interrupt: when the bus silence period reaches designated value, FPGA reports this interruption to ARM.Overtime for prime frame, interrupt handling routine should judge self whether to possess main ability and determine whether to serve as bus master; For from frame timeout, current master should be given bus management resume module, has the equipment of overtime three times of the non-current main reply device scan of main ability to carry out recording processing;

Erroneous frame is interrupted: when FPGA receives erroneous frame on MVB link, report that this interrupts, this interrupts is generally because frame collision is introduced, and this is the foundation that in event arbitration, conflict occurs.

Initialization module is responsible for whole system to carry out necessary initialization, comprises storage allocation space, definition data structure, reads configuration signal, and initialization system context and a synchronous next state are to FPGA.

Further, bus management module comprises following part:

Device scan: in other basic cycle except last basic cycle, bus is main need to remove to scan according to the setting in configuration file the state of several equipment.In order to monitor whole bus, bus is main needs equipment state on poll bus with the up-to-date ruuning situation of equipment, and the current state of equipment is kept in internal memory.When device scan frame that continuous three the dont answer F_CODE of equipment are 15, depending on this equipment, be not present in bus, from equipment state list, disappear.

Sovereignty shift: at the end in each grand cycle, current main can trial be transferred to sovereignty other standby bus master, if without male offspring standby bus master or there is no main the acceptances sovereignty of standby bus retains with sovereign right.

Event arbitration: for there being the equipment of sending out message data demand, arbitrate the transmission message data that its right of priority can not conflicted in bus.

The MVB bus management function based on ARM providing in the present embodiment realizes system can realize system as the core of bus management, can complete the functions such as MVB bus management, field process control; And owing to having adopted modular framework, simplified system architecture, can carry out flexibly, efficiently functional redundancy and expansion, thereby significantly improve the overall performance of control system simultaneously.

Above embodiment is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification, therefore all technical schemes that are equal to also belong to protection category of the present invention.

Claims (9)

1. the MVB bus management function based on ARM realizes a system, it is characterized in that, comprising:

Hardware interface and level of abstraction: for the channel of communicating by letter with FPGA as ARM;

Main control module: show the state of reporting for being responsible for startup, the configuring external interrupt register of MVB board and articulating interrupt handling program and control pilot lamp;

Interruption processing module: interrupt carrying out processing response for the different hardware to from FPGA;

Bus management module: shift and event arbitration function for realize bus master's device scan, sovereignty on the basis of interruption processing module.

2. MVB bus management function according to claim 1 realizes system; It is characterized in that, in described hardware interface and level of abstraction, between ARM and FPGA, by GPIO, interconnect and communicate by letter.

3. MVB bus management function according to claim 2 realizes system; It is characterized in that, application program by GPIO by ARM to FPGA transmitted signal; FPGA by EXTI to ARM transmitted signal.

4. according to the MVB bus management function described in claim 2 or 3, realize system; It is characterized in that, between ARM and FPGA, by GPIO line, realize GPIO and interconnect; Described GPIO line comprises:

Data line: for the data transmission intercoming;

Control signal wire: for assigning instruction for ARM to FPGA;

Sign bit line: for marker frame type, wheel synchronization type and action type;

Interrupt line: for the external interrupt for FPGA notice ARM.

5. MVB bus management function according to claim 4 realizes system; It is characterized in that, described GPIO line also comprises:

Layout line: for configuring FPGA program;

LED line: be used to indicate running status.

6. according to the MVB bus management function described in claim 1-3 or 5 any one, realize system; It is characterized in that, the interruption of described interruption processing module processing response comprises:

Prime frame is interrupted, from frame interruption, monitored item, is started interruption, sync break, deficiency interruption excess time, overtime interrupt and erroneous frame interruption.

7. MVB bus management function according to claim 6 realizes system; It is characterized in that, also comprise:

At the beginning of initial module, for the initialization of being responsible for all devices to carry out.

8. MVB bus management function according to claim 7 realizes system; It is characterized in that, described initialization comprises storage allocation space, definition data structure, reads configuration signal, initialization apparatus context and a synchronous next state be to FPGA.

According to claim 1-3,5 or 7-8 any one described in MVB bus management function realize system; It is characterized in that, also comprise:

Worker thread; Described worker thread runs on all modules, realizes the operation conditions of system for supervising described MVB bus management function.

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