CN115274553A - 晶圆级芯片封装方法及芯片封装结构 - Google Patents

晶圆级芯片封装方法及芯片封装结构 Download PDF

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CN115274553A
CN115274553A CN202210924651.4A CN202210924651A CN115274553A CN 115274553 A CN115274553 A CN 115274553A CN 202210924651 A CN202210924651 A CN 202210924651A CN 115274553 A CN115274553 A CN 115274553A
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wafer
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rewiring
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谢国梁
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China Wafer Level CSP Co Ltd
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Abstract

本发明公开了一种晶圆级芯片封装方法及封装结构，该方法包括：提供一晶圆级基板；在所述晶圆级基板的上表面形成再布线层，所述再布线层包括金属层，所述再布线层内设有无源器件，所述无源器件电性连接所述金属层；提供芯片，所述芯片具有感应区以及与感应区电耦合的焊垫，将所述芯片倒装于所述再布线层上且所述焊垫与所述金属层电性连接；填充塑封材料对所述芯片和再布线层进行塑封；剥离所述晶圆级基板，并在所述再布线层表面形成外接凸起，所述外接凸起与所述金属层电性连接；对形成的晶圆级封装结构进行切割，获得多个独立的芯片封装结构。本发明的晶圆级芯片封装方法，能够提高封装效率，减小封装体积。

Description

晶圆级芯片封装方法及芯片封装结构
技术领域
本发明是关于半导体封装技术领域，特别是关于一种晶圆级芯片封装方法以及芯片封装结构。
背景技术
晶圆级封装(Wafer Level Packaging，缩写WLP)是一种先进的封装技术，因其具有尺寸小、电性能优良、散热好、成本低等优势，近年来发展迅速。根据Verified MarketResearch研究数据，晶圆级封装市场2020年为48.4亿美元，预计到2028年将达到228.3亿美元，从2021年到2028年的复合年增长率为21.4％。
随着电子产品不断升级换代，智能手机、5G、AI等新兴市场对封装技术提出了更高要求，使得封装技术朝着高度集成、三维、超细节距互连等方向发展。晶圆级封装技术可以减小芯片尺寸、布线长度、焊球间距等，因此可以提高集成电路的集成度、处理器的速度等，降低功耗，提高可靠性，顺应了电子产品日益轻薄短小、低成本的发展要需求。
相比于传统封装，晶圆级封装具有以下优点：封装尺寸小、传输速度高、密度连接高、生产周期短、工艺成本低。
现有技术中，对多颗滤波器芯片加入无源器件一并进行封装时，往往封装成型后的封装体，其封装体积较大，且封装效率不高。
公开于该背景技术部分的信息仅仅旨在增加对本发明的总体背景的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域一般技术人员所公知的现有技术。
发明内容
本发明的目的在于提供一种晶圆级芯片封装方法以及芯片封装结构，其能够提高封装效率，减小封装体积。
为实现上述目的，本发明的实施例提供了一种晶圆级芯片封装方法，包括：提供一晶圆级基板；在所述晶圆级基板的上表面形成再布线层，所述再布线层包括金属层，所述再布线层内设有无源器件，所述无源器件电性连接所述金属层；提供芯片，所述芯片具有感应区以及与感应区电耦合的焊垫，将所述芯片倒装于所述再布线层上且所述焊垫与所述金属层电性连接；填充塑封材料对所述芯片和再布线层进行塑封；剥离所述晶圆级基板，并在所述再布线层表面形成外接凸起，所述外接凸起与所述金属层电性连接；对形成的晶圆级封装结构进行切割，获得多个独立的芯片封装结构。
在本发明的一个或多个实施方式中，在晶圆级基板的上表面形成再布线层的步骤之前，还包括：在晶圆级基板的上表面形成黏胶层的步骤，所述再布线层形成于所述黏胶层的表面。
在本发明的一个或多个实施方式中，在剥离所述晶圆级基板的步骤之后，还包括：剥离黏胶层的步骤。
在本发明的一个或多个实施方式中，所述再布线层还包括介质层，所述金属层形成于所述介质层内且部分暴露出所述介质层的上下表面。
在本发明的一个或多个实施方式中，在黏胶层的表面形成再布线层的步骤之前，还包括，在黏胶层的表面形成钝化层的步骤，所述再布线层形成于所述钝化层的表面，所述再布线层内的金属层部分暴露出所述钝化层的表面。
在本发明的一个或多个实施方式中，在填充塑封材料对芯片和再布线层进行塑封的步骤之前，还包括：对所述芯片进行层压，并在所述芯片表面和所述再布线层表面形成层压层的步骤，所述塑封材料填充于所述层压层的表面。
在本发明的一个或多个实施方式中，在将芯片倒装于再布线层上的步骤之前，还包括，在所述芯片的焊垫上形成与焊垫电性连接的金属凸块的步骤，所述芯片的焊垫通过所述金属凸块与所述金属层电性连接。
在本发明的一个或多个实施方式中，所述的在所述芯片的焊垫上形成与焊垫电性连接的金属凸块，包括：提供晶圆级芯片，所述晶圆级芯片具有多颗网格排布的芯片，所述芯片具有感应区以及与感应区电耦合的焊垫；在所述芯片的焊垫上形成金属凸块；切割所述晶圆级芯片得到单个芯片。
本发明一实施例还提供了一种芯片封装结构，包括芯片、再布线层、无源器件、塑封层以及外接凸起。
所述芯片具有相对设置的第一表面和第二表面，所述芯片的第一表面上形成有感应区以及与所述感应区耦合的焊垫；所述再布线层位于所述芯片的第一表面，所述再布线层包括金属层，所述金属层与所述焊垫之间电性连接；所述无源器件位于所述再布线层内且与所述金属层之间电性连接；所述塑封层位于所述芯片的第二表面且包覆所述芯片以及所述再布线层的表面设置；所述外接凸起形成于所述再布线层远离所述芯片的一侧且与所述金属层电性连接。
在本发明的一个或多个实施方式中，所述再布线层还包括介质层，所述金属层形成于所述介质层内且部分暴露出所述介质层的上下表面。
在本发明的一个或多个实施方式中，所述芯片封装结构还包括钝化层和层压层。所述钝化层形成于所述再布线层远离所述芯片的一侧且所述再布线层内的金属层部分暴露出所述钝化层的表面，所述外接凸起完全覆盖暴露出所述钝化层的所述金属层；所述层压层位于所述芯片的第二表面且包覆所述芯片以及所述再布线层的表面设置，所述塑封层形成于所述层压层远离所述芯片的一侧表面上。
与现有技术相比，本发明实施方式的晶圆级芯片封装方法，实现了多颗芯片与无源器件的集成封装，且封装体积小，封装效率高。
附图说明
图1和图2是本发明一实施方式的晶圆级芯片封装方法的流程示意图；
图3-15是本发明一实施方式的晶圆级芯片封装过程的结构示意图。
图6a-图6i是本发明一具体实施方式的芯片封装过程中再布线层的具体形成结构示意图(由图5形成图6的细节步骤)。
图16是本发明一实施方式的芯片封装结构示意图。
具体实施方式
下面结合附图，对本发明的具体实施方式进行详细描述，但应当理解本发明的保护范围并不受具体实施方式的限制。
除非另有其它明确表示，否则在整个说明书和权利要求书中，术语“包括”或其变换如“包含”或“包括有”等等将被理解为包括所陈述的元件或组成部分，而并未排除其它元件或其它组成部分。
正如背景技术所言，现有技术中的滤波器的扇出型封装，其在集成无源器件后，封装体的体积较大，且单颗或几颗滤波器的独立封装，封装效率低。为了解决上述问题，本发明提供了一种晶圆级芯片封装方法，能大大减小封装体的体积，提高封装效率。
下面结合附图，对本发明的具体实施方式进行详细描述。
如图1所示，本发明一实施方式提供了一种晶圆级芯片封装方法，包括：提供一晶圆级基板s1；在晶圆级基板的上表面形成黏胶层s2；在黏胶层的表面形成钝化层s3；在钝化层的表面形成再布线层s4，其中，再布线层包括金属层，再布线层内设有无源器件，无源器件电性连接金属层；提供芯片s5，其中，芯片具有感应区以及与感应区电耦合的焊垫；将芯片倒装于再布线层上且焊垫与金属层电性连接s6；对芯片进行层压并在芯片表面和再布线层表面形成层压层s7；于层压层的表面填充塑封材料s8，以对芯片和再布线层进行塑封；剥离晶圆级基板和黏胶层并在再布线层表面形成外接凸起s9，其中，外接凸起与金属层电性连接；对形成的晶圆级封装结构进行切割s10，以获得多个独立的芯片封装结构。
进一步地，在将芯片倒装于再布线层上的步骤之前，还包括，在芯片的焊垫上形成与焊垫电性连接的金属凸块的步骤，芯片的焊垫通过金属凸块与再布线层的金属层电性连接。具体的，如图2所示，可以先提供晶圆级芯片s51，该晶圆级芯片具有多颗网格排布的芯片，芯片具有感应区以及与感应区电耦合的焊垫；在芯片的焊垫上形成金属凸块s52；切割晶圆级芯片得到单个芯片s53。
图3至图15为本发明一实施方式的晶圆级芯片封装过程的结构示意图。下面结合图3至图15，对本发明的晶圆级芯片的封装方法进行详细阐述。
首先，参考图3所示，提供一晶圆级基板10。晶圆级基板10的材料可以选自玻璃、硅、氧化硅、金属或陶瓷中的一种或多种，且晶圆级基板10为平板型，例如可以但不限于具有一定厚度的玻璃圆形平板。玻璃圆形平板具有相对光滑的平面，其能在后续的工艺中更加方便的被剥离。
参考图4所示，在晶圆级基板10的上表面或下表面形成黏胶层20。黏胶层20在后续工艺中作为钝化层30(再布线层40)与晶圆级基板10之间的分离层，最好选用具有光洁表面的粘合材料支撑。在具体实施例中，黏胶层20可以为UV解胶胶带或热解胶胶带或其他合适的胶带材料，通过喷涂、旋涂或者黏贴等工艺形成，在后续的工艺过程中可以通过UV光照射的方式很方便的将黏胶层20以及晶圆级基板10从钝化层30上揭除。
参考图5所示，在黏胶层20的表面形成钝化层30。钝化层30起到把再布线层40内的金属层41与外部完全隔开的作用，防止金属层41与外部介质接触，从而防止金属层41腐蚀。
参考图6所示，在钝化层30的表面形成再布线层40，其中，再布线层40包括金属层41和介质层42，金属层41形成于介质层42内且部分暴露出介质层42的上下表面，更进一步的，金属层41部分延伸至钝化层30内并自钝化层30的另一侧暴露出钝化层30的表面，便于后续工艺中在钝化层30表面形成与金属层41电性连接的外接凸起70。其中，介质层42可以采用环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅酸玻璃或含氟玻璃。可以采用旋涂、CVD、等离子增强CVD等工艺形成介质层42。再布线层40内还设置有无源器件(图未示)，无源器件完全被再布线层40包裹，且无源器件与金属层41之间电性连接。无源模块可以包括电容、电感和电阻，其具体排布的位置可以根据实际需要进行设计，本发明对此不作限制。
在一具体实施例中，参考图6a至6i所示，形成再布线层40的步骤可以包括：如图6a所示，在钝化层30上形成第一介质层421。如图6b所示，在第一介质层421以及钝化层30上开设第一组通孔422，第一组通孔422深入黏胶层20内但不贯穿黏胶层20。如图6c所示，于第一组通孔422内形成第一金属层411，第一金属层411的上表面与第一介质层421的上表面齐平。如图6d所示，在第一介质层421和第一金属层411上形成第二介质层423。如图6e所示，在第二介质层423上开设第二组通孔424，第二组通孔424暴露出部分或全部第一金属层411。如图6f所示，于第二组通孔424内形成与第一金属层411电性连接的第二金属层412，第二金属层412的上表面与第二介质层423的上表面齐平。如图6g所示，在第二介质层423和第二金属层412上形成第三介质层425。如图6h所示，在第三介质层425上开设第三组通孔426，第三组通孔426暴露出部分或全部第二金属层412。如图6i所示，于第三组通孔426内形成与第二金属层412电性连接的第三金属层413，第三金属层413的上表面凸出于第三介质层425的上表面设置，便于后续工艺的键合封装。
在其他实施方式中，还可以采用其他方式形成再布线层40，例如直接形成介质层42，在介质层42内形成通孔，并于通孔内形成金属层41；或者可以先通过图案化形成金属层41，再填充介质材料形成介质层42等。本发明对此不做限制。
参考图7至图9所示，提供晶圆级芯片100，圆级芯片100包括若干呈行列排列(网格状排布)的芯片110和位于芯片110之间的切割道区域120。其中，图7为晶圆级芯片100的俯视结构示意图，图8为多个芯片110在A-A1方向的剖视图。晶圆级芯片100上的每个芯片110均具有感应区以及环绕感应区设置且与感应区耦合的焊垫。在每个芯片110的焊垫上形成与焊垫电性连接的金属凸块111。沿切割道区域120对晶圆级芯片100进行切割，形成多个芯片110。对晶圆级芯片100进行分割采用现有的切割工艺，在此不再赘述。
参考图10所示，将切割得到的一个或多个芯片110倒装于再布线层40上且芯片110上的金属凸块111与再布线层40上的金属层41电性连接。其中，金属凸块111与金属层41可以采用键合工艺键合，例如可以采用超声键合、热压键合或普通的回流焊等工艺。
参考图11和图12所示，对芯片110进行层压，并在芯片110表面和再布线层40的表面形成层压层50。对层压后的芯片110填充塑封材料进行塑封，后固化塑封材料以形成塑封层60。塑封材料为树脂或防焊油墨材料，例如，环氧树脂或丙烯酸树脂。
形成塑封层60的作用为：一方面，形成的塑封层60起到保护芯片110的作用，防止在外界环境的影响下造成的芯片110性能失效，防止湿气由外部侵入、与外部电气绝缘；另一方面，塑封层60起到支撑芯片110的作用(后续晶圆级基板10会被剥除)，将芯片110固定好以便于后续的电路连接，并且，在封装完成后，使得芯片不易损坏。采用塑封工艺(molding)形成塑封层60，塑封工艺可以采用转移方式或压合方式。
参考图13和图14所示，剥离晶圆级基板10和黏胶层20。可以采用机械研磨、化学抛光、刻蚀、紫外线剥离、机械剥离中的一种或多种剥离黏胶层20及晶圆级基板10；优选地，本实施例中，可以通过撕掉黏胶层20以剥离晶圆级基板10。
若黏胶层20采用的是UV解胶胶带或热解胶胶带，可通过UV光照射的方式使UV解胶胶带或热解胶胶带失去粘性，即可很方便的将黏胶层20以及晶圆级基板10从再布线层40上揭除。
参考图15所示，在再布线层41的表面形成外接凸起70，外接凸起70与金属层41电性连接。外接凸起70用于与外部电路连接。本实施例中，外接凸起70的形状为球形，外接凸起70采用球栅阵列结构(Ball GridArray，BGA)。外接凸起70的形成工艺为植球工艺。外接凸起70的材料可以为金、锡或者锡合金，所述锡合金可以为锡银、锡铅、锡银铜、锡银锌、锡锌、锡铋铟、锡铟、锡金、锡铜、锡锌铟或者锡银锑等。
最后，对形成的晶圆级封装结构进行切割，获得多个独立的芯片封装结构，如图16所示。切割的工艺为切片刀切割或激光切割。由于激光切割具有更小的切口宽度，提高切割工艺的准确性，本实施例中采用激光形成的晶圆级封装结构进行切割。
参考图16所示，本发明还提供了一种芯片封装结构，包括芯片110、钝化层30、再布线层40、无源器件、层压层50、塑封层60以及外接凸起70。
芯片110具有相对设置的第一表面和第二表面，芯片110的第一表面上形成有感应区以及与感应区耦合的焊垫。
再布线层40位于芯片110的第一表面上，再布线40层包括金属层41以及介质层42，金属层41形成于介质层42内且部分暴露出介质层42的上下表面，金属层41与焊垫之间电性连接。无源器件位于再布线层40内且与金属层41之间电性连接。
钝化层30形成于再布线层40远离芯片110的一侧且再布线层40内的金属层41部分暴露出钝化层30的表面。
层压层50位于芯片110的第二表面且包覆芯片110以及再布线层40的表面设置。塑封层60形成于层压层50远离芯片110的一侧表面上。
外接凸起70形成于再布线层40远离芯片110的一侧且与金属层41电性连接，外接凸起70完全覆盖暴露出钝化层30的金属层41。
与现有技术相比，本发明实施方式的晶圆级芯片封装方法，实现了多颗芯片与无源器件的集成封装，且封装体积小，封装效率高。
前述对本发明的具体示例性实施方案的描述是为了说明和例证的目的。这些描述并非想将本发明限定为所公开的精确形式，并且很显然，根据上述教导，可以进行很多改变和变化。对示例性实施例进行选择和描述的目的在于解释本发明的特定原理及其实际应用，从而使得本领域的技术人员能够实现并利用本发明的各种不同的示例性实施方案以及各种不同的选择和改变。本发明的范围意在由权利要求书及其等同形式所限定。

Claims (11)

1.一种晶圆级芯片封装方法，其特征在于，包括：
提供一晶圆级基板；
在所述晶圆级基板的上表面形成再布线层，所述再布线层包括金属层，所述再布线层内设有无源器件，所述无源器件电性连接所述金属层；
提供芯片，所述芯片具有感应区以及与感应区电耦合的焊垫，将所述芯片倒装于所述再布线层上且所述焊垫与所述金属层电性连接；
填充塑封材料对所述芯片和再布线层进行塑封；
剥离所述晶圆级基板，并在所述再布线层表面形成外接凸起，所述外接凸起与所述金属层电性连接；
对形成的晶圆级封装结构进行切割，获得多个独立的芯片封装结构。
2.如权利要求1所述的晶圆级芯片封装方法，其特征在于，在晶圆级基板的上表面形成再布线层的步骤之前，还包括：在晶圆级基板的上表面形成黏胶层的步骤，所述再布线层形成于所述黏胶层的表面。
3.如权利要求2所述的晶圆级芯片封装方法，其特征在于，在剥离所述晶圆级基板的步骤之后，还包括：剥离黏胶层的步骤。
4.如权利要求2所述的晶圆级芯片封装方法，其特征在于，所述再布线层还包括介质层，所述金属层形成于所述介质层内且部分暴露出所述介质层的上下表面。
5.如权利要求4所述的晶圆级芯片封装方法，其特征在于，在黏胶层的表面形成再布线层的步骤之前，还包括，在黏胶层的表面形成钝化层的步骤，所述再布线层形成于所述钝化层的表面，所述再布线层内的金属层部分暴露出所述钝化层的表面。
6.如权利要求1所述的晶圆级芯片封装方法，其特征在于，在填充塑封材料对芯片和再布线层进行塑封的步骤之前，还包括：对所述芯片进行层压，并在所述芯片表面和所述再布线层表面形成层压层的步骤，所述塑封材料填充于所述层压层的表面。
7.如权利要求1所述的晶圆级芯片封装方法，其特征在于，在将芯片倒装于再布线层上的步骤之前，还包括，在所述芯片的焊垫上形成与焊垫电性连接的金属凸块的步骤，所述芯片的焊垫通过所述金属凸块与所述金属层电性连接。
8.如权利要求7所述的晶圆级芯片封装方法，其特征在于，所述的在所述芯片的焊垫上形成与焊垫电性连接的金属凸块，包括：
提供晶圆级芯片，所述晶圆级芯片具有多颗网格排布的芯片，所述芯片具有感应区以及与感应区电耦合的焊垫；
在所述芯片的焊垫上形成金属凸块；
切割所述晶圆级芯片得到单个芯片。
9.一种芯片封装结构，其特征在于，包括：
芯片，具有相对设置的第一表面和第二表面，所述芯片的第一表面上形成有感应区以及与所述感应区耦合的焊垫；
再布线层，位于所述芯片的第一表面，所述再布线层包括金属层，所述金属层与所述焊垫之间电性连接；
无源器件，位于所述再布线层内且与所述金属层之间电性连接；
塑封层，位于所述芯片的第二表面且包覆所述芯片以及所述再布线层的表面设置；
外接凸起，形成于所述再布线层远离所述芯片的一侧且与所述金属层电性连接。
10.如权利要求9所述的芯片封装结构，其特征在于，所述再布线层还包括介质层，所述金属层形成于所述介质层内且部分暴露出所述介质层的上下表面。
11.如权利要求9所述的芯片封装结构，其特征在于，还包括：
钝化层，形成于所述再布线层远离所述芯片的一侧且所述再布线层内的金属层部分暴露出所述钝化层的表面，所述外接凸起完全覆盖暴露出所述钝化层的所述金属层；
层压层，位于所述芯片的第二表面且包覆所述芯片以及所述再布线层的表面设置，所述塑封层形成于所述层压层远离所述芯片的一侧表面上。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116884947A (zh) * 2023-09-05 2023-10-13 长电集成电路(绍兴)有限公司 半导体封装结构及其制备方法
CN116884947B (zh) * 2023-09-05 2024-01-23 长电集成电路(绍兴)有限公司 半导体封装结构及其制备方法

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