CN115226316B - PCB (printed circuit board) electro-gold lead processing method and gold plating method - Google Patents
PCB (printed circuit board) electro-gold lead processing method and gold plating method Download PDFInfo
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- CN115226316B CN115226316B CN202210855006.1A CN202210855006A CN115226316B CN 115226316 B CN115226316 B CN 115226316B CN 202210855006 A CN202210855006 A CN 202210855006A CN 115226316 B CN115226316 B CN 115226316B
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- 238000000034 method Methods 0.000 title claims abstract description 94
- 239000010931 gold Substances 0.000 title claims abstract description 49
- 229910052737 gold Inorganic materials 0.000 title claims abstract description 49
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 238000007747 plating Methods 0.000 title claims abstract description 37
- 238000003672 processing method Methods 0.000 title claims abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052802 copper Inorganic materials 0.000 claims abstract description 28
- 239000010949 copper Substances 0.000 claims abstract description 28
- 238000005516 engineering process Methods 0.000 claims abstract description 22
- 238000005520 cutting process Methods 0.000 claims abstract description 15
- UCHOFYCGAZVYGZ-UHFFFAOYSA-N gold lead Chemical compound [Au].[Pb] UCHOFYCGAZVYGZ-UHFFFAOYSA-N 0.000 claims description 26
- 238000003801 milling Methods 0.000 claims description 18
- LAXBNTIAOJWAOP-UHFFFAOYSA-N 2-chlorobiphenyl Chemical compound ClC1=CC=CC=C1C1=CC=CC=C1 LAXBNTIAOJWAOP-UHFFFAOYSA-N 0.000 description 7
- 101710149812 Pyruvate carboxylase 1 Proteins 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0228—Cutting, sawing, milling or shearing
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The embodiment of the invention provides a PCB (printed circuit board) electro-gold lead processing method and a gold plating method, wherein the PCB electro-gold lead processing method comprises the following steps: processing the bottom copper on the surface of the PCB by adopting a circuit film process to form an electro-gold lead wire for an electro-gold process at a preset position, wherein a preset section of the electro-gold lead wire is formed into a necking section, and the width of the necking section is 50-83% of the standard width of other sections of the electro-gold lead wire; after a gold plating layer is formed by carrying out an electro-gold process on a PCB (printed circuit board) by utilizing an electro-gold lead, cutting a necking section of the electro-gold lead by adopting a routing process or a V-shaped groove processing process, wherein the routing process consists of two routing procedures; the V-shaped groove processing technology is to cut the necking section along a vertical plane line perpendicular to the central axis of the necking section at the midpoint of the length of the necking section to form a V-shaped groove on the surface of the PCB, and two groove side walls of the V-shaped groove, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section. The embodiment can effectively reduce burrs generated during cutting of the electrogas lead.
Description
Technical Field
The embodiment of the invention relates to the technical field of PCB electroplating, in particular to a PCB electro-gold lead processing method and a gold plating method.
Background
At present, the existing PCB needs to be plated with gold on the surface of the circuit board in the manufacturing process; before the surface of the PCB is plated with gold, an electro-gold lead wire is required to be arranged on the PCB, and the electroplating equipment supplies current to each part needing gold plating on the PCB through the electro-gold lead wire, so that a gold plating layer is formed on the PCB.
When the gold plating process is finished, the gold plating lead is usually required to be cut off, the existing gold plating lead cutting method is mainly realized through a routing process or a V-shaped groove processing process, however, after the gold plating lead is cut off, more burrs are formed at the cutting part of the gold plating lead in the traditional routing process or the V-shaped groove processing process, in order to prevent the burrs from causing short circuit of a PCB, burrs are required to be removed by means of tools such as a hairbrush, the gold plating process flow of the PCB is increased, and the manufacturing efficiency of the PCB is reduced.
Disclosure of Invention
The technical problem to be solved by the embodiment of the invention is to provide the PCB electro-gold lead processing method which can effectively reduce burrs generated when the electro-gold lead is cut off.
The technical problem to be further solved by the embodiment of the invention is to provide the PCB gold plating method, which can effectively reduce burrs generated when the electrogilding leads are cut off.
In order to solve the technical problems, the embodiment of the invention provides the following technical scheme: a PCB electrical gold lead processing method comprises the following steps:
Processing the bottom copper on the surface of the PCB by adopting a circuit film process to form an electro-gold lead wire for an electro-gold process at a preset position, wherein a preset section of the electro-gold lead wire is formed into a necking section, and the width of the necking section is 50-83% of the standard width of other sections of the electro-gold lead wire; and
After the gold plating process is carried out on the PCB by utilizing the gold lead to form a gold plating layer, a milling process or a V-shaped groove processing process is adopted to cut off a necking section of the gold lead, the milling process consists of two milling processes, wherein the first milling process is to mill and cut the middle part of the necking section along a first travelling direction to form an initial milling pit, and the second milling process is to mill and cut the pit side wall of the initial milling pit along a second travelling direction opposite to the first travelling direction to form a standard milling pit, and two pit side walls of the standard milling pit, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section; the V-shaped groove processing technology is that the necking section is cut off along a vertical plane line knife perpendicular to the central axis of the necking section at the midpoint of the length of the necking section to form a V-shaped groove on the surface of a PCB, and two groove side walls of the V-shaped groove, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section.
Further, the necked section has a width of 6 mils when the base copper has a thickness of less than 1 ounce; the necked section has a width of 8 mils when the base copper has a thickness of greater than or equal to 1 ounce and less than 1.5 ounces; the necked section has a width of 10 mils when the base copper has a thickness of greater than or equal to 1.5 ounces.
Further, the initial gong pit and the standard gong pit are transversely arranged on two adjacent necking sections in the length direction of the necking section, two pit side walls of the initial gong pit and the standard gong pit are respectively positioned in two adjacent necking sections on the electric gold lead, the length of the two adjacent necking sections outside the initial gong pit is 10mil, and the length of the two adjacent necking sections outside the standard gong pit is 6mil.
Further, the necked-down sections have equal lengths and less than or equal to 20 mils on opposite ends thereof located outside the V-shaped groove.
Further, the V-shaped groove processing technology adopts a cutter with the service life of 10000min and the cutter running speed of 15-20m/min.
On the other hand, in order to solve the above further technical problems, the embodiments of the present invention further provide the following technical solutions: a PCB gold plating method comprises the following steps:
Processing the bottom copper on the surface of the PCB by adopting a circuit film process to form an electro-gold lead wire for an electro-gold process at a preset position, wherein a preset section of the electro-gold lead wire is formed into a necking section, and the width of the necking section is 50-83% of the standard width of other sections of the electro-gold lead wire;
forming a gold plating layer by using the gold-plating lead to perform a gold-plating process on the PCB; and
Cutting off a necking section of the gold lead by adopting a routing process or a V-shaped groove processing process, wherein the routing process consists of two routing processes, a first routing process is to route and cut the middle of the necking section along a first travelling direction to form an initial routing pit, a second routing process is to route and cut pit side walls of the initial routing pit along a second travelling direction opposite to the first travelling direction to form a standard routing pit, and two pit side walls of the standard routing pit, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section; the V-shaped groove processing technology is that the necking section is cut off along a vertical plane line knife perpendicular to the central axis of the necking section at the midpoint of the length of the necking section to form a V-shaped groove on the surface of a PCB, and two groove side walls of the V-shaped groove, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section.
Further, the necked section has a width of 6 mils when the base copper has a thickness of less than 1 ounce; the necked section has a width of 8 mils when the base copper has a thickness of greater than or equal to 1 ounce and less than 1.5 ounces; the necked section has a width of 10 mils when the base copper has a thickness of greater than or equal to 1.5 ounces.
Further, the initial gong pit and the standard gong pit are transversely arranged on two adjacent necking sections in the length direction of the necking section, two pit side walls of the initial gong pit and the standard gong pit are respectively positioned in two adjacent necking sections on the electric gold lead, the length of the two adjacent necking sections outside the initial gong pit is 10mil, and the length of the two adjacent necking sections outside the standard gong pit is 6mil.
Further, the necked-down sections have equal lengths and less than or equal to 20 mils on opposite ends thereof located outside the V-shaped groove.
Further, the V-shaped groove processing technology adopts a cutter with the service life of 10000min and the cutter running speed of 15-20m/min.
After the technical scheme is adopted, the embodiment of the invention has at least the following beneficial effects: according to the embodiment of the invention, the circuit film technology is firstly adopted to process the bottom copper on the surface of the PCB to form the electric gold lead, the necking section is arranged on the electric gold lead, the width of the necking section is 50-83% of the standard width of other sections of the electric gold lead, so that effective conduction current of the necking section can be ensured when the electric gold technology is carried out subsequently, meanwhile, burrs generated when the necking section is cut off are also reduced, after the electric gold lead is utilized to form a gold plating layer, the necking section is cut off by adopting the gong board technology or the V-shaped groove processing technology to realize the disconnection of the electric gold lead, wherein the gong board technology consists of two gong cutting procedures, and the initial gong pit and the standard gong pit are respectively formed backwards.
Drawings
Fig. 1 is a flowchart illustrating steps of an alternative embodiment of a method for processing electrical gold leads of a PCB board according to the present invention.
Fig. 2 is a schematic plan view of an alternative embodiment of the method for processing electrical gold leads of a PCB board according to the present invention, after processing copper bottom on the surface of the PCB board by using a circuit film process.
Fig. 3 is a schematic plan view of a PCB board after a first routing process is performed on a necked-down section by a routing process according to an alternative embodiment of the present invention.
Fig. 4 is a schematic plan view of a PCB board after a second routing process is performed on a necked-down section by a routing process according to an alternative embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a PCB board after a necked-down section is completed by an alternative embodiment of the present invention PCB board electrical gold lead processing method using a routing process.
Fig. 6 is a schematic plan view of a PCB after the necked-down section is completed by V-groove processing in an alternative embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a PCB after the necked-down section is completed using V-groove processing in an alternative embodiment of the PCB electrical gold lead processing method of the present invention.
Detailed Description
The application will be described in further detail with reference to the drawings and the specific examples. It should be understood that the following exemplary embodiments and descriptions are only for the purpose of illustrating the application and are not to be construed as limiting the application, and that the embodiments and features of the embodiments of the application may be combined with one another without conflict.
As shown in fig. 1, an alternative embodiment of the present invention provides a method for processing an electrical gold lead of a PCB board, including the following steps:
s11: processing the bottom copper on the surface of the PCB 1 by adopting a circuit film process to form an electro-gold lead 10 for an electro-gold process at a preset position, wherein a preset section of the electro-gold lead 10 is formed into a necking section 101, and the width of the necking section 101 is 50-83% of the standard width of other sections of the electro-gold lead 10, as shown in figure 2; and
S12: after the gold plating process is performed on the PCB board 1 by using the gold lead 10 to form a gold plating layer, a routing process or a V-groove 16 processing process is adopted to cut off a necked-down section 101 of the gold lead 10, wherein the routing process is composed of two routing processes, a first routing process is to perform routing on the middle part of the necked-down section 101 along a first travelling direction to form an initial routing pit 12, as shown in fig. 3, and a second routing process is to perform routing on pit side walls of the initial routing pit 12 along a second travelling direction opposite to the first travelling direction to form a standard routing pit 14, as shown in fig. 4, two pit side walls of the standard routing pit 14, which are located in the length direction of the necked-down section 101, are both located in the corresponding necked-down section 101, as shown in fig. 5; the V-groove processing process cuts the necked-down section 101 along a vertical plane perpendicular to the central axis of the necked-down section 101 at the midpoint of the length of the necked-down section 101 to form V-grooves 16 on the surface of the PCB board 1, as shown in fig. 6, and two groove side walls of the V-grooves 16 located in the length direction of the necked-down section 101 are located in the corresponding necked-down section 101, as shown in fig. 7.
According to the embodiment of the invention, the circuit film technology is adopted to treat the bottom copper on the surface of the PCB 1 to form the electro-gold lead 10, the necking section 101 is arranged on the electro-gold lead 10, the width of the necking section 101 is 50-83% of the standard width of other sections of the electro-gold lead 10, so that effective conduction current of the necking section 101 can be ensured when the electro-gold technology is carried out subsequently, burrs generated when the necking section 101 is cut off are reduced, after the electro-gold lead 10 is utilized to form a gold plating layer, the necking section 101 is cut off by adopting the gong board technology or the V-shaped groove 16 processing technology to realize the disconnection of the electro-gold lead 10, wherein the gong board technology consists of two gong cutting procedures, namely, an initial gong pit 12 and a standard gong pit 14 are respectively formed backwards, and as the running directions of cutters of the two gong cutting procedures are opposite, so that burrs are removed as much as possible in the gong cutting process, in addition, when the V-shaped groove processing technology is adopted to cut off the necking section 101, the burrs can be effectively reduced when the V-shaped groove 101 is cut off by cutting off the necking section 101 along a line perpendicular to the central axis of the necking section 101.
In an alternative embodiment of the present invention, the necked section 101 has a width of 6 mils when the base copper has a thickness of less than 1 ounce; the necked section 101 has a width of 8 mils when the base copper has a thickness of greater than or equal to 1 ounce and less than 1.5 ounces; the necked section 101 has a width of 10 mils when the base copper has a thickness of greater than or equal to 1.5 ounces. In the embodiment, the width of the necking section 101 is flexibly adjusted according to the thickness of the base copper, so that when the necking section 101 is cut off, reasonable metal cutting amount is designed to reduce burrs; at the same time, it is ensured that the necked down section 101 of the electro-gold process is capable of conducting current effectively. In practice, the standard width of the electrogilding wire 10 is typically 304 microns and about 12 mils when designed.
In an alternative embodiment of the present invention, the initial pit 12 and the standard pit 14 span two adjacent necked-in sections 101 along the length direction of the necked-in sections 101, two pit sidewalls of the initial pit 12 and the standard pit 14 are respectively located in two adjacent necked-in sections 101 on the electrical lead 10, the two adjacent necked-in sections 101 are located outside the initial pit 12 with a length of 10mil, and the two adjacent necked-in sections 101 are located outside the standard pit 14 with a length of 6mil. In this embodiment, in design, there are two adjacent necking segments 101 with a length greater than 6mil and less than or equal to 12mil, and at this time, the electrical gold wire 10 between the two necking segments 101 is also routed to achieve cutting of the electrical gold wire 10, and in implementation, routing can be flexibly performed according to the length of the necking segments 101. In the schematic diagrams as in fig. 3 and 4, circles in the figures indicate the movement paths of the gongs, and arrows in the figures indicate the row direction.
In an alternative embodiment of the invention, the necked-down section 101 is equal in length and less than or equal to 20 mils on both ends located outside the V-groove 16. In this embodiment, when the length of the single necked-down section 101 is greater than 40 mils, the length of the necked-down section 101 outside the V-shaped groove 16 at both ends is equal to 20 mils, which effectively reduces the amount of metal cutting and burrs.
In an alternative embodiment of the present invention, the V-groove 16 is machined with a tool life of 10000min and a tool speed of 15-20m/min. In the embodiment, the V-shaped groove processing technology is performed by adopting the parameters, so that compared with the traditional technology, the service life of the cutter is not required to be specially reduced, and the production cost is reduced.
On the other hand, the embodiment of the invention further provides a PCB gold plating method, which comprises the following steps:
Processing the bottom copper on the surface of the PCB 1 by adopting a circuit film process to form an electro-gold lead 10 for an electro-gold process at a preset position, wherein a preset section of the electro-gold lead 10 is formed into a necking section 101, and the width of the necking section 101 is 50-83% of the standard width of other sections of the electro-gold lead 10;
forming a gold plating layer by performing an electro-gold process on the PCB 1 by using the electro-gold lead 10; and
Cutting off a necking section 101 of the electrical gold lead 10 by adopting a routing process or a V-shaped groove 16 processing process, wherein the routing process consists of two routing processes, a first routing process is to route the middle part of the necking section 101 along a first travelling direction to form an initial routing pit 12, and a second routing process is to route pit side walls of the initial routing pit 12 along a second travelling direction opposite to the first travelling direction to form a standard routing pit 14, wherein two pit side walls of the standard routing pit 14, which are positioned in the length direction of the necking section 101, are positioned in the corresponding necking section 101; the V-shaped groove 16 machining process is to cut the necked-down section 101 along a vertical plane line perpendicular to the central axis of the necked-down section 101 at the midpoint of the length of the necked-down section 101 to form a V-shaped groove 16 on the surface of the PCB board 1, wherein two groove side walls of the V-shaped groove 16 located in the length direction of the necked-down section 101 are located in the corresponding necked-down section 101.
In this embodiment, the method for plating gold on the PCB board uses the same method for processing the electrical gold wire on the PCB board as described above, so that burrs generated when the electrical gold wire is cut off can be effectively reduced. In the specific implementation, the PCB 1 can be subjected to the processes of film drying, pattern electroplating, etching, green oil, electrogilding and the like to form a gold-plated layer on the PCB 1; in addition, the copper base can be formed on the surface of the PCB 1 by a chemical copper deposition process and an electroplating process which are sequentially carried out.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are all within the scope of the present invention.
Claims (10)
1. The PCB electrical gold lead processing method is characterized by comprising the following steps of:
Processing the bottom copper on the surface of the PCB by adopting a circuit film process to form an electro-gold lead wire for an electro-gold process at a preset position, wherein a preset section of the electro-gold lead wire is formed into a necking section, and the width of the necking section is 50-83% of the standard width of other sections of the electro-gold lead wire; and
After the gold plating process is carried out on the PCB by utilizing the gold lead to form a gold plating layer, a milling process or a V-shaped groove processing process is adopted to cut off a necking section of the gold lead, the milling process consists of two milling processes, wherein the first milling process is to mill and cut the middle part of the necking section along a first travelling direction to form an initial milling pit, and the second milling process is to mill and cut the pit side wall of the initial milling pit along a second travelling direction opposite to the first travelling direction to form a standard milling pit, and two pit side walls of the standard milling pit, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section; the V-shaped groove processing technology is that the necking section is cut off along a vertical plane line knife perpendicular to the central axis of the necking section at the midpoint of the length of the necking section to form a V-shaped groove on the surface of a PCB, and two groove side walls of the V-shaped groove, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section.
2. The method of electrical gold lead processing for a PCB of claim 1 wherein the necked-down section has a width of 6 mils when the base copper has a thickness of less than 1 ounce; the necked section has a width of 8 mils when the base copper has a thickness of greater than or equal to 1 ounce and less than 1.5 ounces; the necked section has a width of 10 mils when the base copper has a thickness of greater than or equal to 1.5 ounces.
3. The method for processing the electrical gold lead of the PCB according to claim 1, wherein the initial pit and the standard pit cross two adjacent necking sections in the length direction of the necking section, two pit side walls of the initial pit and the standard pit are respectively positioned in two adjacent necking sections on the electrical gold lead, the length of the two adjacent necking sections positioned outside the initial pit is 10mil, and the length of the two adjacent necking sections positioned outside the standard pit is 6mil.
4. The method of electrical gold lead processing of a PCB of claim 1 wherein the necked-down sections are of equal length and less than or equal to 20 mils on both ends outside the V-shaped groove.
5. The method for processing the electrical gold lead of the PCB according to claim 1, wherein the V-shaped groove processing technology adopts a cutter with the service life of 10000min and the cutter running speed of 15-20m/min.
6. A method for plating gold on a PCB board, the method comprising the steps of:
Processing the bottom copper on the surface of the PCB by adopting a circuit film process to form an electro-gold lead wire for an electro-gold process at a preset position, wherein a preset section of the electro-gold lead wire is formed into a necking section, and the width of the necking section is 50-83% of the standard width of other sections of the electro-gold lead wire;
forming a gold plating layer by using the gold-plating lead to perform a gold-plating process on the PCB; and
Cutting off a necking section of the gold lead by adopting a routing process or a V-shaped groove processing process, wherein the routing process consists of two routing processes, a first routing process is to route and cut the middle of the necking section along a first travelling direction to form an initial routing pit, a second routing process is to route and cut pit side walls of the initial routing pit along a second travelling direction opposite to the first travelling direction to form a standard routing pit, and two pit side walls of the standard routing pit, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section; the V-shaped groove processing technology is that the necking section is cut off along a vertical plane line knife perpendicular to the central axis of the necking section at the midpoint of the length of the necking section to form a V-shaped groove on the surface of a PCB, and two groove side walls of the V-shaped groove, which are positioned in the length direction of the necking section, are positioned in the corresponding necking section.
7. The method of gold plating a PCB of claim 6 wherein the necked-down section has a width of 6 mils when the base copper has a thickness of less than 1 ounce; the necked section has a width of 8 mils when the base copper has a thickness of greater than or equal to 1 ounce and less than 1.5 ounces; the necked section has a width of 10 mils when the base copper has a thickness of greater than or equal to 1.5 ounces.
8. The method of gold plating a PCB board of claim 6, wherein the initial and standard gongs traverse adjacent two necked-down sections in the length direction of the necked-down sections, the two pit sidewalls of the initial and standard gongs are respectively located in adjacent two necked-down sections on the electro-gold wire, the length of the adjacent two necked-down sections located outside the initial gong pit is 10mil, and the length of the adjacent two necked-down sections located outside the standard gong pit is 6mil.
9. The method of gold plating a PCB of claim 6, wherein the necked-down sections are equal in length and less than or equal to 20 mils on both ends outside the V-shaped groove.
10. The method of gold plating on a PCB according to claim 6, wherein the V-shaped groove processing technology adopts a cutter with a service life of 10000min and a cutter running speed of 15-20m/min.
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Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105154774A (en) * | 2015-09-23 | 2015-12-16 | 宝山钢铁股份有限公司 | Free-cutting medium-carbon non-quenching and tempering steel for fracture splitting connecting rod and manufacturing method thereof |
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JP3495699B2 (en) * | 2000-12-11 | 2004-02-09 | 株式会社双晶テック | Manufacturing method of wiring board having lead with bump |
US20050156961A1 (en) * | 2004-01-21 | 2005-07-21 | Kia Silverbrook | Method of printing on-demand patterned media |
CN211297151U (en) * | 2019-12-26 | 2020-08-18 | 广州市太和电路板有限公司 | Lead structure of printed circuit board golden finger |
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CN105154774A (en) * | 2015-09-23 | 2015-12-16 | 宝山钢铁股份有限公司 | Free-cutting medium-carbon non-quenching and tempering steel for fracture splitting connecting rod and manufacturing method thereof |
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---|
厚膜HIC镀金引线柱直接采用锡基焊料研究;刘俊夫;郑静;;电子元件与材料;20160701(第07期);全文 * |
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