CN115225078B - Level detection circuit and level conversion circuit - Google Patents
Level detection circuit and level conversion circuit Download PDFInfo
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- CN115225078B CN115225078B CN202211134702.XA CN202211134702A CN115225078B CN 115225078 B CN115225078 B CN 115225078B CN 202211134702 A CN202211134702 A CN 202211134702A CN 115225078 B CN115225078 B CN 115225078B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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Abstract
The invention relates to the technical field of level conversion, and discloses a level detection circuit and a level conversion circuit, wherein the level detection circuit comprises a signal processing unit, a first pulse signal generating unit, a second pulse signal generating unit, a first load branch, a second load branch, a first main switch branch, a first side switch branch, a second main switch branch, a second side switch branch and a current source; when the level is changed, the pulse signal generating unit generates a pulse signal, the pulse signal is used for controlling the conducting time of the first bypass switch branch and the second bypass switch branch, on one hand, the electric potential forming speed of the first load branch and the second load branch can be increased in the initial stage of level switching by controlling the duration time of the pulse signal, the response speed is improved, on the other hand, after the electric potentials of the first load branch and the second load branch are formed, the pulse signal is not input to the control end of the first bypass switch branch or the control end of the second bypass switch branch, and the power consumption of the circuit can be reduced.
Description
Technical Field
The invention relates to the technical field of level conversion, in particular to a level detection circuit and a level conversion circuit.
Background
In the field of analog circuits, a level conversion circuit is often required to perform level conversion of signals, for example, when a single chip outputs a driving signal to drive a peripheral circuit to work, the level conversion of the signals output by the single chip is required due to poor driving capability of a switching signal or a PWM signal output by the single chip.
For a level shift circuit, its shift speed and operating power consumption are important parameters of the circuit. However, for the existing level shift circuit, the shift speed and the operating power consumption are opposite, if the shift speed is increased, the circuit operating current needs to be increased, and the increase of the operating current increases the operating power consumption. Therefore, the conventional level shift circuit will increase the working power consumption when the shift speed is increased, and the shift speed will be slowed down when the working power consumption is reduced.
Disclosure of Invention
In view of the deficiencies of the background art, the present invention provides a level detection circuit and a level shift circuit to increase the level shift speed and reduce power consumption.
To solve the above technical problems, a first aspect of the present invention provides a level detection circuit, comprising
A signal processing unit including an input terminal and an output terminal, configured to invert an input signal;
a first pulse signal generating unit and a second pulse signal generating unit; the first pulse signal generating unit is electrically connected with the output end and generates at least one pulse signal when the signal level of the output end is changed; the second pulse signal generating unit is electrically connected with the input end and generates at least one pulse signal when the signal level of the input end is changed;
the load circuit comprises a first load branch, a second load branch, a first main switch branch, a first bypass switch branch, a second main switch branch, a second bypass switch branch and a current source;
the input end of the first main switch branch and the input end of the first bypass switch branch are respectively and electrically connected with the output end of the first load branch; the control end of the first main switch branch circuit is electrically connected with the input end of the signal processing unit, and is conducted to generate a first current when the signal level of the input end of the signal processing unit is in a first state; the control end of the first bypass switch branch circuit is electrically connected with the pulse signal output end of the second pulse signal generation unit, and is conducted when the level of the input pulse signal is in a first state to generate a second current, wherein the second current is greater than the first current;
the input end of the second main switch branch and the input end of the second side switch branch are respectively and electrically connected with the output end of the second load branch; the control end of the second main switch branch circuit is electrically connected with the output end of the signal processing unit, and is conducted when the signal level of the output end of the signal processing unit is in a first state to generate a third current; the control end of the second side switch branch circuit is electrically connected with the pulse signal output end of the first pulse signal generation unit, and is conducted when the level of the input pulse signal is in a first state to generate fourth current; the fourth current is greater than the third current;
the output end of the first main switch branch and the output end of the second main switch branch are electrically connected with the current source, and the output end of the first bypass switch branch and the output end of the second bypass switch branch are both grounded.
In a certain embodiment of the first aspect, the signal processing unit is an inverter.
In a certain embodiment of the first aspect, the first state is a high state.
In one embodiment of the first aspect, the first pulse signal generating unit generates at least one pulse signal when the signal level of the output terminal changes from a low level to a high level; the second pulse signal generating unit generates at least one pulse signal when the signal level of the input terminal changes from a low level to a high level.
In a certain embodiment of the first aspect, the first load branch comprises a first MOS transistor P1 and a second MOS transistor HN1, and the second load branch comprises a third MOS transistor P2 and a fourth MOS transistor HN2; the source electrode of the first MOS tube P1 is electrically connected with the source electrode of the third MOS tube P2; the grid electrode of the first MOS tube P1 is respectively and electrically connected with the drain electrode of the first MOS tube P1 and the drain electrode of the second MOS tube HN 1; the grid electrode of the third MOS tube P2 is respectively and electrically connected with the drain electrode of the third MOS tube P2 and the drain electrode of the fourth MOS tube HN2; the source electrode of the second MOS tube HN1 is the output end of the first load branch; and the source electrode of the fourth MOS tube HN2 is the output end of the second load branch.
In a certain implementation manner of the first aspect, the first main switching branch includes a fifth MOS transistor N3, the first bypass switching branch includes a sixth MOS transistor N1, the second main switching branch includes a seventh MOS transistor N4, and the second bypass switching branch includes an eighth MOS transistor N2;
the drain electrode of the fifth MOS tube N3 and the drain electrode of the sixth MOS tube N1 are respectively and electrically connected with the output end of the first load branch; the grid electrode of the fifth MOS tube N3 is electrically connected with the input end of the signal processing unit; the grid electrode of the sixth MOS tube N1 is electrically connected with the pulse signal output end of the second pulse signal generation unit;
the drain electrode of the seventh MOS transistor N4 and the drain electrode of the eighth MOS transistor N2 are respectively and electrically connected with the output end of the second load branch circuit; the grid electrode of the seventh MOS tube N4 is electrically connected with the output end of the signal processing unit; the grid electrode of the eighth MOS tube N2 is electrically connected with the pulse signal output end of the first pulse signal generation unit;
the source electrode of the fifth MOS transistor N3 and the source electrode of the seventh MOS transistor N4 are respectively and electrically connected with the current source; and the source electrode of the sixth MOS tube N1 and the source electrode of the eighth MOS tube N2 are grounded.
The operation principle of the level detection circuit of the present invention will be explained:
an external signal is input to an input end of the signal processing unit, and a conversion voltage VHB is input to an input end of the first load branch and an input end of the second load branch;
when an external signal is changed from a low level to a high level, the first main switch branch is switched on, the first bypass switch branch is switched on when an input pulse signal is at the high level, the second main switch branch and the second bypass switch branch are switched off, and the voltage of the output end of the first load branch is smaller than the voltage of the output end of the second load branch; when the control end of the first bypass switch branch circuit does not input a pulse signal, the first bypass switch branch circuit is turned off, but the first main switch branch circuit is still turned on at the moment, and the voltage of the output end of the first load branch circuit can still be smaller than the voltage of the output end of the second load branch circuit;
when an external signal is changed from a high level to a low level, an input signal of the first pulse signal generating unit is changed from the low level to the high level through the phase reversal of the signal processing unit, the second main switch branch is conducted at the moment, the second side switch branch is conducted when the input pulse signal is at the high level, the first main switch branch and the first side switch branch are turned off, and the voltage of the output end of the first load branch is greater than the voltage of the output end of the second load branch at the moment; when the control end of the second side switch branch circuit does not input a pulse signal, the second side switch branch circuit is switched off, but the second main switch branch circuit is still switched on at the moment, and the voltage of the output end of the first load branch circuit can still be greater than the voltage of the output end of the second load branch circuit; therefore, the level state of the external signal can be obtained by detecting and comparing the voltage of the electrical node of the first load branch circuit and the voltage of the electrical node of the second load branch circuit;
in addition, because the first MOS transistor P1, the third MOS transistor P2, the second MOS transistor HN1, and the fourth MOS transistor HN2 all have parasitic capacitances, in order to increase the switching speed of the MOS transistors, the present invention allows the first main switching branch to generate a first current and allows the first bypass switching branch to generate a second current when the pulse signal generating unit outputs a pulse signal within a period of time after the level of the external signal changes, thereby increasing the charge and discharge currents of the gates of the first MOS transistor P1 and the third MOS transistor P2, increasing the switching speed and the response speed of the present invention, and after the first MOS transistor P1 and the third MOS transistor P2 are turned on, in order to reduce power consumption, the on-time of the first bypass switching branch may be controlled by controlling the number of pulse signals generated by the pulse signal generating unit and the high-level duration of the pulse signals, so as to reduce power consumption.
In a second aspect, the present invention further provides a level shift circuit, which employs the above level detection circuit, and includes a voltage comparison unit, a current mirror unit, and a second signal processing unit; the voltage comparison unit comprises a voltage input end, a first input end, a second input end, a first output end and a second output end, the first input end is electrically connected with the first load branch, the second input end is electrically connected with the second load branch, the first output end is electrically connected with the main current mirror of the current mirror unit, the second output end is respectively electrically connected with the slave current mirror of the current mirror unit and the input end of the second signal processing unit, and the second signal processing unit is used for inverting the input signal; when the voltage of the first input end is greater than that of the second input end, the voltage comparison unit enables the voltage input end to be communicated with the input end of the second signal processing unit; when the voltage of the first input end is smaller than that of the second input end, the first output end inputs working current to the main current mirror.
In one embodiment of the second aspect, the voltage comparison unit includes a ninth MOS transistor P3 and a tenth MOS transistor P4, a source of the ninth MOS transistor P3 is electrically connected to a source of the tenth MOS transistor P4, a drain of the ninth MOS transistor P3 is a first output terminal of the voltage comparison unit, and a drain of the tenth MOS transistor P4 is a second output terminal of the voltage comparison unit; the gate of the ninth MOS transistor P3 is a first input terminal of the voltage comparison unit, the gate of the tenth MOS transistor P4 is a second input terminal of the voltage comparison unit, and the source of the ninth MOS transistor P3 is a voltage input terminal of the voltage comparison unit.
In one embodiment of the second aspect, the second signal processing unit includes an inverter.
When the voltage conversion circuit is actually used, the voltage input end is connected with the conversion voltage VHB, the output end of the current mirror unit is connected with the conversion voltage VHS, the conversion voltage VHB is in a high level state, and the conversion voltage VHS is in a low level state;
when the voltage of the first input end is smaller than the voltage of the second input end, namely the signal input by the input end of the signal processing unit is at a high level, the current mirror unit works due to the input of working current, at the moment, the conversion voltage VHS is input into the second signal processing unit for inversion, and the second signal processing unit outputs a high-level signal;
when the voltage of the first input end is greater than the voltage of the second input end, namely the signal input by the input end of the signal processing unit is at a low level, the voltage input end is communicated with the input end of the second signal processing unit, at the moment, the conversion voltage VHB is input to the second signal processing unit for inversion, and the second signal processing unit outputs a low-level signal, so that the level conversion is realized. When the level conversion is carried out by the level conversion circuit, the conversion speed of the level detection circuit is improved, and the working power consumption is reduced, so that the speed of the whole level conversion process is also improved, and the working power consumption is also reduced.
Compared with the prior art, the invention has the following beneficial effects: when the level is converted, namely the level is changed from low level to high level, the invention generates the pulse signal which is used for controlling the duration time of the second current and the fourth current, on one hand, the potential forming speed of the first load branch and the second load branch can be accelerated in the initial stage of level switching by controlling the duration time of the pulse signal, the response speed is improved, on the other hand, after the potentials of the first load branch and the second load branch are formed, the pulse signal is not input to the control end of the first bypass switch branch or the second bypass switch branch, and the whole use power consumption of the circuit can be reduced.
Drawings
FIG. 1 is a schematic diagram of a level detection circuit according to an embodiment;
fig. 2 is a circuit diagram of a first load branch, a second load branch, a first main switch branch, a first bypass switch branch, a second main switch branch, a second bypass switch branch and a current source in an embodiment;
FIG. 3 is a waveform diagram of an external input signal and a signal generated by the second pulse signal generating unit;
FIG. 4 is a circuit diagram of a level conversion circuit in an embodiment;
fig. 5 is a waveform diagram of the level shift circuit in use.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
As shown in FIG. 1, the level detection circuit comprises
A signal processing unit 1 including an input terminal and an output terminal, configured to invert an input signal;
a first pulse signal generating unit 2 and a second pulse signal generating unit 3; the first pulse signal generating unit 2 is electrically connected with the output end and generates at least one pulse signal when the signal level of the output end is changed; the second pulse signal generating unit 3 is electrically connected with the input end and generates at least one pulse signal when the signal level of the input end changes;
a first load branch 4, a second load branch 5, a first main switch branch 6, a first bypass switch branch 7, a second main switch branch 8, a second bypass switch branch 9 and a current source 10;
the input end of the first main switch branch 6 and the input end of the first bypass switch branch 7 are respectively electrically connected with the output end of the first load branch 4; the control end of the first main switch branch 6 is electrically connected with the input end of the signal processing unit 1, and is conducted when the signal level of the input end of the signal processing unit 1 is in a first state to generate a first current; the control end of the first bypass switch branch 7 is electrically connected with the pulse signal output end of the second pulse signal generating unit 3, and is conducted to generate a second current when the level of the input pulse signal is in a first state, wherein the second current is greater than the first current; wherein the first current is in uA level, and the second current is in mA level;
the input end of the second main switch branch 8 and the input end of the second side switch branch 9 are respectively electrically connected with the output end of the second load branch 5; the control end of the second main switch branch 8 is electrically connected with the output end of the signal processing unit 1, and is conducted when the signal level of the output end of the signal processing unit 1 is in a first state to generate a third current; the control end of the second side switch branch 9 is electrically connected with the pulse signal output end of the first pulse signal generating unit 2, and is conducted when the level of the input pulse signal is in a first state to generate a fourth current; the fourth current is greater than the third current; wherein the third current is in a uA level, and the fourth current is in a mA level;
the output end of the first main switch branch 6 and the output end of the second main switch branch 8 are electrically connected with a current source 10, and the output end of the first bypass switch branch 7 and the output end of the second bypass switch branch 9 are both grounded.
In this embodiment, the first pulse signal generating unit 2 generates a pulse signal when the signal level at the output terminal changes from a low level to a high level; the second pulse signal generating unit 3 generates a pulse signal when the signal level of the input terminal changes from a low level to a high level. Taking the second pulse signal generating unit 3 as an example, the waveform of the external input signal IN and the waveform of the pulse signal generated by the second pulse signal generating unit 3 are as shown IN fig. 3. When the pulse signal is in a high state, the first bypass switch branch 7 or the second bypass switch branch 9 is turned on. In practical use, the high level duration of the pulse signal may be between 1ns and 100 ns.
In one embodiment, the first pulse signal generating unit 2 generates one pulse signal when the signal level at the output terminal changes from a high level to a low level; the second pulse signal generating unit 3 generates a pulse signal when the signal level of the input terminal changes from a high level to a low level.
In the present embodiment, the signal processing unit 1 includes an inverter INV1. The first state is a high state.
As shown in fig. 2, in an implementation circuit of the level detection circuit, the first load branch 4 includes a first MOS transistor P1 and a second MOS transistor HN1, and the second load branch 5 includes a third MOS transistor P2 and a fourth MOS transistor HN2; the source electrode of the first MOS tube P1 is electrically connected with the source electrode of the third MOS tube P2; the grid electrode of the first MOS tube P1 is respectively and electrically connected with the drain electrode of the first MOS tube P1 and the drain electrode of the second MOS tube HN 1; the grid electrode of the third MOS tube P2 is respectively and electrically connected with the drain electrode of the third MOS tube P2 and the drain electrode of the fourth MOS tube HN2; the source of the second MOS transistor HN1 is the output end of the first load branch 4; the source of the fourth MOS transistor HN2 is the output end of the second load branch 5.
The first main switch branch 6 comprises a fifth MOS transistor N3, the first bypass switch branch 7 comprises a sixth MOS transistor N1, the second main switch branch 8 comprises a seventh MOS transistor N4, and the second bypass switch branch 9 comprises an eighth MOS transistor N2;
the drain electrode of the fifth MOS transistor N3 and the drain electrode of the sixth MOS transistor N1 are respectively and electrically connected with the output end of the first load branch 4; the grid electrode of the fifth MOS tube N3 is electrically connected with the input end of the signal processing unit 1; the grid electrode of the sixth MOS tube N1 is electrically connected with the pulse signal output end of the second pulse signal generating unit 3;
the drain electrode of the seventh MOS tube N4 and the drain electrode of the eighth MOS tube N2 are respectively and electrically connected with the output end of the second load branch 5; the grid electrode of the seventh MOS tube N4 is electrically connected with the output end of the signal processing unit 1; the grid electrode of the eighth MOS tube N2 is electrically connected with the pulse signal output end of the first pulse signal generating unit 2;
the source electrode of the fifth MOS transistor N3 and the source electrode of the seventh MOS transistor N4 are respectively electrically connected with a current source 10; the source electrode of the sixth MOS transistor N1 and the source electrode of the eighth MOS transistor N2 are grounded.
IN actual use, an external input signal IN is input to the input end of the signal processing unit 1, and the input end of the first load branch 4 and the input end of the second load branch 5 input the conversion voltage VHB; a grid electrode of the second MOS tube HN1 is input with a power supply VDD, and a grid electrode of the fourth MOS tube HN2 is input with the power supply VDD;
when the external input signal IN changes from low level to high level, the first main switch branch 6 is turned on, the first bypass switch branch 7 is turned on when the input pulse signal is high level, the second main switch branch 8 and the second bypass switch branch 9 are turned off, and at this time, the voltage of the output end of the first load branch 4 is smaller than the voltage of the output end of the second load branch 5; when no pulse signal is input to the control end of the first bypass switching branch 7, the first bypass switching branch 7 is turned off, but the first main switching branch 6 is still turned on at the moment, and the voltage of the output end of the first load branch 4 can still be smaller than the voltage of the output end of the second load branch 5;
when the external input signal IN changes from high level to low level, the input signal of the first pulse signal generating unit 2 changes from low level to high level through the phase reversal of the signal processing unit 1, at this time, the second main switch branch 8 is turned on, the second side switch branch 9 is turned on when the input pulse signal is high level, the first main switch branch 6 and the first side switch branch 7 are turned off, and at this time, the voltage of the output end of the first load branch 4 is greater than the voltage of the output end of the second load branch 5; when no pulse signal is input to the control end of the second side switch branch 9, the second side switch branch 9 is turned off, but the second main switch branch 8 is still turned on at the moment, and the voltage of the output end of the first load branch 4 can still be greater than the voltage of the output end of the second load branch 5; therefore, the level state of the external input signal IN can be obtained by detecting and comparing the voltage of the electrical node of the first load branch 4 and the voltage of the electrical node of the second load branch 5;
IN addition, because the first MOS transistor P1, the third MOS transistor P2, the second MOS transistor HN1, and the fourth MOS transistor HN2 all have parasitic capacitances, IN order to increase the switching speed of the MOS transistors, the present invention allows the first main switching branch 6 to generate a first current and allows the first bypass switching branch 7 to generate a second current when the pulse signal generating unit outputs a pulse signal after a period of time after the level of the external input signal IN changes, thereby increasing the charge and discharge currents of the gates of the first MOS transistor P1 and the third MOS transistor P2, increasing the switching speed and the response speed of the present invention, and after the first MOS transistor P1 and the third MOS transistor P2 are turned on, IN order to reduce power consumption, the on-time of the first bypass switching branch 7 may be controlled by controlling the number of pulse signals generated by the pulse signal generating unit and the high level duration of the pulse signals, so as to reduce power consumption.
As shown in fig. 4, the present invention further provides a level shift circuit, which further includes a voltage comparing unit 11, a current mirror unit 12 and a second signal processing unit 13 on the basis of the circuit of fig. 2; the voltage comparison unit 11 comprises a voltage input end, a first input end, a second input end, a first output end and a second output end, the first input end is electrically connected with the first load branch 4, the second input end is electrically connected with the second load branch 5, the first output end is electrically connected with the main current mirror of the current mirror unit 12, the second output end is respectively electrically connected with the auxiliary current mirror of the current mirror unit 12 and the input end of the second signal processing unit 13, and the second signal processing unit 13 performs phase inversion on input signals; when the voltage of the first input end is greater than that of the second input end, the voltage comparison unit 11 has a voltage input end communicated with the input end of the second signal processing unit 13; when the voltage of the first input terminal is lower than that of the second input terminal, the voltage comparison unit 11 inputs the working current to the main current mirror through the first output terminal.
Specifically, the voltage comparison unit 11 includes a ninth MOS transistor P3 and a tenth MOS transistor P4, a source of the ninth MOS transistor P3 is electrically connected to a source of the tenth MOS transistor P4, a drain of the ninth MOS transistor P3 is a first output terminal of the voltage comparison unit 11, and a drain of the tenth MOS transistor P4 is a second output terminal of the voltage comparison unit 11; the gate of the ninth MOS transistor P3 is a first input terminal of the voltage comparing unit 11 and is electrically connected to the drain of the first MOS transistor P1, the gate of the tenth MOS transistor P4 is a second input terminal of the voltage comparing unit 11 and is electrically connected to the drain of the third MOS transistor P2, and the source of the ninth MOS transistor P3 is a voltage input terminal of the voltage comparing unit and is configured to input the conversion voltage VHB.
Specifically, the second signal processing unit 13 includes an inverter INV2.
Specifically, the current mirror unit 12 includes a MOS transistor N5 and a MOS transistor N6, where the MOS transistor N5 is a master current mirror of the current mirror unit 12, and the MOS transistor N6 is a slave current mirror of the current mirror unit 12.
In actual use, the voltage input end is connected with the conversion voltage VHB, the output end of the current mirror unit 12 is connected with the conversion voltage VHS, the conversion voltage VHB is in a high level state, and the conversion voltage VHS is in a low level state;
when the voltage of the first input terminal is lower than the voltage of the second input terminal, that is, when the signal input from the input terminal of the signal processing unit 1 is at a high level, the current mirror unit 12 operates by inputting the operating current, and at this time, the converted voltage VHS is input to the second signal processing unit 13 to be inverted, and the second signal processing unit 13 outputs a high-level signal corresponding to the high level of the external input signal IN.
When the voltage of the first input terminal is greater than the voltage of the second input terminal, that is, when the signal input at the input terminal of the signal processing unit 1 is at a low level, the voltage input terminal is communicated with the input terminal of the second signal processing unit 13, at this time, the switching voltage VHB is input to the second signal processing unit 13 for inversion, and the second signal processing unit 13 outputs a signal at a low level corresponding to the low level of the external input signal IN, thereby realizing level switching. When the level conversion circuit of the invention is used for level conversion, the conversion speed of the level detection circuit is improved, and the working power consumption is reduced, so that the speed of the whole level conversion process is also improved, and the working power consumption is also reduced.
For easy understanding, IN the present embodiment, waveforms of an external input signal IN, an output signal INB of the signal processing unit 1, an output signal INB _ P of the first pulse signal generating unit 2, an output signal IN _ P of the second pulse signal generating unit 3, a drain voltage INH of the first MOS transistor P1, a drain voltage INBH of the third MOS transistor P2, and an output terminal voltage INE of the inverter INV2 are as shown IN fig. 5.
Exemplarily, the current value of the pulse signal output by the first pulse signal generating unit 2 is designed to be 1mA, the duration is 5ns, the current of the current source 10 is 5uA, and the time required by the level shift circuit of the present invention to convert the external input signal IN into the output signal of the second signal processing unit 13 is less than 1ns; when the frequency of the external input signal IN is 1MHz, the average power consumption of the level conversion circuit is about 15uA. The conversion time of the conventional level conversion circuit is generally more than 10ns, and the overall average power consumption is more than hundreds of uA (ultra wide band) and even more than 1 mA.
In summary, in the present invention, when the level is switched, the pulse signal is generated when the level is switched, that is, when the level is changed from low level to high level, and the pulse signal is used for controlling the duration of the second current and the fourth current, by controlling the duration of the pulse signal, on one hand, the forming speed of the potentials of the first load branch 4 and the second load branch 5 can be increased in the initial stage of the level switching, and the response speed can be increased, and on the other hand, after the potentials of the first load branch 4 and the second load branch 5 are formed, the pulse signal is no longer input to the control terminal of the first bypass switch branch or the second bypass switch branch, that is, the second current or the fourth current is removed, so that the overall power consumption of the circuit can be reduced.
In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (9)
1. The level detection circuit is characterized by comprising
A signal processing unit including an input terminal and an output terminal, configured to invert an input signal;
a first pulse signal generating unit and a second pulse signal generating unit; the first pulse signal generating unit is electrically connected with the output end and generates at least one pulse signal when the signal level of the output end is changed; the second pulse signal generating unit is electrically connected with the input end and generates at least one pulse signal when the signal level of the input end is changed;
the load circuit comprises a first load branch, a second load branch, a first main switch branch, a first bypass switch branch, a second main switch branch, a second bypass switch branch and a current source;
the input end of the first main switch branch and the input end of the first bypass switch branch are respectively and electrically connected with the output end of the first load branch; the control end of the first main switch branch circuit is electrically connected with the input end of the signal processing unit, and is conducted when the signal level of the input end of the signal processing unit is in a first state to generate a first current; the control end of the first bypass switch branch circuit is electrically connected with the pulse signal output end of the second pulse signal generating unit, and is conducted when the level of the input pulse signal is in a first state to generate a second current; the second current is greater than the first current;
the input end of the second main switch branch and the input end of the second side switch branch are respectively and electrically connected with the output end of the second load branch; the control end of the second main switch branch circuit is electrically connected with the output end of the signal processing unit, and is conducted when the signal level of the output end of the signal processing unit is in a first state to generate a third current; the control end of the second side switch branch circuit is electrically connected with the pulse signal output end of the first pulse signal generation unit, and is conducted when the level of the input pulse signal is in a first state to generate fourth current; the fourth current is greater than the third current;
the output end of the first main switch branch and the output end of the second main switch branch are respectively electrically connected with the current source, and the output end of the first bypass switch branch and the output end of the second bypass switch branch are both grounded.
2. The level detection circuit of claim 1, wherein the signal processing unit is an inverter.
3. The level detection circuit of claim 1, wherein the first state is a high state.
4. The level detecting circuit according to claim 1, wherein said first pulse signal generating unit generates at least one pulse signal when the signal level of said output terminal changes from a low level to a high level; the second pulse signal generating unit generates at least one pulse signal when the signal level of the input terminal changes from a low level to a high level.
5. The level detection circuit according to claim 1, wherein the first load branch comprises a first MOS transistor (P1) and a second MOS transistor (HN 1), and the second load branch comprises a third MOS transistor (P2) and a fourth MOS transistor (HN 2); the source electrode of the first MOS tube (P1) is electrically connected with the source electrode of the third MOS tube (P2); the grid electrode of the first MOS tube (P1) is respectively and electrically connected with the drain electrode of the first MOS tube (P1) and the drain electrode of the second MOS tube (HN 1); the grid electrode of the third MOS tube (P2) is respectively and electrically connected with the drain electrode of the third MOS tube (P2) and the drain electrode of the fourth MOS tube (HN 2); the source electrode of the second MOS tube (HN 1) is the output end of the first load branch; and the source electrode of the fourth MOS tube (HN 2) is the output end of the second load branch.
6. The circuit according to any of claims 1-5, wherein the first main switching branch comprises a fifth MOS transistor (N3), the first bypass switching branch comprises a sixth MOS transistor (N1), the second main switching branch comprises a seventh MOS transistor (N4), and the second bypass switching branch comprises an eighth MOS transistor (N2);
the drain electrode of the fifth MOS tube (N3) and the drain electrode of the sixth MOS tube (N1) are respectively and electrically connected with the output end of the first load branch; the grid electrode of the fifth MOS tube (N3) is electrically connected with the input end of the signal processing unit; the grid electrode of the sixth MOS tube (N1) is electrically connected with the pulse signal output end of the second pulse signal generation unit;
the drain electrode of the seventh MOS tube (N4) and the drain electrode of the eighth MOS tube (N2) are respectively and electrically connected with the output end of the second load branch; the grid electrode of the seventh MOS tube (N4) is electrically connected with the output end of the signal processing unit; the grid electrode of the eighth MOS tube (N2) is electrically connected with the pulse signal output end of the first pulse signal generation unit;
the source electrode of the fifth MOS tube (N3) and the source electrode of the seventh MOS tube (N4) are respectively and electrically connected with the current source; the source electrode of the sixth MOS tube (N1) and the source electrode of the eighth MOS tube (N2) are grounded.
7. Level shift circuit, comprising a level detection circuit according to any of claims 1 to 6, comprising a voltage comparison unit, a current mirror unit and a second signal processing unit; the voltage comparison unit comprises a voltage input end, a first input end, a second input end, a first output end and a second output end, the first input end is electrically connected with the first load branch, the second input end is electrically connected with the second load branch, the first output end is electrically connected with the main current mirror of the current mirror unit, the second output end is respectively electrically connected with the slave current mirror of the current mirror unit and the input end of the second signal processing unit, and the second signal processing unit performs phase inversion on input signals; when the voltage of the first input end is greater than that of the second input end, the voltage comparison unit enables the voltage input end to be communicated with the input end of the second signal processing unit; when the voltage of the first input end is smaller than that of the second input end, the first output end inputs working current to the main current mirror.
8. The circuit according to claim 7, wherein the voltage comparison unit comprises a ninth MOS transistor (P3) and a tenth MOS transistor (P4), a source of the ninth MOS transistor (P3) is electrically connected to a source of the tenth MOS transistor (P4), a drain of the ninth MOS transistor (P3) is a first output terminal of the voltage comparison unit, and a drain of the tenth MOS transistor (P4) is a second output terminal of the voltage comparison unit; the grid electrode of the ninth MOS tube (P3) is a first input end of the voltage comparison unit, the grid electrode of the tenth MOS tube (P4) is a second input end of the voltage comparison unit, and the source electrode of the ninth MOS tube (P3) is a voltage input end of the voltage comparison unit.
9. The circuit of claim 7, wherein the second signal processing unit comprises an inverter.
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| CN202211134702.XA CN115225078B (en) | 2022-09-19 | 2022-09-19 | Level detection circuit and level conversion circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11308092A (en) * | 1998-04-24 | 1999-11-05 | Nec Ic Microcomput Syst Ltd | Level shift circuit and nonvolatile memory provided with the same |
| JP2001185996A (en) * | 1999-12-22 | 2001-07-06 | Nec Ic Microcomput Syst Ltd | Input circuit of semiconductor device |
| JP2014007809A (en) * | 2012-06-22 | 2014-01-16 | Renesas Electronics Corp | Semiconductor integrated circuit and operation method of the same |
| CN107223310A (en) * | 2017-04-13 | 2017-09-29 | 深圳市汇顶科技股份有限公司 | Level shifting circuit and fingerprint identification device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101699772B1 (en) * | 2010-06-17 | 2017-01-26 | 삼성전자주식회사 | Power converter and method of converting power |
| CN115001250A (en) * | 2016-04-01 | 2022-09-02 | 侯经权 | Direct drive power control |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11308092A (en) * | 1998-04-24 | 1999-11-05 | Nec Ic Microcomput Syst Ltd | Level shift circuit and nonvolatile memory provided with the same |
| JP2001185996A (en) * | 1999-12-22 | 2001-07-06 | Nec Ic Microcomput Syst Ltd | Input circuit of semiconductor device |
| JP2014007809A (en) * | 2012-06-22 | 2014-01-16 | Renesas Electronics Corp | Semiconductor integrated circuit and operation method of the same |
| CN107223310A (en) * | 2017-04-13 | 2017-09-29 | 深圳市汇顶科技股份有限公司 | Level shifting circuit and fingerprint identification device |
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