CN115221824A

CN115221824A - Asynchronous reconstruction method and device and computer equipment

Info

Publication number: CN115221824A
Application number: CN202210846023.9A
Authority: CN
Inventors: 吴少俊; 朱佳明; 吕世猛
Original assignee: Beijing Aurora Xingtong Technology Co ltd
Current assignee: Beijing Aurora Xingtong Technology Co ltd
Priority date: 2022-07-18
Filing date: 2022-07-18
Publication date: 2022-10-21
Anticipated expiration: 2042-07-18
Also published as: CN115221824B

Abstract

The invention discloses an asynchronous reconstruction method, an asynchronous reconstruction device and computer equipment. The asynchronous reconstruction method comprises the following steps: acquiring reconstruction data from a memory, wherein the reconstruction data comprises ELF reconstruction data and/or BIT reconstruction data; and loading the reconstruction data to a target loading position. The invention solves the technical problem that the reconstructed data needs to transmit ELF data and BIT data simultaneously to cause long-time bus occupation in the prior art.

Description

Asynchronous reconstruction method and device and computer equipment

Technical Field

The invention relates to the field of computer internet, in particular to an asynchronous reconstruction method, an asynchronous reconstruction device and computer equipment.

Background

With the unique advantage of Programmable, the FPGA (Field-Programmable Gate Array) chip has taken a lot of place in the wave of all flowers, and based on the characteristics of flexible design, strong compatibility, parallel computation, strong applicability and the like, the FPGA chip is widely applied to a wide range of industries including network communication, industrial control, consumer electronics, data centers, automotive electronics, artificial intelligence and the like. The representative FPGA chip is Xilinx ZYNQ series FPGA SOC, and the ZYNQ architecture can be represented by the following formula: zynq = ARM + FPGA, where ARM is an application-level processor capable of running operating systems like Linux, vxworks, etc., and the Xilinx 7-series FPGA architecture can run Programmable Logic (PL). The QSPI startup process of ZYNQ is divided into three stages: the method comprises a Stage0, a Stage1, an FSBL (First Stage Boot loader) Stage and a Stage2, an SSBL (Second Stage Boot loader) Stage, wherein the bootROM is firmware loaded at the First time of power-on Boot, fixed writing is performed by a manufacturer, a user cannot modify the firmware, a fixed function is to load a small amount of data from a Flash (non-volatile memory), the

stages

1 and 2 are generated by the user and can be configured, and the Stage2 contains reconstruction data, including ELF data required by ARM and BIT data required by FPGA.

Reconfiguration, that is, reconfiguration of software, a conventional reconfiguration method at present is to use a xilinx SDK tool to generate a complete boot. And (3) FSBL + BIT + ELF, then writing BOOT in a corresponding Flash address in an arbitrary transmission or programming mode, and loading Flash data at the current position at the Stage0 Stage when starting the next time, namely completing software reconstruction. The above reconstruction approach has the following disadvantages: 1. for example, zynq7100, the reconstructed data boot. Bin includes a BIT file of 16.6MB and an ELF file of 322KB, and if the ELF file of 322KB is updated separately, the BIT file of 16.6MB which is not changed is packed together and then transmitted as a whole, and the percentage of the real effective data is: 322 KB/(16.6MB + 322kb) =1.86%, which causes great waste of data transmission and data storage stages, but current embedded products are increasingly systematized, peripherals and loads are increasing, and a conventional data or communication bus does not allow a bus to be occupied for long time for data transmission.

Aiming at the problem that the ELF data and the BIT data must be transmitted simultaneously to reconstruct the data in the prior art, so that a bus is occupied for a long time, an effective solution is not provided at present.

Disclosure of Invention

The embodiment of the invention provides an asynchronous reconstruction method, an asynchronous reconstruction device and computer equipment, and at least solves the technical problem that ELF data and BIT data must be transmitted simultaneously to reconstruct data in the prior art, so that a bus is occupied for a long time.

According to an aspect of an embodiment of the present invention, there is provided an asynchronous reconstruction method, including: acquiring reconstruction data from a memory, wherein the reconstruction data comprises ELF reconstruction data and/or BIT reconstruction data; and loading the reconstruction data to a target loading position.

According to another aspect of the embodiments of the present invention, there is also provided an asynchronous reconstruction apparatus, including: the acquisition module is used for acquiring reconstruction data from the memory, and the reconstruction data comprises ELF reconstruction data and/or BIT reconstruction data; and the loading module is used for loading the reconstruction data to the target loading position.

According to another aspect of the embodiments of the present invention, there is also provided a computer device including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the asynchronous reconstruction method when executing the program.

In the embodiment of the invention, the reconstruction data is obtained from the memory, and the reconstruction data comprises ELF reconstruction data and/or BIT reconstruction data; the reconstruction data are loaded to the target loading position, the purposes of flexibly selecting the ELF reconstruction alone, the BIT reconstruction alone or the ELF reconstruction and the BIT reconstruction simultaneously according to requirements are achieved, the size of the reconstruction data is compressed, the bus occupation time is shortened, the technical effect of effectively reducing the error code condition in data transmission is achieved, and the technical problem that the bus is occupied for a long time because the ELF data and the BIT data must be transmitted simultaneously by the reconstruction data in the prior art is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a schematic diagram of an asynchronous reconstruction method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an alternative asynchronous reconstruction method according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of memory distribution of Flash in the prior art;

FIG. 4 is a schematic diagram of an alternative asynchronous reconstruction method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an alternative asynchronous reconstruction method according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of an alternative asynchronous reconstruction method according to an embodiment of the present invention;

fig. 7 is a schematic diagram of an asynchronous reconstruction apparatus according to an embodiment of the present invention.

Detailed Description

It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

In accordance with an embodiment of the present invention, there is provided a method embodiment of an asynchronous reconstruction method, it being noted that the steps illustrated in the flowchart of the figure may be performed in a computer system, such as a set of computer-executable instructions, and that while a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than presented herein.

Fig. 1 is an asynchronous reconstruction method according to an embodiment of the present invention, as shown in fig. 1, the method includes the following steps:

step S102, obtaining reconstruction data from a memory, wherein the reconstruction data comprises ELF reconstruction data and/or BIT reconstruction data;

and step S104, loading the reconstruction data to a target loading position.

Specifically, the embodiment of the invention can be used in the use situation that ZYNQ series products are used and the software code reconstruction is required. For example, for a satellite product use scene, under the condition that software needs to be reconstructed, microwave radio is generally adopted to transmit data, and by using the scheme of the application, the data transmission amount can be reduced, so that the effect of compressing the microwave transmission time length is achieved.

In the embodiment of the invention, the reconstruction data is obtained from the memory, and the reconstruction data comprises ELF reconstruction data and/or BIT reconstruction data; the method and the device load the reconstruction data to a target loading position, achieve the aim of flexibly selecting the ELF reconstruction alone, the BIT reconstruction alone or the ELF reconstruction and the BIT reconstruction simultaneously according to requirements, further achieve the technical effects of compressing the reconstruction data size and shortening the occupied time of a bus, wherein the bus refers to a transmission channel for transmitting the reconstruction data, effectively reduce the error code condition in data transmission, and further solve the technical problem that the reconstruction data needs to transmit the ELF data and the BIT data simultaneously to cause the bus to be occupied for a long time in the prior art.

In an alternative embodiment, the memory includes a boot program, a data partition table, an ELF data storage area, and a BIT data storage area; the startup program comprises an address of a data partition table, the data partition table comprises an address of an ELF data storage area and an address of a BIT data storage area, the ELF data storage area is used for storing ELF data, and the BIT data storage area is used for storing BIT data.

Alternatively, the memory may be a non-volatile memory Flash, which has the advantage that power-off data is not lost. The Boot program may be a First Stage Boot Loader (FSBL), the data partition TABLE may be represented by TABLE, and the FSBL includes an address of TABLE, so that reading TABLE may be implemented, and further, an address of an ELF data storage area and an address of a BIT data storage area in TABLE may be obtained, and ELF data and BIT data may be read from Flash and loaded.

Optionally, the memory distribution of Flash is as shown in fig. 2, where Table _0, table _1, and Table _2 are collectively referred to as Table, and FSBL includes an address of Table, that is, a Table addr, which may point to addresses of starting positions of Table _0, table _1, and Table _ 2; TABLE stores the address of the ELF data storage area, that is, ELF ADDR, specifically indicating the start address of the ELF data area, and the address of the BIT data storage area, that is, BIT ADDR, specifically indicating the start address of the BIT data area, in addition to which the sizes of ELF data and BIT data and the target loading position to be loaded are stored, ELF _0, ELF _1, ELF _2 indicate the ELF data storage areas, and BIT0, BIT1, BIT2 indicate the BIT data storage areas. In the above memory distribution, table _0, ELF _0, and BIT _0 are read-only regions, and cannot be reconstructed, and as shown in fig. 2, the memory distribution of Flash can realize maximum utilization of Flash space.

It should be particularly noted that fig. 3 is a schematic diagram of memory distribution of Flash in the prior art, and it can be seen from fig. 3 that in the conventional manner, the boot.bin are completely isolated from each other, and the ELF data and the BIT data can only act on the boot.bin where the ELF data and the BIT data are located, and cannot cross to other boot.bins; by adopting the memory distribution mode of the Flash, the ELF data and the BIT data can be combined randomly, and the configuration is more flexible.

In an alternative embodiment, the step S102 of obtaining the reconstruction data from the memory includes:

step S202, acquiring an address of a data partition table from a starting program;

step S204, acquiring the address of an ELF data storage area and/or the address of a BIT data storage area in the data partition table according to the address of the data partition table;

in step S206, the reconstruction data is obtained according to the address of the ELF data storage area and/or the address of the BIT data storage area.

Optionally, in the case that the memory already contains reconstruction data, the whole process applied to the ZYNQ series product to acquire and load reconstruction data from the memory may include a bootROM phase, an FSBL phase and a user application phase as shown in fig. 4; step S202 is a bootROM stage before the address of the data partition table is obtained from the startup program, specifically, after the bootROM reads the startup mirror image from Flash, the startup program FSBL is loaded into the OCM (On Chip Memory), the CPU (central processing unit) jumps to the 0 address of the OCM to start executing the startup program FSBL, and the conventional initialization work is firstly completed in the FSBL; the FSBL stage includes: step S202, acquiring an address of a data partition Table from a starting program, specifically, selecting one of a plurality of Table addr registers in FSBL, extracting a pointing address of the selected Table addr register, and reading a TABLE Table with a specified length from the acquired address, namely reading Table _0, table _1, table _2 and the like; the FSBL stage further comprises: step S204, acquiring the address of an ELF data storage area and/or the address of a BIT data storage area in the data partition table according to the address of the data partition table; specifically, table _0, table _1, and Table _2 store an ELF data start address, a length, a target loading position, a BIT data start address, a length, and a target loading position to be loaded, and according to the above information, the corresponding positions of the ELF data storage area and the BIT data storage area in Flash, that is, the address of the ELF data storage area and the address of the BIT data storage area, can acquire the address of the ELF data storage area in the data partition Table according to the reconstruction requirement, or acquire the address of the BIT data storage area, or acquire the address of the ELF data storage area and the address of the BIT data storage area at the same time; the FSBL stage further comprises: step S206, acquiring reconstructed data according to the address of the ELF data storage area and/or the address of the BIT data storage area; the FSBL stage further comprises: step S104, loading the reconstruction data to a target loading position, specifically, loading ELF reconstruction data and/or BIT reconstruction data to a target loading position, where the target loading position may be an OCM or an external DDR (double data rate synchronous dynamic random access memory), ending the FSBL stage, jumping to a user application stage, and completing the loading.

In the above alternative, both the OCM and the CPU are components of a ZYNQ series product.

In an alternative embodiment, the acquiring the reconfiguration data according to the address of the ELF data storage area and/or the address of the BIT data storage area in step S206 includes:

step S302, under the condition that the reconstruction data is ELF reconstruction data, acquiring ELF reconstruction data stored in an ELF data storage area according to the address of the ELF data storage area;

step S304, under the condition that the reconstruction data is BIT reconstruction data, acquiring the BIT reconstruction data stored in the BIT data storage area according to the address of the BIT data storage area;

and step S306, under the condition that the reconstruction data are ELF reconstruction data and BIT reconstruction data, acquiring the ELF reconstruction data stored in the ELF data storage area according to the address of the ELF data storage area, and acquiring the BIT reconstruction data stored in the BIT data storage area according to the address of the BIT data storage area.

The embodiment can realize that when the reconstruction data is ELF reconstruction data, specific situations such as updating of the ELF data and reconstruction of the BIT data are needed, and when the BIT data is not updated and is not needed to be reconstructed, only the ELF data can be acquired without acquiring the BIT data; similarly, when the reconstructed data is BIT reconstructed data, specific situations such as that the BIT data needs to be reconstructed when updated, and when the ELF data is not updated and does not need to be reconstructed, only the BIT data can be acquired without acquiring the ELF data, thereby achieving the effect of acquiring and loading the ELF data and the BIT data in any matching manner.

In an alternative embodiment, if the step S102 fails to acquire the reconstruction data from the memory for a preset number of times, preset ELF data and BIT data are acquired to ensure that the system operates normally and has the capability of continuing reconstruction.

In an alternative embodiment, before the step S102 obtaining the reconstruction data from the memory, the method further includes:

in step S402, the rebuilt data stored in the boot image is programmed into the memory.

Specifically, the original data in the memory is derived from a boot image, after the Zynq series products develop application software by using a self-contained development environment, a boot image BOOT.

Optionally, as shown in fig. 5, the process of regenerating data in the memory, i.e. programming the reconstructed data stored in the boot image into the memory, includes the following steps:

1. bin file structure, obtaining Boot Header (mirror Header) containing offset addresses of Image Header Table and Partition Header Table.

2. According to the offset address of the Partition Header Table, partition Header Table DATA is obtained, wherein the Partition Header Table DATA includes the storage position and size of Partition 1 DATA (mirror DATA 1, usually FSBL), partition 2 DATA (mirror DATA 2, usually BIT), and Partition 3 DATA (mirror DATA 3, usually ELF) in the current boot.

3. Reading DATA according to the storage positions and sizes of the Partition 1 DATA, the Partition 2 DATA and the Partition 3 DATA, and storing the DATA as separate DATA files, wherein the Partition 1 DATA corresponds to the FSBL DATA, the Partition 2 DATA corresponds to the ELF DATA, and the Partition 3 DATA corresponds to the BIT DATA, and optionally, the FSBL DATA is general DATA, so that extraction at each time is not needed, and only the Partition 2 DATA and the Partition 3 DATA can be extracted and stored as the ELF DATA and the BIT DATA.

4. And writing a TABLE file according to the storage positions of the ELF data and the BIT data files planned in advance (the ELF data and the BIT data can be stored in any positions of an ELF partition and a BIT partition in Flash), wherein the TABLE file comprises parameters such as the starting addresses, the lengths, the loading target positions and the like of the ELF data and the BIT data files planned in advance, and generating the corresponding data file from the TABLE file.

The three files of TABLE, ELF and BIT are generated in the above steps, the divided areas can be arranged according to the distribution of the Flash memory, and if the update occurs subsequently, step S402 needs to be executed to write the reconstructed data which is updated into the memory, that is, the reconstructed data stored in the boot image is written into the memory.

In an alternative embodiment, in the case that the reconfiguration data is ELF reconfiguration data, the step S402 of programming the reconfiguration data stored in the boot image into the memory includes:

step S502, the memory acquires ELF reconstruction data stored in the boot image;

step S504, according to the size of ELF reconstruction data and the address of an ELF data storage area, a data partition table is generated;

step S506, the data partition table is programmed according to the address of the data partition table, and ELF reconstruction data is programmed according to the address of the ELF data storage area.

Specifically, as shown in fig. 6, when the reconstructed data is ELF reconstructed data, that is, only ELF data is updated, after software modification is completed, a boot image boot.bin file is generated, ELF data and BIT data in the boot.bin are extracted and stored respectively, a TABLE file is compiled and stored according to ELF _1 and BIT _2 positions in a Flash memory allocation TABLE and the current ELF data size and BIT data size, and the TABLE file is programmed to a TABLE _1 position in a Flash distribution TABLE; and programming the ELF data to an ELF _1 position in a Flash distribution table. That is, the loading of the ELF data can be performed by reconstructing the ELF data alone, the loading of the BIT data is not required, and compared with the conventional method in which the whole boot is required to be reconstructed, the reconstruction method of bin is performed by taking the Zynq series z7100 product as an example, and according to the formula: (1-ELF data size/(BIT data size + ELF data size) = 100% = (1-322 KB/(16.6 MB + 322KB)) = 100% = 98.14%), 98.14% of reconstructed data size can be compressed, wherein 322KB is an empirical value, the actual size is about 322KB according to current engineering empirical software, and 16.6MB is the fixed BIT size of the current series of chips and is fixed.

As shown in the following figures, the conventional mode boot.bin is completely isolated, and the ELF and BIT files only act on the current boot.bin and cannot be used in a cross manner; the design scheme of the patent can be used for arbitrarily combining ELF files and BIT files, and is flexible in configuration

In an alternative embodiment, in the case that the reconfiguration data is BIT reconfiguration data, the step S402 of programming the reconfiguration data stored in the boot image into the memory includes:

step S602, a memory acquires BIT reconstruction data stored in a boot image;

step S604, generating a data partition table according to the size of the BIT reconstruction data and the address of the BIT data storage area;

step S606, the data partition table is programmed according to the address of the data partition table, and BIT reconstruction data is programmed according to the address of the BIT data storage area.

Similarly, when the reconstructed data is BIT reconstructed data, that is, when only BIT data is updated, the individual reconstructed BIT data can be loaded without loading ELF data.

In an alternative embodiment, in the case that the reconstruction data is ELF reconstruction data and BIT reconstruction data, the step S402 of programming the reconstruction data stored in the boot image into the memory includes:

step S702, a memory acquires ELF reconstruction data and BIT reconstruction data stored in a starting mirror image;

step S704, generating a data partition table according to the size of the ELF reconstruction data, the address of the ELF data storage area, the size of the BIT reconstruction data and the address of the BIT data storage area;

step S706, the data partition table is programmed according to the address of the data partition table, the ELF reconstruction data is programmed according to the address of the ELF data storage area, and the BIT reconstruction data is programmed according to the address of the BIT data storage area.

According to the 3 embodiments, compared with the prior art that ELF data or BIT data are required to be updated independently, the ELF + BIT data are required to be packaged into BOOT.bin again, even if the BIT data or the ELF data are not changed, the Flash space is required to be occupied, the method and the device can realize independent ELF reconstruction, independent BIT reconstruction or ELF and BIT reconstruction simultaneously according to the flexibility of requirements, so that the Flash space is optimized, multiple addresses are prevented from being occupied by repeated files, program loading is more flexible, different ELF data and BIT data can be selected to be matched with each other for operation, and different functional requirements of different working occasions are met.

Example 2

According to an embodiment of the present invention, an asynchronous reconstruction apparatus is provided, and fig. 7 illustrates an asynchronous reconstruction apparatus according to an embodiment of the present invention, and as shown in fig. 7, the apparatus includes an obtaining module and a loading module, where the obtaining module is configured to obtain reconstruction data from a memory, and the reconstruction data includes ELF reconstruction data and/or BIT reconstruction data; and the loading module is used for loading the reconstruction data to the target loading position.

It should be noted here that the above acquiring module and loading module correspond to steps S102 to S104 in embodiment 1, and the above modules are the same as the examples and application scenarios realized by the corresponding steps, but are not limited to the disclosure in embodiment 1. It should be noted that the modules described above as part of an apparatus may be implemented in a computer system such as a set of computer-executable instructions.

In an optional embodiment, the obtaining module includes a first obtaining module, a second obtaining module, and a third obtaining module; the first acquisition module is used for acquiring the address of the data partition table from the starting program; the second acquisition module is used for acquiring the address of the ELF data storage area and/or the address of the BIT data storage area in the data partition table according to the address of the data partition table; and the third acquisition module is used for acquiring the reconstruction data according to the address of the ELF data storage area and/or the address of the BIT data storage area.

It should be noted here that the first acquiring module, the second acquiring module and the third acquiring module correspond to step S202 to step S206 in embodiment 1, and the modules are the same as the corresponding steps in implementation examples and application scenarios, but are not limited to the disclosure in embodiment 1. It should be noted that the modules described above as part of an apparatus may be implemented in a computer system such as a set of computer-executable instructions.

In an optional embodiment, the third obtaining module includes a fourth obtaining module, a fifth obtaining module, and a sixth obtaining module, where the fourth obtaining module is configured to, when the reconstruction data is ELF reconstruction data, obtain ELF reconstruction data stored in the ELF data storage area according to an address of the ELF data storage area; a fifth obtaining module, configured to obtain, when the reconstructed data is BIT reconstructed data, BIT reconstructed data stored in the BIT data storage area according to the address of the BIT data storage area; and the sixth acquisition module is used for acquiring the ELF reconstruction data stored in the ELF data storage area according to the address of the ELF data storage area and acquiring the BIT reconstruction data stored in the BIT data storage area according to the address of the BIT data storage area under the condition that the reconstruction data are the ELF reconstruction data and the BIT reconstruction data.

It should be noted here that the first acquiring module, the second acquiring module and the third acquiring module correspond to step S302 to step S306 in embodiment 1, and the modules are the same as the corresponding steps in implementation examples and application scenarios, but are not limited to the disclosure in embodiment 1. It should be noted that the modules described above as part of an apparatus may be implemented in a computer system such as a set of computer-executable instructions.

In an alternative embodiment, the apparatus further comprises: and the programming module is used for programming the reconstruction data stored in the boot image into the memory before the acquisition module acquires the reconstruction data from the memory.

It should be noted here that the above-mentioned interface programming module corresponds to step S402 in embodiment 1, and the above-mentioned module is the same as the example and application scenario realized by the corresponding step, but is not limited to the disclosure of embodiment 1. It should be noted that the modules described above as part of an apparatus may be implemented in a computer system such as a set of computer-executable instructions.

In an optional embodiment, in the case that the reconstruction data is ELF reconstruction data, the programming module includes a seventh obtaining module, a first generating module, and a first programming module, where the seventh obtaining module is configured to enable the memory to obtain the ELF reconstruction data stored in the boot image; the first generation module is used for generating a data partition table according to the size of ELF reconstruction data and the address of an ELF data storage area; and the first programming module is used for programming the data partition table according to the address of the data partition table and programming ELF reconstruction data according to the address of the ELF data storage area.

It should be noted here that the seventh obtaining module, the first generating module and the first writing module correspond to steps S502 to S506 in embodiment 1, and the modules are the same as the corresponding steps in the implementation example and application scenarios, but are not limited to the disclosure in embodiment 1. It should be noted that the modules described above as part of an apparatus may be implemented in a computer system such as a set of computer-executable instructions.

In an optional embodiment, when the reconstruction data is BIT reconstruction data, the programming module includes an eighth obtaining module, a second generating module, and a second programming module, where the eighth obtaining module is configured to enable the memory to obtain the BIT reconstruction data stored in the boot image; the second generation module is used for generating a data partition table according to the size of the BIT reconstruction data and the address of the BIT data storage area; and the second programming module is used for programming the data partition table according to the address of the data partition table and programming BIT reconstruction data according to the address of the BIT data storage area.

It should be noted here that the eighth obtaining module, the second generating module and the second programming module correspond to steps S602 to S606 in embodiment 1, and the modules are the same as the corresponding steps in implementation examples and application scenarios, but are not limited to the disclosure in embodiment 1. It should be noted that the modules described above as part of an apparatus may be implemented in a computer system such as a set of computer-executable instructions.

In an optional embodiment, in the case that the reconstruction data is ELF reconstruction data and BIT reconstruction data, the programming module includes a ninth obtaining module, a third generating module, and a third programming module, where the ninth obtaining module is configured to enable the memory to obtain the ELF reconstruction data and the BIT reconstruction data stored in the boot image; the third generation module is used for generating a data partition table according to the size of the ELF reconstruction data, the address of the ELF data storage area, the size of the BIT reconstruction data and the address of the BIT data storage area; and the third programming module is used for programming the data partition table according to the address of the data partition table, programming ELF reconstruction data according to the address of the ELF data storage area, and programming BIT reconstruction data according to the address of the BIT data storage area.

It should be noted here that the ninth obtaining module, the third generating module and the third programming module correspond to steps S702 to S706 in embodiment 1, and the modules are the same as the corresponding steps in the implementation example and application scenarios, but are not limited to the disclosure in embodiment 1. It should be noted that the modules described above as part of the apparatus may be implemented in a computer system such as a set of computer executable instructions.

Example 3

According to an embodiment of the present invention, there is provided a storage medium including a stored program, wherein, when the program runs, a device in which the storage medium is located is controlled to execute the asynchronous reconstruction method according to embodiment 1.

Example 4

According to an embodiment of the present invention, a processor for running a program is provided, where the program runs to perform the asynchronous reconstruction method according to embodiment 1.

Example 5

According to an embodiment of the present invention, there is provided a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the asynchronous reconstruction method according to embodiment 1.

Example 6

According to an embodiment of the present invention, a terminal is provided, including an obtaining module, a loading module and a processor, where the obtaining module is configured to obtain reconstruction data from a memory, and the reconstruction data includes ELF reconstruction data and/or BIT reconstruction data; the loading module is used for loading the reconstruction data to a target loading position; and a processor, wherein the processor runs the program, and the program runs the asynchronous reconstruction method according to embodiment 1 on the data output from the acquisition module and the loading module.

Example 7

According to an embodiment of the present invention, a terminal is provided, which includes an obtaining module, a loading module, and a storage medium, where the obtaining module is configured to obtain reconstruction data from a memory, and the reconstruction data includes ELF reconstruction data and/or BIT reconstruction data; the loading module is used for loading the reconstruction data to a target loading position; a storage medium for storing a program, wherein the program performs the asynchronous reconstruction method as described in embodiment 1 on data output from the acquisition module and the loading module at runtime.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

In the above embodiments of the present invention, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described in detail in a certain embodiment.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or may not be executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention, which is substantially or partly contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. An asynchronous reconstruction method, comprising:

acquiring reconstruction data from a memory, wherein the reconstruction data comprises ELF reconstruction data and/or BIT reconstruction data;

and loading the reconstruction data to a target loading position.

2. The method of claim 1, wherein the memory includes a boot program, a data partition table, an ELF data store, and a BIT data store;

the startup program comprises an address of the data partition table, the data partition table comprises an address of the ELF data storage area and an address of the BIT data storage area, the ELF data storage area is used for storing ELF data, and the BIT data storage area is used for storing BIT data.

3. The method of claim 2, wherein retrieving reconstruction data from memory comprises:

acquiring the address of the data partition table from the starting program;

acquiring the address of the ELF data storage area and/or the address of the BIT data storage area in the data partition table according to the address of the data partition table;

and acquiring the reconstruction data according to the address of the ELF data storage area and/or the address of the BIT data storage area.

4. The method according to claim 3, wherein the obtaining the reconfiguration data according to the address of the ELF data memory area and/or the address of the BIT data memory area comprises:

under the condition that the reconstruction data is ELF reconstruction data, acquiring the ELF reconstruction data stored in the ELF data storage area according to the address of the ELF data storage area;

under the condition that the reconstruction data is BIT reconstruction data, acquiring the BIT reconstruction data stored in the BIT data storage area according to the address of the BIT data storage area;

and under the condition that the reconstruction data are ELF reconstruction data and BIT reconstruction data, acquiring the ELF reconstruction data stored in the ELF data storage area according to the address of the ELF data storage area, and acquiring the BIT reconstruction data stored in the BIT data storage area according to the address of the BIT data storage area.

5. The method of any of claims 2-4, wherein prior to retrieving the reconstruction data from the memory, the method further comprises:

programming the reconstructed data stored in the boot image into the memory.

6. The method of claim 5, wherein, in the case that the rebuild data is ELF rebuild data, the programming the rebuild data stored in the boot image into the memory comprises:

the memory obtains the ELF reconfiguration data stored in the boot image;

generating the data partition table according to the size of the ELF reconstruction data and the address of the ELF data storage area;

and programming the data partition table according to the address of the data partition table, and programming the ELF reconstruction data according to the address of the ELF data storage area.

7. The method of claim 5, wherein in the case that the rebuild data is BIT rebuild data, the programming the rebuild data stored in the boot image into the memory comprises:

the memory acquires the BIT reconstruction data stored in the boot image;

generating the data partition table according to the size of the BIT reconstruction data and the address of the BIT data storage area;

and programming the data partition table according to the address of the data partition table, and programming the BIT reconstruction data according to the address of the BIT data storage area.

8. The method of claim 5, wherein in the case that the reconfiguration data is ELF reconfiguration data and BIT reconfiguration data, the programming the reconfiguration data stored in the boot image into the memory comprises:

the memory acquires the ELF reconstruction data and the BIT reconstruction data stored in the boot image;

generating the data partition table according to the size of the ELF reconstruction data, the address of the ELF data storage area, the size of the BIT reconstruction data and the address of the BIT data storage area;

and programming the data partition table according to the address of the data partition table, programming the ELF reconstruction data according to the address of the ELF data storage area, and programming the BIT reconstruction data according to the address of the BIT data storage area.

9. An asynchronous reconstruction device, comprising:

the acquisition module is used for acquiring reconstruction data from a memory, wherein the reconstruction data comprises ELF reconstruction data and/or BIT reconstruction data;

and the loading module is used for loading the reconstruction data to a target loading position.

10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the asynchronous reconstruction method of any one of claims 1 to 8 when executing the program.