CN115202426B

CN115202426B - Digital LDO circuit

Info

Publication number: CN115202426B
Application number: CN202211128108.XA
Authority: CN
Inventors: 赵亮; 王卫华; 付德龙; 王�锋; 马福博; 闵应存
Original assignee: CETC 14 Research Institute
Current assignee: CETC 14 Research Institute
Priority date: 2022-09-16
Filing date: 2022-09-16
Publication date: 2023-02-14
Anticipated expiration: 2042-09-16
Also published as: CN115202426A

Abstract

The invention discloses a digital LDO circuit, which comprises a voltage-frequency converter module, a time-voltage converter module, a frequency quantizer module and a power tube array module, wherein the input of the voltage-frequency converter module is reference voltage, the output of the power tube array module is connected with the input of the other end of the voltage-frequency converter module, and the output of the voltage-frequency converter module is respectively connected with the corresponding nodes of the time-voltage converter module; the voltage frequency converter module is connected with the input of the frequency quantizer module, and the output of the time voltage converter module is connected with the input of the frequency quantizer module; the output of the frequency quantizer module is respectively connected with the control words of the power tube array module, and the output of the power tube array module is the voltage output end of the LDO circuit. The invention solves the problems of high transient response speed of the digital LDO, easy calibration of mismatch between devices, high precision, high digitization degree, easy transplantation, easy low-voltage design and quick power-on establishment time.

Description

Digital LDO circuit

Technical Field

The invention relates to a semiconductor integrated circuit, in particular to a digital LDO circuit.

Background

With the continuous development of electronic systems, the integration level is higher and higher, the power management becomes more and more important, and the Low Dropout Regulator (LDO) develops and evolves over several decades, and the basic architecture tends to mature, and is widely applied to power management chips. In recent years, with the increasing system requirements, the response speed of the conventional analog LDO is limited by the loop bandwidth when the conventional analog LDO faces a large dynamic current, and it is difficult to meet the system requirements.

In a circuit structure of a classic digital LDO proposed in recent years, a clock-controlled comparator is used for replacing an error amplifier in an analog LDO, a switch-type power tube is used for replacing a single power tube in the analog LDO, when a load generates transient large current, the digital LDO depends on the clock-controlled comparator to adjust the number of switches of the power tube, the speed of the digital LDO is limited by the clock frequency and the speed of the comparator, the jump of output voltage is often caused, and the transient response of the digital LDO is poor. Although the transient response has been improved by changing the adjustment method of the power tube array (e.g., dichotomy, etc.), the transient response has the additional response disadvantage of large voltage ripple. In summary, it is a difficult problem to be solved in the industry to increase the transient response speed and the regulation speed of the digital LDO and reduce the output ripple.

Chinese patent CN111555613A discloses a digital LDO structure in "a fast-regulating digital LDO circuit" (application number: 202010361516.4), which improves the transient response of LDO by changing the number of switches in each group in the power transistor array, and its main disadvantages are: a. the speed is still limited by the clock CLK frequency of the comparators, and b, the monitoring range of VOUT voltage is limited by the number of the comparators, and when a large dynamic load occurs, the response speed of the part exceeding the comparison range of the voltage of the comparators is deteriorated.

Chinese patent CN110045774A discloses a digital LDO structure in "a digital LDO circuit with fast transient response" (application number: 201910264898.6), which improves the transient response speed by bisection, and has the following main disadvantages: a. the speed is still limited by the clock CLK frequency of the comparator, b.

The Digital LDO structure in the paper "Time-Based Digital LDO regulator with fractional Controlled Power Transformer Strength and Fast transfer Response" JG Kang, MG Jeong, J Park, C Yoo,2019 IEEE Asian Solid-State Circuits reference (A-SSCC), 20191101 "has the main disadvantages: errors occur when two VCOs oscillate at harmonic frequencies with each other.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a digital LDO circuit which can perform coarse adjustment, intermediate adjustment and fine adjustment of a power tube array. The limitation of a clock signal on the speed of a traditional clock control comparator is avoided, the response speed is improved, and the transient large-current load change condition can be monitored in real time through harmonic detection and frequency fundamental wave monitoring, so that the response of a power tube is accelerated, and the response speed is further improved. The influence of various non-ideal factors in the process of converting the voltage to the frequency and the phase is effectively reduced, and the output voltage precision of the LDO is improved.

The purpose of the invention is realized by the following technical scheme.

A digital LDO circuit, comprising: the input of the voltage frequency converter module is a reference voltage VREF, the output VOUT of the power tube array module is connected with the input VOUT of the other end of the voltage frequency converter module, and the outputs UP, UPB, DN, DNB and RESET of the voltage frequency converter module are respectively connected with corresponding nodes of the time voltage converter module; CLK1, CLK2 of the voltage to frequency converter module is connected to the inputs CLK1, CLK2 of the frequency quantizer module, the outputs VUP, VDN of the time to voltage converter module are connected to the inputs VUP, VDN of the frequency quantizer module; the output Corse, mid and Fine of the frequency quantizer module are respectively connected with the control words Corse, mid and Fine of the power tube array module, and the output VOUT of the power tube array module is the voltage output end of the LDO circuit.

The voltage frequency converter module comprises a voltage controlled oscillator VCO1, a voltage controlled oscillator VCO2, a phase frequency detector PFD and a double-path selector MUX; the reference voltage VREF and the output voltage VOUT of the LDO are respectively connected with the voltage-controlled oscillator VCO1 and the voltage-controlled oscillator VCO2 after passing through the MUX, the MUX is controlled by a control signal CAL _ EN, the output clock of the voltage-controlled oscillator VCO1 is CLK1, the output clock of the voltage-controlled oscillator VCO2 is CLK2, the CLK1 and the CLK2 are respectively connected with the input of the phase frequency detector circuit PFD, and the output of the phase frequency detector circuit PFD is UP, UPB, DN, DNB and RESET.

The difference between a reference voltage VREF and an output voltage VOUT of the LDO is converted into the difference between frequencies of CLK1 and CLK2 through a voltage-controlled oscillator, the phase difference between the CLK1 and the CLK2 is converted into UP and DN signals through a phase frequency detector PFD, UPB is the inverse of UP, DNB is the inverse of DN, a RESET signal is output after PFD comparison in each period is completed, the voltage-frequency converter module realizes the conversion of a voltage signal into a frequency signal and a phase signal, and the control of an LDO loop is completed through the processing of a subsequent circuit on the frequency signal and the phase signal.

The time-voltage converter module comprises P-type transistors MP1, MP2, MP3 and MP4, N-type transistors MN1 and MN2, current sources I1 and I2 and variable capacitors C1 and C2; the output of the current source I1 is connected to the sources of the P-type transistors MP1 and MP2, the gates of MP1 and MP2 are connected to the nodes UP and UPB, respectively, the drain of MP1 is connected to the upper plate of the variable capacitor C1 and the drain of MN1, the drain of MP2 is connected to ground AVSS, the drain of MP3 is connected to the upper plate of the variable capacitor C2 and the drain of MN2, the drain of MP4 is connected to ground AVSS, the gates of MN1 and MN2 are all connected to RESET, and the source of MN1, the source of MN2, the lower plate of the variable capacitor C1, and the lower plate of the variable capacitor C2 are all connected to ground AVSS.

The time-voltage converter module controls a current source I1 and a current source I2 to respectively charge a variable capacitor C1 and a variable capacitor C2 according to outputs UP and DN of the PFD, phase difference value information is converted into voltages VUP and VDN, VUP voltage pulse width represents phase advance of CLK1, VDN voltage pulse width represents phase advance of CLK2, MP2 and MP1 form a current rudder, MP3 and MP4 also form a current rudder, and MN1 and MN2 release charges on C1 and C2 after each comparison is finished, so that voltage accumulation on C1 and C2 is prevented from being too high to exceed voltage ranges of other circuits.

In the initial stage of power-on, the calibration process is as follows: firstly, VOUT and VREF are shorted through MUX, and then the frequency and phase of CLK1 and CLK2 should be completely equal, and if all devices are ideal devices, the voltage of VUP and VDN should be completely equal, but due to mismatch between two VCOs and between devices in the time-to-voltage converter, VUP is not equal to VDN, and by continuously adjusting the values of variable capacitors C1 and C2 in each period, the VUP voltage is finally equal to the VDN voltage, that is, by adjusting the difference in capacitance between C1 and C2, the non-ideal factors introduced by the devices between VCO1 and VCO2, between I1 and I2, and between MP1 and MP3 are compensated.

The Frequency quantizer module comprises a Frequency-halving circuit DIV2, a Harmonic monitoring circuit Harmonic Det, a Frequency comparator Frequency Cmp, a voltage comparator CMP and a digital algorithm circuit Dig; the CLK1 and the CLK2 are input of a Harmonic monitoring circuit Harmonic Det, and the output of the Harmonic monitoring circuit Harmonic Det is V2; CLK1 and CLK2 are the inputs of the Frequency comparator Frequency Cmp, the output of which is V1; VUP and VDN are inputs to the comparator CMP, the output of which is V0; v0, V1 and V2 are used as the input of the digital algorithm circuit Dig, and the output is coarse control Corse, middle control Mid and Fine control Fine.

The frequency quantizer module monitors and compares frequency harmonics, frequency fundamental waves and phase information of CLK1 and CLK2, the harmonic monitoring circuit is used for monitoring whether the difference between the frequencies of CLK1 and CLK2 is more than one time, if so, a coarse tuning Corse is triggered, and the coarse tuning array part of the power tube array is adjusted; the Frequency comparison circuit Frequency Cmp is used for comparing the difference condition of Frequency fundamental waves between CLK1 and CLK2, correspondingly triggering the middle tuning Mid and adjusting the middle tuning array part of the power tube array; when a load has large transient current change, the frequency difference between CLK1 and CLK2 is increased, the larger the transient current is, the larger the frequency difference between CLK1 and CLK2 is, the larger the transient response is, the smaller the transient response is, the coarse tuning and the middle tuning respectively, the comparator CMP is used for comparing the information of the phase difference between CLK1 and CLK2, is a Fine tuning part, and correspondingly adjusts a Fine tuning array in a power tube array, and the Fine tuning part is used for improving the output accuracy of the LDO.

The power tube array module comprises coarse adjustment, middle adjustment and fine adjustment three-gear power tube arrays, and the number of the power tube arrays is C, M and F; the coarse adjustment power tube array comprises C N-type transistors, control words of the C N-type transistors are connected with the Corse, the middle adjustment power tube array comprises M N-type transistors, control words of the M N-type transistors are connected with the Mid, the Fine adjustment power tube array comprises F N-type transistors, control words of the F N-type transistors are connected with the Fine, and specific values of the C, the M and the F are selected according to practical application scenes.

Compared with the prior art, the invention has the advantages that: the invention converts the voltage signal into frequency and phase signals, and performs coarse adjustment, intermediate adjustment and fine adjustment of the power tube array based on three modes of frequency harmonic monitoring, frequency fundamental wave comparison and phase comparison. The limit of a clock signal to the speed of a traditional clock control comparator is avoided, the response speed is improved, and the transient large-current load change condition can be monitored in real time through harmonic detection and frequency fundamental wave monitoring, so that the response of a power tube is accelerated, and the response speed is further improved. In addition, by using the variable capacitor arrays C1 and C2, the mismatch and other non-ideal factors of various devices on a voltage-to-frequency and phase transition path are calibrated, the influence of various non-ideal factors in the voltage-to-frequency and phase transition process is effectively reduced, and the output voltage precision of the LDO is improved.

The time-voltage converter module in the digital LDO circuit is simple in structure, and the rest except the time-voltage converter module, the power tube array module and the comparator CMP can be comprehensively realized in a full digital mode, so that the proposed digital LDO circuit is easy to transplant among processes. The method has the advantages of visual thought, simple circuit and easy realization.

The invention can avoid the error of the mutual oscillation of the two VCOs on the harmonic frequency through the harmonic monitoring circuit; the characteristics of high response speed and high precision are achieved by respectively controlling three gears of coarse adjustment, medium adjustment and fine adjustment through harmonic monitoring, frequency fundamental wave comparison and phase comparison; mismatch between devices is calibrated through C1 and C2, so that the output precision of the LDO is improved; d. and directly triggering a coarse tuning mode at the power-on time of the LDO to carry out quick establishment. The invention solves the problem of low transient response speed of the digital LDO. The invention is easy to calibrate the mismatch between devices and has high precision. The invention has high digitization degree, easy transplantation and easy low voltage design. The digital LDO has fast power-on establishment time.

Drawings

Fig. 1 is a schematic diagram of a voltage-to-frequency converter module according to the present invention.

Fig. 2 is a schematic diagram of a time-to-voltage converter module according to the present invention.

FIG. 3 is a block diagram of a frequency quantizer according to the present invention.

Fig. 4 is a schematic structural diagram of a power tube array module according to the present invention.

Detailed Description

The invention is described in detail below with reference to the drawings and specific examples.

A digital LDO circuit comprising: the device comprises a voltage frequency converter module, a time voltage converter module, a frequency quantizer module and a power tube array module.

The connection relationship among the modules is as follows:

the input of the voltage-frequency converter module is a reference voltage VREF, the output VOUT of the power tube array module is connected with the input VOUT at the other end of the voltage-frequency converter module, and the outputs UP, UPB, DN, DNB and RESET of the voltage-frequency converter module are respectively connected with corresponding nodes of the time-voltage converter; in addition to the above connections, the CLK1, CLK2 of the voltage to frequency converter module is connected to the inputs CLK1, CLK2 of the frequency quantizer module;

the output VUP and VDN of the time-voltage converter are connected with the input VUP and VDN of the frequency quantizer;

the output Corse, mid and Fine of the frequency quantizer module are respectively connected with the control words Corse, mid and Fine of the power tube array, and the output VOUT of the power tube array module is the voltage output end of the LDO circuit.

The internal connection relation of each module is as follows:

as shown in fig. 1, the voltage-to-frequency converter module includes a voltage-controlled oscillator VCO1, a voltage-controlled oscillator VCO2, a phase frequency detector PFD, and a dual-way selector MUX; the reference voltage VREF and the output voltage VOUT of the LDO are respectively connected with the voltage-controlled oscillator VCO1 and the voltage-controlled oscillator VCO2 after passing through the MUX, the MUX is controlled by a control signal CAL _ EN, the output clock of the voltage-controlled oscillator VCO1 is CLK1, the output clock of the voltage-controlled oscillator VCO2 is CLK2, the CLK1 and the CLK2 are respectively connected with the input of the phase frequency detector circuit PFD, and the output of the phase frequency detector circuit PFD is UP, UPB, DN, DNB and RESET.

The difference between the reference voltage VREF and the LDO output voltage VOUT is converted into a difference between the frequencies of CLK1 and CLK2 by a voltage controlled oscillator, and the phase difference between CLK1 and CLK2 is converted into UP and DN signals by a phase frequency detector PFD. UPB is the inverse of UP, DNB is the inverse of DN, and a RESET signal is output after PFD comparison in each period is finished. The voltage-frequency converter module realizes the conversion from the voltage signal to the frequency and phase signal, and completes the control of the LDO loop through the subsequent circuit processing of the frequency and phase signal.

As shown in fig. 2, the time-to-voltage converter module includes P-type transistors MP1, MP2, MP3, MP4, N-type transistors MN1, MN2, current sources I1, I2, and variable capacitors C1, C2; the output of the current source I1 is connected to the sources of the P-type transistors MP1 and MP2, the gates of MP1 and MP2 are connected to the nodes UP and UPB, respectively, the drain of MP1 is connected to the upper plate of the variable capacitor C1 and the drain of MN1, the drain of MP2 is connected to ground AVSS, the drain of MP3 is connected to the upper plate of the variable capacitor C2 and the drain of MN2, the drain of MP4 is connected to ground AVSS, except for the above connections, the gates of MN1 and MN2 are connected to RESET, and the source of MN1, the source of MN2, the lower plate of the variable capacitor C1, and the lower plate of the variable capacitor C2 are connected to ground AVSS.

The time-voltage converter controls the current source I1 and the current source I2 to respectively charge the variable capacitor C1 and the variable capacitor C2 according to the outputs UP and DN of the PFD, so that phase difference value information in the modules is converted into voltages VUP and VDN, the pulse width length of the VUP voltage represents the phase advance of CLK1, the pulse width length of the VDN voltage represents the phase advance of CLK2, the MP2 and the MP1 form a current rudder, so that non-ideal factors such as charge injection caused by the switching of the current source I1 are reduced, and the MP3 and the MP4 also form a current rudder. After each comparison is finished, the MN1 and the MN2 release the charges on the C1 and the C2, and the condition that the voltage accumulation on the C1 and the C2 is too high to exceed the voltage range of other circuits is avoided.

In the initial stage of power-on, the calibration process is as follows: first, VOUT and VREF are shorted by MUX, and the frequency and phase of CLK1 and CLK2 should be identical, and if all devices are ideal devices, the voltage of VUP and VDN should be identical, but VUP is not equal to VDN due to mismatch between the two VCOs and between the devices in the time-to-voltage converter. By continuously adjusting the values of the variable capacitors C1 and C2 in each period, the VUP voltage is finally equal to the VDN voltage, i.e. by adjusting the difference in capacitance between C1 and C2, the non-ideal factors introduced by the devices between VCO1 and VCO2, between I1 and I2, between MP1 and MP3, etc. are compensated.

As shown in fig. 3, the Frequency quantizer module includes a divide-by-two circuit DIV2, a Harmonic monitoring circuit Harmonic Det, a Frequency comparator Frequency Cmp, a voltage comparator Cmp, and a digital algorithm circuit Dig; CLK1 and CLK2 are input of a Harmonic monitoring circuit Harmonic Det, and the output of the Harmonic monitoring circuit Harmonic Det is V2; CLK1 and CLK2 are the inputs of the Frequency comparator Frequency Cmp, the output of which is V1; VUP and VDN are inputs to the comparator CMP, the output of which is V0; v0, V1 and V2 are used as the input of the digital arithmetic circuit Dig, and the output is coarse adjustment control Corse, middle adjustment control Mid and Fine adjustment control Fine.

The frequency quantizer module monitors and compares frequency harmonics, frequency fundamental waves and phase information of CLK1 and CLK2, the harmonic monitoring circuit is used for monitoring whether the difference between the frequencies of CLK1 and CLK2 is more than one time, if so, a coarse tuning Corse is triggered, and the coarse tuning array part of the power tube array is adjusted; the Frequency comparison circuit Frequency Cmp is used for comparing the difference condition of Frequency fundamental waves between CLK1 and CLK2, correspondingly triggering a middle modulation Mid and adjusting a middle modulation array part of the power tube array; when a load generates large transient current change, the frequency difference value of CLK1 and CLK2 is increased, the larger the transient current is, the larger the frequency difference value between CLK1 and CLK2 is, and the transient response from large to small is respectively responded through coarse adjustment and medium adjustment, so that the response speed is improved. The comparator CMP is used for comparing the information of the phase difference value of the CLK1 and the CLK2, is a Fine adjustment part and correspondingly adjusts a Fine adjustment array in the power tube array, and the Fine adjustment part is used for improving the output accuracy of the LDO.

As shown in fig. 4, the power tube array module includes coarse tuning, middle tuning, and fine tuning three-gear power tube arrays, the number of which is C, M, and F; the coarse adjustment power tube array comprises C N-type transistors, control words of the C N-type transistors are connected with the Corse, the middle adjustment power tube array comprises M N-type transistors, control words of the M N-type transistors are connected with the Mid, the Fine adjustment power tube array comprises F N-type transistors, control words of the F N-type transistors are connected with the Fine, specific values of the C, the M and the F can be selected according to practical application scenes, and the power tube array can be all N-type transistors or all P-type transistors.

The power tube array is divided into a coarse adjustment array, a middle adjustment array and a fine adjustment array which respectively correspond to a coarse adjustment mode, a middle adjustment mode and a fine adjustment mode.

The working principle of the digital LDO circuit is as follows:

the digital LDO circuit provided by the invention realizes loop control by converting a voltage signal into a frequency signal and a phase signal, and avoids the use of a clock control type comparator in the traditional structure. By monitoring the frequency harmonic wave, the frequency fundamental wave difference value and the phase difference value and utilizing three methods of coarse adjustment, intermediate adjustment and fine adjustment, the characteristics of quick response and high progress are realized, and further, all non-ideal factors such as mismatch in the conversion process from a voltage signal to a frequency signal and from the phase signal are calibrated by utilizing the variable capacitor arrays C1 and C2, so that the precision of the output voltage of the digital LDO is improved.

The voltage frequency converter module converts the reference voltage VREF and the output voltage V0UT of the LDO into frequency signals CLK1 and CLK2 through the voltage-controlled oscillators VCO1 and VCO2, and the frequency difference and the phase difference of CLK1 and CLK2 represent the voltage difference of the voltages VREF and V0 UT. The frequency quantizer module firstly monitors the frequency difference condition of CLK1 and CLK2, the Harmonic monitoring circuit Harmonic Det is used for monitoring whether the frequency difference of CLK1 and CLK2 is two times or more, if the frequency difference of CLK1 and CLK2 is two times or more, representing that the voltage difference of VREF and V0UT is larger at the moment, a coarse tuning Corse is opened, and the coarse tuning part in the power tube array is controlled by the Corse. The frequency comparison circuit compares the difference of the fundamental frequencies of CLK1 and CLK2, and the frequency difference also represents the voltage difference between VREF and V0UT, when the fundamental frequency difference controls the middle tuning Mid, and the Mid controls the middle tuning part in the power tube array. The comparator CMP is used to compare the phase difference between CLK1 and CLK2, which controls the Fine section of the power transistor array. For the condition of instantaneous jump of the output voltage V0UT caused by large transient current, a harmonic comparison circuit or a frequency comparison circuit is triggered to perform coarse adjustment and medium adjustment on the power tube array. The transient response speed is improved by using coarse adjustment and medium adjustment, and the accuracy of the output voltage of the digital LDO is improved by using fine adjustment.

The phase frequency detector PFD will extract the phase information between CLK1 and CLK2, the magnitude of the UP and DN pulse widths representing the phase lead and phase lag values of CLK1 compared to CLK2, respectively. The time-to-voltage converter converts the phase difference represented by the pulse widths UP and DN into a difference between the voltages VUP and VDN by charging the capacitor C1 (or C2) through the current source I1 (or I2), which is compared by the comparator CMP.

C1 and C2 in the time-to-voltage comparator calibrate all circuits on the voltage information to frequency and phase information transition paths: firstly, the voltage control end of the VCO2 is in short circuit with VREF, at the same time, a comparator CMP monitors the size conditions of VUP and VDN on C1 and C2, and if the VCO1 and the VCO2, the I1 and the I2, PFD and switches MP1, MP2, MP3 and MP4 are all ideal devices, the VUP is equal to the VDN, actually, due to non-ideal factors such as mismatch between the devices and charge injection, the VUP is not equal to the VDN, at the same time, the values of capacitors C1 and C2 are continuously adjusted in each comparison period according to the high-low condition of an output V0 of the CMP, until the VUP is equal to the VDN, the calibration is finished, and at the same time, the non-ideal factors of all circuits on a conversion path from voltage information to frequency and phase information are reversely counteracted by the C1 and the C2. The calibration improves the conversion precision of voltage to frequency and phase, and simply and effectively improves the precision of the output voltage of the digital LDO.

In addition, at the moment of the establishment of the VOUT, because the voltage difference between the VOUT and the VREF is large at the moment, the harmonic detection circuit can be directly triggered, so that a coarse tuning mode is triggered, and compared with a traditional LDO structure, the establishment time of the VOUT is effectively shortened.

Claims

1. A digital LDO circuit, comprising: the input of the voltage-frequency converter module is a reference voltage VREF, the reference voltage VREF is an input voltage reference of a digital LDO circuit and is provided by an external circuit to serve as the input voltage offset of the digital LDO circuit, the output VOUT of the power tube array module is connected with the input VOUT of the other end of the voltage-frequency converter module, and the outputs UP, UPB, DN, DNB and RESET of the voltage-frequency converter module are respectively connected with corresponding nodes of the time-voltage converter module; CLK1, CLK2 of the voltage-to-frequency converter module is connected to the inputs CLK1, CLK2 of the frequency quantizer module, the time-to-voltage converter module includes variable capacitors C1, C2, the outputs VUP, VDN of the time-to-voltage converter module are upper plate voltage signals of the variable capacitors C1, C2, the pulse width difference of UP and DN is converted into a voltage difference of VUP and VDN, the outputs VUP, VDN of the time-to-voltage converter module are connected to the inputs VUP, VDN of the frequency quantizer module; the output of the frequency quantizer module, namely, corse, mid and Fine, are respectively connected with control words, namely, corse, mid and Fine, of the power tube array module, wherein the Corse, mid and Fine respectively represent coarse tuning, intermediate tuning and Fine tuning carried out by different frequency differences of CLK1 and CLK2, the output VOUT of the power tube array module is a voltage output end of the LDO circuit, and the voltage-frequency converter module comprises a voltage-controlled oscillator VCO1, a voltage-controlled oscillator VCO2, a frequency and phase discriminator PFD and a two-way selector MUX; the reference voltage VREF and the output voltage VOUT of the LDO are respectively connected with the voltage-controlled oscillator VCO1 and the voltage-controlled oscillator VCO2 after passing through the MUX, the MUX is controlled by a control signal CAL _ EN, the output clock of the voltage-controlled oscillator VCO1 is CLK1, the output clock of the voltage-controlled oscillator VCO2 is CLK2, the clock frequencies of the CLK1 and the CLK2 reflect the heights of the VREF and the VOUT, the CLK1 and the CLK2 are respectively connected with the input of the phase frequency detector circuit PFD, the output of the phase frequency detector circuit UPD is UP, DN, DNB and RESET, when the phase of the CLK1 is ahead of the CLK2, the UP pulse width is larger than the DN pulse width of DN, otherwise, the DN pulse width is larger than UP, the difference between the reference voltage VREF and the output voltage VOUT of the LDO is converted into the frequency difference between the CLK1 and the CLK2 through the phase frequency detector PFD, the phase difference between the CLK1 and the DN2 is converted into signals and DN, the UPB is the inverse of the DN, and the UP and DN is inverted, when the comparison of the RESET is finished, the comparison of each output cycle, the comparison of the voltage and the voltage conversion into the signals, and the subsequent control of the frequency conversion of the loop of the frequency of the signals are finished through the frequency detector module, and the control module.

2. The digital LDO circuit of claim 1, wherein: the time-voltage converter module comprises P-type transistors MP1, MP2, MP3 and MP4, N-type transistors MN1 and MN2, current sources I1 and I2 and variable capacitors C1 and C2; the output of the current source I1 is connected with the sources of the P-type transistors MP1 and MP2, the gates of MP1 and MP2 are respectively connected with the nodes UP and UPB, the drain of MP1 is connected with the upper plate of the variable capacitor C1 and the drain of MN1, the drain of MP2 is grounded AVSS, the drain of MP3 is connected with the upper plate of the variable capacitor C2 and the drain of MN2, the drain of MP4 is grounded AVSS, the gate of MN1 and the gate of MN2 are all connected with RESET, and the source of MN1, the source of MN2, the lower plate of the variable capacitor C1 and the lower plate of the variable capacitor C2 are all grounded AVSS.

3. The digital LDO circuit of claim 2, wherein: the time-voltage converter module controls a current source I1 and a current source I2 to respectively charge a variable capacitor C1 and a variable capacitor C2 according to outputs UP and DN of the PFD, phase difference value information is converted into voltages VUP and VDN, VUP voltage pulse width represents phase advance of CLK1, VDN voltage pulse width represents phase advance of CLK2, MP2 and MP1 form a current rudder, MP3 and MP4 also form a current rudder, and MN1 and MN2 release charges on C1 and C2 after each comparison is finished, so that voltage accumulation on C1 and C2 is prevented from being too high to exceed voltage ranges of other circuits.

4. The digital LDO circuit of claim 1, wherein: in the initial stage of power-on, the calibration process is as follows: firstly, VOUT and VREF are shorted through MUX, and then the frequency and phase of CLK1 and CLK2 should be completely equal, and if all devices are ideal devices, the voltage of VUP and VDN should be completely equal, but due to mismatch between two VCOs and between devices in the time-to-voltage converter, VUP is not equal to VDN, and by continuously adjusting the values of variable capacitors C1 and C2 in each period, the VUP voltage is finally equal to the VDN voltage, that is, by adjusting the difference in capacitance between C1 and C2, the non-ideal factors introduced by the devices between VCO1 and VCO2, between I1 and I2, and between MP1 and MP3 are compensated.

5. The digital LDO circuit of claim 1, wherein: the Frequency quantizer module comprises a Frequency halving circuit DIV2, a Harmonic monitoring circuit Harmonic Det, a Frequency comparator Frequency Cmp, a voltage comparator CMP and a digital algorithm circuit Dig; the CLK1 and the CLK2 are input of a Harmonic monitoring circuit Harmonic Det, and the output of the Harmonic monitoring circuit Harmonic Det is V2; CLK1 and CLK2 are the inputs of the Frequency comparator Frequency Cmp, the output of which is V1; VUP and VDN are inputs to the comparator CMP, the output of which is V0; v0, V1 and V2 are used as the input of the digital arithmetic circuit Dig, and the output is coarse adjustment control Corse, middle adjustment control Mid and Fine adjustment control Fine.

6. The digital LDO circuit of claim 5, wherein: the frequency quantizer module monitors and compares frequency harmonics, frequency fundamental waves and phase information of CLK1 and CLK2, the harmonic monitoring circuit is used for monitoring whether the difference between the frequencies of the CLK1 and the CLK2 reaches more than one time, and if the difference reaches more than one time, a rough tuning Corse is triggered to adjust a rough tuning array part of the power tube array; the Frequency comparison circuit Frequency Cmp is used for comparing the difference condition of Frequency fundamental waves between CLK1 and CLK2, correspondingly triggering the middle tuning Mid and adjusting the middle tuning array part of the power tube array; when a load has large transient current change, the frequency difference between CLK1 and CLK2 is increased, the larger the transient current is, the larger the frequency difference between CLK1 and CLK2 is, the larger the transient response is respectively responded to by coarse tuning and middle tuning, the comparator CMP is used for comparing the phase difference information of CLK1 and CLK2, is a Fine tuning part and correspondingly adjusts a Fine tuning array in a power tube array, and the Fine tuning part is used for improving the output accuracy of the LDO.

7. The digital LDO circuit of claim 1, wherein: the power tube array module comprises a coarse adjustment power tube array, a middle adjustment power tube array and a fine adjustment power tube array, and the number of the power tube arrays is C, M and F; the coarse adjustment power tube array comprises C N-type transistors, control words of the C N-type transistors are connected with the Corse, the middle adjustment power tube array comprises M N-type transistors, control words of the M N-type transistors are connected with the Mid, the Fine adjustment power tube array comprises F N-type transistors, control words of the F N-type transistors are connected with the Fine, and specific values of the C, the M and the F are selected according to practical application scenes.