CN117097338A - Voltage digital conversion circuit based on TDC with adjustable delay precision - Google Patents
Voltage digital conversion circuit based on TDC with adjustable delay precision Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/60—Analogue/digital converters with intermediate conversion to frequency of pulses
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Abstract
The invention discloses a voltage digital conversion circuit based on an adjustable delay precision TDC, which comprises: the voltage-time conversion circuit VTC, the feedback circuit FB, the delay chain phase-locked loop circuit DLL and the time-digital conversion circuit TDC. The differential voltage signal is input into a voltage-to-time conversion circuit, the voltage difference is converted into a time interval and is input into a feedback circuit and a time-to-digital conversion circuit, the feedback circuit generates a clock frequency Fref and transmits the clock frequency Fref to the input end of a delay chain phase-locked loop, the output end generates a control voltage Vctrl and transmits the control voltage Vctrl to the input end of the time-to-digital conversion circuit, and the time interval passes through the time-to-digital conversion circuit to complete the conversion work of the whole circuit. The feedback circuit automatically adjusts and matches the input clock frequency Fref of the delay chain phase-locked loop DLL to obtain a corresponding control voltage Vctrl, and the Vctrl can adjust the precision of a delay unit of the TDC voltage-controlled delay chain. And adjusting the maximum quantization range of the TDC to the range of the maximum time output interval of the VTC under the corresponding PVT condition, and finishing accurate conversion.
Description
Technical Field
The invention relates to a voltage digital conversion circuit based on an adjustable delay precision TDC, and belongs to the field of data converters.
Background
In nature, most of the perceived signals are mainly analog signals, and the analog signals need to be processed, so that the subsequent electronic equipment is convenient to use. Thus, the performance of the analog-to-digital converter plays a critical role in the overall circuitry. With the improvement of the CMOS integrated circuit process, the feature size is continuously reduced, and the structural design of the analog circuit is more difficult, so that compared with the analog circuit, the digital circuit can utilize the advantage of the process improvement, the speed is faster, the area is smaller, and the improvement of the conversion speed can reduce the influence of noise on the circuit. In recent years, analog-to-digital converters combine the advantages of voltage domain, time domain and digital circuits, and the functions of analog-to-digital converters are implemented by voltage-to-time converters (VTCs) and time-to-digital converters (TDCs).
The voltage-time converter converts the voltage signal input by difference into a corresponding time interval signal, and then obtains a corresponding digital code through the time-digital converter to finish conversion. However, the process, voltage and temperature (PVT) can affect the charge and discharge rate of the current source to the capacitor in the VTC, change the precision of the delay unit forming the delay chain in the TDC, and affect the stability and accuracy of the TDC, thereby causing a conversion error. According to the invention, the precision of the delay unit of the TDC circuit connected to the feedback circuit and the delay chain phase-locked loop can be automatically adjusted according to the influence of PVT on the time output interval of the TDC, so that the voltage of differential input can output correct digital codes under any PVT environment.
Disclosure of Invention
The invention provides a new self-adaptive quantization mode for the TDC quantized VTC output time interval, which aims to solve the problem that PVT variation affects the accuracy of the voltage time conversion circuit time output interval and the delay chain precision in the time digital conversion circuit, so that the differential input voltage can be converted into a correct digital code in any PVT environment. Because the same differential input voltage difference corresponds to different output time intervals under different PVT conditions of the VTC, namely, the time difference of rising edges of Tstart and Ttop in FIG. 1, the invention provides a voltage-digital conversion circuit based on an adjustable delay precision TDC. The precision of the corresponding Vctrl adjustment delay chain is obtained through time interval feedback to the DLL, even if the VTC is affected by PVT, the same differential voltage input obtains different output time intervals, the DLL circuit can also be matched with different input clock frequencies Fref according to the time interval feedback to adjust the resolution of the TDC, and then the maximum quantization range of the TDC is adjusted to the range of the maximum time output interval of the VTC under the corresponding PVT condition. Thereby completing the accurate conversion from the voltage input signal to the digital output signal.
The above purpose is achieved by the following technical scheme:
a voltage digital conversion circuit based on an adjustable delay precision TDC comprises the following components: the voltage-time conversion circuit VTC, the feedback circuit FB, the delay chain phase-locked loop circuit DLL and the time-digital conversion circuit TDC.
The invention relates to conversion of voltage domain, time domain into digital code. From the overall structure, the differential voltage signal is input into the voltage-to-time conversion circuit, the voltage difference is converted into time intervals and is input into the feedback circuit and the time-to-digital conversion circuit, the feedback circuit generates clock frequency Fref and transmits the clock frequency Fref to the input end of the delay chain phase-locked loop, the output end generates control voltage Vctrl and transmits the control voltage Vctrl to the input end of the time-to-digital conversion circuit, and the time intervals pass through the time-to-digital conversion circuit to complete the conversion work of the overall circuit.
The voltage time conversion circuit comprises sampling switches S1 and S2, sampling capacitors Cp and Cn, two discharging current sources Ip and In and two inverters INV1 and INV2. One ends of the sampling switches S1 and S2 are respectively connected with differential analog input signals VIP and VIN, the other ends of the sampling switches S2 are respectively connected with sampling capacitors Cp and Cn, discharging current sources Ip and In and input ends of inverters INV1 and INV2, and output ends of the inverters INV1 and INV2 are two rising time edges Tstart and Ttop.
The delay chain phase-locked loop circuit DLL consists of a phase frequency detector PFD, a charge pump CP, a voltage-controlled delay chain VCDL and a first-order filter capacitor C. The input end of the phase frequency detector PFD is connected with the reference clock frequency Fref and the output of the last delay unit of the voltage-controlled delay chain, the output is connected with the input of the charge pump, the output Vctrl of the charge pump is connected with the filter capacitor C and the voltage-controlled delay chain, the input of the voltage-controlled delay chain is the reference clock frequency Fref, and the output is connected with the input end of the phase frequency detector.
The time-to-digital conversion circuit comprises a voltage-controlled delay chain VCDL circuit with adjustable delay precision, a D trigger latch circuit and a temperature code revolution number code circuit T2BEncoder. The input end of the voltage-controlled delay chain circuit with adjustable delay precision is a voltage-time conversion circuit output end Tstart signal and a delay chain phase-locked loop output Vctrl signal, the output end is an output signal Q <1:N > of each delay chain and is connected with an input end D of a corresponding D trigger, all clock CLK ends of the D trigger are connected with the voltage-time conversion circuit output end Tstart signal, the input end of the temperature code revolution number code circuit is connected with the output ends of all the D triggers, and the digital code is output from the output end.
The circuit structure of the invention can automatically adjust the time domain quantization range according to different time intervals generated by the time conversion circuit under different PVT conditions by the same differential voltage input, so as to obtain correct digital code output. Therefore, the invention can effectively simplify the circuit structure, save the power consumption of the whole circuit and improve the efficiency of voltage digital conversion.
Drawings
Fig. 1 is a block diagram of the circuit configuration of the present invention.
Fig. 2 is a schematic block diagram of a voltage-to-time conversion circuit according to the present invention.
Fig. 3 is a schematic block diagram of a delay chain phase locked loop circuit of the present invention.
Fig. 4 is a schematic block diagram of the circuit of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the drawings and examples.
A voltage-to-digital conversion circuit based on an adjustable delay precision TDC, as shown in FIG. 1, comprising: the circuit comprises a voltage-to-time conversion circuit (VTC), a feedback circuit (FB), a delay chain phase-locked loop circuit (DLL) and a time-to-digital conversion circuit (TDC). The invention relates to conversion of voltage domain, time domain into digital code. From the overall structure, the voltage-time conversion circuit converts the input differential voltage signals VIP and VIN into corresponding time intervals (time difference between rising edges of Tstart and Tstop) and transmits the time intervals to the input end of the time-digital conversion circuit, meanwhile, the size of the time intervals is processed by the feedback circuit to generate clock frequency Fref and transmit the clock frequency Fref to the input end of the delay chain phase-locked loop, the delay chain phase-locked loop can generate control voltage Vctrl according to Fref correspondence and transmit the control voltage Vctrl to the input end of the time-digital conversion circuit, and the time intervals pass through the time-digital conversion circuit to complete the conversion work of the overall circuit.
A voltage digital conversion circuit based on an adjustable delay precision TDC, wherein two time rising edges Tstart and Ttop output by the voltage digital conversion circuit are in a certain feedback relation with an input clock frequency Fref of a delay chain phase-locked loop (DLL), and the input clock frequency Fref can be adaptively adjusted according to different time intervals so as to ensure that the time range of the TDC which can be quantized is consistent with the maximum time output interval range of a VTC under the corresponding PVT condition.
The basic working principle of the invention is that as shown In fig. 2, a sample-hold circuit firstly samples differential voltage input signals VIP and VIN, samples voltage information on capacitors Cp and Cn for storage, then closes sampling switches S1 and S2, enters a holding stage, then discharges constant current sources Ip and In to discharge the sampling capacitors, the charge on the sampling capacitors is gradually reduced, and the voltages at the input ends of two inverters INV1 and INV2 are gradually reduced. When the voltage is lower than the inversion threshold value of the inverter, the output of the inverter is inverted to generate two time rising edges Tstart and Ttop, and the time interval is quantized by the time digital conversion circuit to generate a corresponding digital code.
The phase detector compares the phases of the two signals, generates an UP signal if the Fref signal leads the output signal of the voltage-controlled delay chain according to the phase difference between the two signals, generates a DOWN signal if the Fref signal lags the output signal of the voltage-controlled delay chain, inputs the DOWN signal into the charge pump, controls the turn-off and turn-on of a current source in the charge pump, charges and discharges a filter capacitor C, generates a corresponding control voltage Vctrl, and further controls the magnitude of the delay precision of the delay unit in the VCDL, and adjusts the phase of the output signal of the VCDL by comparing the phase of the two signals with the reference clock frequency Fref, and then generates a stable phase of the output signal after the Fref signal leads the output signal of the voltage-controlled delay chain, and if the Fref signal lags the output signal of the voltage-controlled delay chain, the DOWN signal is generated, and the corresponding UP signal and DOWN signal are input into the charge pump, so that the turn-off and turn-on of the current source in the charge pump are controlled, and the filter capacitor C is charged and discharged, the corresponding control voltage Vctrl is generated, and the voltage Vcl is regulated, and the phase of the delay precision of the VCDL is regulated again, and the phase of the output signal is regulated repeatedly, and the phase of the output signal is finally, and the output signal is regulated. The integral delay of the voltage-controlled delay chain is the period size of Fref, and after the DLL is locked, the phase difference of signals output by the last delay unit of Fref and VCDL is uniformly distributed on the delay unit of the VCDL. If the VCDL consists of N delay cells, the delay of each delay cell is T Fref /N。
The stable control voltage Vctrl is input into the voltage-controlled delay chain of the TDC, as shown in FIG. 4, the voltage-controlled delay chain in the TDC is consistent with that in the DLL, thereby ensuring that the delay of each delay unit in the TDC is accurately maintained at T Fref N, thereby accurately adjusting the precision of the TDC, ensuring the time input range of the TDC capable of being quantized and the output time of the VTCThe interval ranges are consistent. The input end of the TDC middle-pressure control delay chain is Tstart signal, and the output signal of the delay unit is Q<1:N>Respectively inputting the signals into a D trigger latch circuit, and generating corresponding temperature codes T by using a Ttop signal as a trigger signal of the D trigger<1:N>And finally obtaining the correct digital code output through a temperature code digital code circuit.
It should be understood that the above description is not intended to limit the invention to the particular embodiments disclosed, but to limit the invention to the particular embodiments disclosed, and that the invention is not limited to the particular embodiments disclosed, but is intended to cover modifications, adaptations, additions and alternatives falling within the spirit and scope of the invention.
Claims (8)
1. A voltage to digital conversion circuit based on an adjustable delay precision TDC, comprising: the voltage-time conversion circuit VTC, the feedback circuit FB, the delay chain phase-locked loop circuit DLL and the time-digital conversion circuit TDC;
the differential voltage signal is input into a voltage-to-time conversion circuit, the voltage difference is converted into a time interval and is input into a feedback circuit and a time-to-digital conversion circuit, the feedback circuit generates a clock frequency Fref and transmits the clock frequency Fref to the input end of a delay chain phase-locked loop, the output end generates a control voltage Vctrl and transmits the control voltage Vctrl to the input end of the time-to-digital conversion circuit, and the time interval passes through the time-to-digital conversion circuit to complete circuit conversion work.
2. The voltage-to-digital conversion circuit based on the adjustable delay precision TDC of claim 1, wherein the voltage-to-time conversion circuit VTC includes sampling switches S1, S2, sampling capacitors Cp, cn, two discharge current sources Ip, in and two inverters INV1, INV2; one ends of the sampling switches S1 and S2 are respectively connected with differential analog input signals VIP and VIN, the other ends of the sampling switches S2 are respectively connected with sampling capacitors Cp and Cn, discharging current sources Ip and In and input ends of inverters INV1 and INV2, and output ends of the inverters INV1 and INV2 are two rising time edges Tstart and Ttop.
3. The voltage-to-digital conversion circuit based on the adjustable delay precision TDC according to claim 1, wherein the delay chain phase-locked loop circuit DLL consists of a phase frequency detector PFD, a charge pump CP, a voltage-controlled delay chain VCDL and a first-order filter capacitor C; the input end of the phase frequency detector PFD is connected with the reference clock frequency Fref and the output of the last delay unit of the voltage-controlled delay chain, the output is connected with the input of the charge pump, the output Vctrl of the charge pump is connected with the filter capacitor C and the voltage-controlled delay chain, the input of the voltage-controlled delay chain is the reference clock frequency Fref, and the output is connected with the input end of the phase frequency detector.
4. The voltage-to-digital conversion circuit based on the TDC with adjustable delay precision according to claim 1, wherein the time-to-digital conversion circuit comprises a voltage-controlled delay chain VCDL circuit with adjustable delay precision, a D trigger latch circuit and a temperature code number-of-revolution code circuit T2BEncoder; the input end of the voltage-controlled delay chain circuit with adjustable delay precision is a voltage-time conversion circuit output end Tstart signal and a delay chain phase-locked loop output Vctrl signal, the output end is an output signal Q <1:N > of each delay chain and is connected with an input end D of a corresponding D trigger, all clock CLK ends of the D trigger are connected with the voltage-time conversion circuit output end Tstart signal, the input end of the temperature code revolution number code circuit is connected with the output ends of all the D triggers, and the digital code is output from the output end.
5. The voltage-to-digital conversion circuit based on the TDC with adjustable delay precision according to claim 1, wherein two time rising edges Tstart and Ttop output by the voltage-to-time conversion circuit keep feedback relation with the input clock frequency Fref of the delay chain phase-locked loop DLL, and the input clock frequency Fref is adaptively adjusted along with different time intervals so as to ensure that the time range in which the TDC can be quantized as a whole is consistent with the maximum time output interval range of the VTC under the corresponding PVT condition.
6. The voltage-to-digital conversion circuit based on the TDC with adjustable delay precision according to claim 1, wherein the sample-hold circuit samples differential voltage input signals VIP and VIN, samples voltage information on capacitors Cp and Cn for storage, then turns off sampling switches S1 and S2, enters a hold stage, then discharges constant current sources Ip and In to discharge the sampling capacitors, the charge on the sampling capacitors gradually decreases, and the voltages at the input ends of two inverters INV1 and INV2 gradually decrease; when the voltage is lower than the inversion threshold value of the inverter, the output of the inverter is inverted to generate two time rising edges Tstart and Ttop, and the time interval is quantized by the time digital conversion circuit to generate a corresponding digital code.
7. The voltage-digital conversion circuit based on the TDC with adjustable delay precision according to claim 6, wherein the time interval is input into a feedback circuit for processing at the same time, corresponding clock frequency Fref is generated and transmitted to input ends of a phase frequency discriminator and a voltage-controlled delay chain in a delay chain phase-locked loop circuit structure, the voltage-controlled delay chain comprises a plurality of delay units, each time a delay unit passes through, the clock frequency Fref delays by a time precision delta t, the output of the last delay unit and the reference clock frequency Fref are input into the phase discriminator together, the phase discriminator compares the phases of the two signals, according to the phase difference between the two signals, if the Fref signal is ahead of the output signal of the voltage-controlled delay chain, UP signal is generated, if the Fref signal is behind the output signal of the voltage-controlled delay chain, DOWN signal is generated, the corresponding UP signal and DOWN signal are input into a charge pump, thereby controlling the turn-off and turn-on of a current source in the charge pump, the filter capacitor C is charged and discharged, corresponding control voltage Vctrl is generated, the output of the voltage Vctrl is regulated, the voltage VCtrl is regulated by the delay unit is regulated by the phase delay unit, and the phase of the last control voltage VCtrl is regulated by the last time, and the phase delay unit is regulated by the last time, and the phase delay signal is regulated by the last time signal is regulated by the phase delay signal; the integral delay of the voltage-controlled delay chain is the period size of Fref, and after the DLL is locked, the phase difference of signals output by the last delay unit of Fref and VCDL is uniformly distributed in the delay units of the VCDLApplying; if the VCDL consists of N delay cells, the delay of each delay cell is T Fref /N。
8. The voltage-to-digital conversion circuit based on TDC with adjustable delay precision as set forth in claim 7, wherein the control voltage Vctrl is input into the voltage-controlled delay chain of the TDC, the voltage-controlled delay chain in the TDC is consistent with the voltage-controlled delay chain in the DLL, and the delay of each delay unit in the TDC is ensured to be accurately maintained at T Fref and/N, so that the precision of the TDC is adjusted, and the quantized time input range of the TDC is ensured to be consistent with the output time interval range of the VTC; the input end of the TDC middle-pressure control delay chain is Tstart signal, and the output signal of the delay unit is Q<1:N>Respectively inputting the signals into a D trigger latch circuit, and generating corresponding temperature codes T by using a Ttop signal as a trigger signal of the D trigger<1:N>And finally obtaining the correct digital code output through a temperature code digital code circuit.
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| CN202310928624.9A CN117097338A (en) | 2023-07-27 | 2023-07-27 | Voltage digital conversion circuit based on TDC with adjustable delay precision |
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| CN202310928624.9A CN117097338A (en) | 2023-07-27 | 2023-07-27 | Voltage digital conversion circuit based on TDC with adjustable delay precision |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117555212A (en) * | 2024-01-11 | 2024-02-13 | 深圳市山海半导体科技有限公司 | Time delay module, time-to-digital converter, system and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117555212A (en) * | 2024-01-11 | 2024-02-13 | 深圳市山海半导体科技有限公司 | Time delay module, time-to-digital converter, system and method |
| CN117555212B (en) * | 2024-01-11 | 2024-04-09 | 深圳市山海半导体科技有限公司 | Time delay module, time-to-digital converter, system and method |
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