CN115189690A - Capacitive load step-down level shift circuit - Google Patents

Abstract

The invention relates to a capacitance load step-down level shift circuit, which adopts a capacitance load structure, is applied to a GaN half-bridge drive circuit and aims to solve the influence of negative pressure of the drive circuit.

Description

Capacitive load step-down level shift circuit

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a capacitive load step-down level shift circuit.

Background

GaN, as a third generation semiconductor device, is gradually replacing silicon devices and is widely used in the fields of traditional and new energy, greatly improving the efficiency of electric energy conversion. The half-bridge drive of the GaN power device is an important component of an application system of the GaN power device at present, and the half-bridge drive level shift circuit is a key research technology of the drive. The design of a high-performance level shift circuit to realize low-delay transient noise suppression and GaN negative voltage protection to meet the design requirements of high reliability and low power consumption is a research focus. In the GaN half-bridge gate driving circuit, due to the freewheeling action of the inductive load, the continuous charging of the bootstrap capacitor will make the high-side power supply enter the negative voltage, resulting in the gate-source voltage of the high-side GaN device being too high, thereby breaking down the GaN device.

In order to ensure that the high-side voltage is clamped under the GaN effective grid voltage, a high-side clamping negative voltage resistant circuit needs to be designed to protect a GaN device, a voltage reduction level shift circuit is adopted to monitor the floating state of the high-side voltage in real time and feed the floating state back to a bootstrap charging loop, and the charging time is enabled to avoid the negative voltage time. The level shift circuit structure generally includes a resistance conversion circuit, a capacitance conversion circuit, a positive feedback interlock conversion circuit, a current mode level conversion circuit, and the like.

In order to effectively overcome common mode transient noise and further improve the rapid conversion of the shift circuit, the invention provides a capacitive load step-down level shift circuit which can improve the conversion speed and effectively reduce the interference of common mode noise.

Disclosure of Invention

The invention aims to overcome the problems in the prior art, and provides a capacitive load step-down level shift circuit which adopts a capacitive load structure and is applied to a GaN half-bridge driving circuit, wherein a negative pressure resisting circuit adopts a step-down level shift circuit to monitor the floating state of high-side voltage in real time and feed the voltage back to a bootstrap charging circuit, so that the charging time avoids negative pressure time, the step-down level shift circuit adopts a capacitive load, narrow pulses control the input of the high-side shift circuit, and a circuit controls a capacitive charging and discharging circuit during high-side extension, so that common-mode interference can be effectively reduced, and the conversion speed is high and the power consumption is low.

In order to achieve the technical purpose and achieve the technical effect, the invention is realized by the following technical scheme:

a capacitor load step-down level shift circuit comprises a left channel input end V _IN And a right channel input V _INN Said left channel input terminal V _IN The output end of the inverter INV1 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with a high-side voltage HB, and RC time delay is formed by an internal on-resistance of the inverter INV1 and the capacitor C3 so as to generate short pulses;

the output end of the inverter INV1 is connected with the input end of the buffer BUFF1, the output end of the buffer BUFF1 is connected with the grid electrode of the high-side input PMOS transistor M1, the source electrode of the PMOS transistor M1 is connected with the high-side voltage HB, the drain electrode of the PMOS transistor M1 is connected with the source electrode of the PMOS transistor M3, and the grid electrode of the PMOS transistor M3 is connected with the left-side channel input end V _IN The drain electrode of the PMOS transistor M3 is connected with one end of the capacitor C1, the other end of the capacitor C1 is connected with the ground GND, so that when the PMOS transistor M1 and the PMOS transistor M3 are simultaneously conducted, short pulse control is performed, and the capacitor C1 is charged by the high-side voltage HB through the PMOS transistor M1 and the PMOS transistor M3;

the drain electrode of the PMOS transistor M3 is connected with the input end of the buffer BUFF5 and the positive electrode end of the diode D1, and the output end of the buffer BUFF5 is connected with the output end V _OUT1 The cathode terminal of the diode D1 is connected to the low-side voltage VCC, and the diode D1 serves as a clamping diode for preventing the voltage on the left shift channel from exceeding the low-side voltage VCC.

Further, the left channel input end V _IN The output end of the inverter INV3 is connected with one end of a capacitor C5, the other end of the capacitor C5 is connected with a high side voltage HS, and an RC delay is formed by an internal on-resistance of the inverter INV3 and the capacitor C5;

the output end of the inverter INV3 is connected with the input end of the buffer BUFF3, the output end of the buffer BUFF3 is connected with the grid electrode of the PMOS transistor M5 at the high side, the output end of the buffer BUFF1 is connected with the input end of the inverter INV5, the output end of the inverter INV5 is connected with the grid electrode of the PMOS transistor M7, the source electrode of the PMOS transistor M5 is connected with the high-side voltage HB, the drain electrode of the PMOS transistor M5 is connected with the source electrode of the PMOS transistor M7, the drain electrode of the PMOS transistor M7 is connected with the ground GND through the resistor R1, so that when the PMOS transistor M5 and the PMOS transistor M7 are simultaneously conducted, the short pulse control is carried out, and the drain electrode of the PMOS transistor M7 is at the high level;

the drain of the PMOS transistor M7 is connected to the gate of the NMOS transistor M9, the drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M3, and the source of the NMOS transistor M9 is connected to the GND, so that the gate of the NMOS transistor M9 is turned on when the voltage is high, and the capacitor C1 forms a discharge circuit through the NMOS transistor M9.

Further, the left channel input end V _IN Connected with the input end of the inverter INV0, the pulse signal of the output end of the inverter INV0 enters the right channel to form the input end V of the right channel _INN 。

Further, the right channel input end V _INN The output end of the inverter INV2 is connected with one end of a capacitor C4, the other end of the capacitor C4 is connected with a high side voltage HB, and RC delay is formed by an internal on-resistance of the inverter INV2 and the capacitor C4 so as to generate short pulses;

the output end of the inverter INV2 is connected with the input end of the buffer BUFF2, the output end of the buffer BUFF2 is connected with the grid electrode of the PMOS transistor M2 with high-side input, the source electrode of the PMOS transistor M2 is connected with high-side voltage HB, and the input end V of a right channel _INN The high-side voltage HB is controlled by a short pulse when the PMOS transistor M2 and the PMOS transistor M4 are simultaneously conducted, and the capacitor C2 is charged by the high-side voltage HB through the PMOS transistor M2 and the PMOS transistor M4;

the drain electrode of the PMOS transistor M4 is connected with the input end of the buffer BUFF6 and the positive electrode end of the diode D2, and the output end of the buffer BUFF6 is connected with the output end V _OUT2 And the cathode end of the diode D2 is connected with the low-side voltage VCC, and the diode D2 is used as a clamping diode and used for preventing the voltage on the right-side shift channel from exceeding VCC.

Further, the right channel input end V _INN And an inverter INV4, the output end of the inverter INV4 is connected with one end of the capacitor C6, the other end of the capacitor C6 is connected with the high side voltage HS, and an RC delay is formed by the internal on-resistance of the inverter INV4 and the capacitor C6;

the output end of the inverter INV4 is connected with the input end of the buffer BUFF4, the output end of the buffer BUFF4 is connected with the grid electrode of the PMOS transistor M6 at the high side, the source electrode of the PMOS transistor M6 is connected with the high side voltage HB, the output end of the buffer BUFF2 is connected with the input end of the inverter INV6, the output end of the inverter INV6 is connected with the grid electrode of the PMOS transistor M8, the drain electrode of the PMOS transistor M6 is connected with the source electrode of the PMOS transistor M8, the drain electrode of the PMOS transistor M8 is connected with the ground GND through the resistor R2, so that when the PMOS transistor M6 and the PMOS transistor M8 are simultaneously conducted, short pulse control is carried out, and the drain electrode of the PMOS transistor M8 is at the high level;

the drain of the transistor M8 is connected to the gate of the NMOS transistor M10, the drain of the NMOS transistor M10 is connected to the drain of the PMOS transistor M4, and the source of the NMOS transistor M10 is connected to the GND, so that the gate of the NMOS transistor M10 is turned on when the gate is at a high level, and the capacitor C2 forms a discharge loop through the NMOS transistor M10.

The invention has the beneficial effects that:

the circuit can be applied to a GaN half-bridge driving circuit, a voltage reduction level shift circuit is adopted to monitor the floating state of high-side voltage in real time and feed back the floating state to a bootstrap charging loop, so that the charging time is kept away from negative pressure time, the voltage reduction level shift circuit adopts a capacitance load, narrow pulses control the input of the high-side shift circuit, and a circuit controls a capacitance charging and discharging loop during high-side operation, so that common-mode interference can be effectively reduced, the conversion speed is high, the power consumption is low, a GaN device can be effectively protected, the grid voltage of the GaN device is controlled within a normal working range, the damage of the negative pressure to the GaN device is avoided, and the circuit has good common-mode noise suppression and high-speed excellent effects.

Drawings

FIG. 1 is a schematic diagram of a buck level shift circuit according to the present invention;

FIG. 2 is a timing waveform diagram of each key node of the circuit of the present invention;

FIG. 3 is a schematic diagram of the buck level shift circuit of the present invention applied to a GaN half-bridge driver IC.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

As shown in FIG. 1, in a capacitor load step-down level shift circuit, a high-side negative voltage detection circuit detects circuit abnormality and outputs a pulse signal to an input end V of the step-down level shift circuit _IN The input signal enters the left channel and the right channel of the step-down level shift circuit in two paths, and comprises a left channel input end V _IN And a right channel input V _INN Said left channel input terminal V _IN The output end of the inverter INV1 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with a high side voltage HB, and an RC delay is formed by an internal on-resistance of the inverter INV1 and the capacitor C3 so as to generate a short pulse;

the output end of the inverter INV1 is connected with the input end of the buffer BUFF1, the output end of the buffer BUFF1 is connected with the grid electrode of the PMOS transistor M1 with high-side input, the grid electrode of the PMOS transistor M1 is conducted when being in a low level, the source electrode of the PMOS transistor M1 is connected with a high-side voltage HB, the drain electrode of the PMOS transistor M1 is connected with the source electrode of the PMOS transistor M3, and the grid electrode of the PMOS transistor M3 is connected with a left-side channel input end V _IN Left channel input terminal V _IN When the voltage is low, the PMOS transistor M3 is conducted, the drain electrode of the PMOS transistor M3 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is connected with the ground GND, so that when the PMOS transistor M1 and the PMOS transistor M3 are conducted simultaneously, short pulse control is performed, and the capacitor C1 is charged by the high-side voltage HB through the PMOS transistor M1 and the PMOS transistor M3;

the drain electrode of the PMOS transistor M3 is connected with the input end of the buffer BUFF5 and the positive electrode end of the diode D1, and the output end of the buffer BUFF5 is connected with the output end V _OUT1 The negative terminal of the diode D1 is connected to the low-side voltage VCC, and the diode D1 serves as a clamping diode for preventing the voltage on the left shift channel from exceeding the low-side voltage VCC.

The left channel input end V _IN Connected with the input end of the inverter INV3, the output end of the inverter INV3 is connected with the capacitor C5One end of the capacitor C5 is connected, the other end of the capacitor C5 is connected with a high-side voltage HS, and an RC time delay is formed by an internal on-resistance of the inverter INV3 and the capacitor C5;

the output end of the inverter INV3 is connected with the input end of the buffer BUFF3, the output end of the buffer BUFF3 is connected with the grid electrode of the PMOS transistor M5 at the high side, the grid electrode of the PMOS transistor M5 is conducted when the grid electrode is at the low level, the output end of the buffer BUFF1 is connected with the input end of the inverter INV5, the output end of the inverter INV5 is connected with the grid electrode of the PMOS transistor M7, the grid electrode of the PMOS transistor M7 is conducted when the grid electrode is at the low level, the source electrode of the PMOS transistor M5 is connected with the voltage HB at the high side, the drain electrode of the PMOS transistor M5 is connected with the source electrode of the PMOS transistor M7, the drain electrode of the PMOS transistor M7 is connected with the ground GND through the resistor R1, so that the short pulse control is realized when the PMOS transistor M5 and the PMOS transistor M7 are conducted simultaneously, and the drain electrode of the PMOS transistor M7 is at the high level;

the drain electrode of the PMOS transistor M7 is connected with the grid electrode of the NMOS transistor M9, the drain electrode of the NMOS transistor M9 is connected with the drain electrode of the PMOS transistor M3, the source electrode of the NMOS transistor M9 is connected with the GND, so that the grid electrode of the NMOS transistor M9 is conducted when the grid electrode is in a high level, and the capacitor C1 forms a discharge loop through the NMOS transistor M9, so that the problem of quick discharge of charges on the capacitor C1 is solved.

The left channel input end V _IN The pulse signal at the output end of the inverter INV0 enters the right channel to form a right channel input end V _INN 。

The right channel input end V _INN The output end of the inverter INV2 is connected with one end of a capacitor C4, the other end of the capacitor C4 is connected with a high side voltage HB, and RC delay is formed by an internal on-resistance of the inverter INV2 and the capacitor C4 so as to generate short pulses;

the output end of the inverter INV2 is connected with the input end of the buffer BUFF2, the output end of the buffer BUFF2 is connected with the grid electrode of the PMOS transistor M2 with high-side input, the grid electrode of the PMOS transistor M2 is conducted when the grid electrode is at low level, the source electrode of the PMOS transistor M2 is connected with high-side voltage HB, and the input end V of a right channel _INN Connected with the gate of PMOS transistor M4, and right channel input terminal V _INN When the voltage is low, the PMOS transistor M4 is conducted, the drain electrode of the PMOS transistor M2 is connected with the source electrode of the PMOS transistor M4, the drain electrode of the PMOS transistor M4 is connected with one end of the capacitor C2, and the other end of the capacitor C2 is connected with the ground GND, so that when the PMOS transistor M2 and the PMOS transistor M4 are conducted simultaneously, short pulse control is performed, and the capacitor C2 is charged by the high-side voltage HB through the PMOS transistor M2 and the PMOS transistor M4;

the drain electrode of the PMOS transistor M4 is connected with the input end of the buffer BUFF6 and the positive electrode end of the diode D2, and the output end of the buffer BUFF6 is connected with the output end V _OUT2 And the cathode end of the diode D2 is connected with the low-side voltage VCC, and the diode D2 is used as a clamping diode and used for preventing the voltage on the right-side shift channel from exceeding VCC.

The right channel input end V _INN The output end of the inverter INV4 is connected with one end of a capacitor C6, the other end of the capacitor C6 is connected with a high side voltage HS, and RC delay is formed by an internal on-resistance of the inverter INV4 and the capacitor C6;

the output end of the inverter INV4 is connected with the input end of the buffer BUFF4, the output end of the buffer BUFF4 is connected with the grid electrode of the PMOS transistor M6 at the high side, the grid electrode of the PMOS transistor M6 is conducted when the grid electrode is at the low level, the source electrode of the PMOS transistor M6 is connected with the voltage HB at the high side, the output end of the buffer BUFF2 is connected with the input end of the inverter INV6, the output end of the inverter INV6 is connected with the grid electrode of the PMOS transistor M8, the grid electrode of the PMOS transistor M8 is conducted when the grid electrode is at the low level, the drain electrode of the PMOS transistor M6 is connected with the source electrode of the PMOS transistor M8, the drain electrode of the PMOS transistor M8 is connected with the ground GND through the resistor R2, so that when the PMOS transistor M6 and the PMOS transistor M8 are conducted simultaneously, the short pulse control is realized, and the drain electrode of the PMOS transistor M8 is at the high level;

the drain electrode of the transistor M8 is connected with the gate electrode of the NMOS transistor M10, the drain electrode of the NMOS transistor M10 is connected with the drain electrode of the PMOS transistor M4, and the source electrode of the NMOS transistor M10 is connected with the GND, so that the gate electrode of the NMOS transistor M10 is conducted when the level is high, and the capacitor C2 forms a discharge loop through the NMOS transistor M10, so that the problem of rapid discharge of charges on the capacitor C2 is solved.

dVs/dt specification in this circuit for common mode noise rejectionThe following were used: vt is the switching threshold voltage of the output buffers (buffer BUFF5 and buffer BUFF 6), typically V _CC (ii)/2, its important index FoM (Figure of Merit), foM = (dVs/dt) × (Vs); for the left channel FoM = (V) _CC -V _T ）/（R _M9 *C _M1 ) Vs, wherein R _M9 Is the on-state equivalent resistance, C, of the NMOS transistor M9 _M1 Is the drain equivalent capacitance of PMOS transistor M1, generally V _T =V _CC /2，Vs=V _CC Namely: foM = [ (V) _T /2)]/( R _M9 *C _M1 )*(2*V _T )=( V _T ) ² /( R _M9 *C _M1 ) (ii) a For a high-speed circuit, the drain capacitance of the input PMOS transistor M1 generally has small change, the size of the NMOS transistor M9 is adjusted to enable the on-resistance to be small, so that the FoM index of the NMOS transistor can be very high, and a good common mode rejection effect can be achieved under high-speed work.

As shown in fig. 3, which is a circuit block diagram of a half-bridge gate driving chip and an application system of a GaN power device, a half-bridge driving circuit is divided into two channels, i.e., a high-side channel and a low-side channel, the high-side driving circuit realizes signal transmission by using a bootstrap boosting mode, and two channels input with HI and LI enter the two channels, i.e., the high-side channel and the low-side channel, respectively; the high-side negative voltage detection circuit outputs a pulse signal to directly control the step-down level shift circuit, in order to prevent the situation that the output of the level shift circuit is simultaneously high level due to the influence of noise, a logic processing protection circuit is added, and a pulse control signal is generated through a buffer to directly control the switch transistor, wherein the control signal is high level during the negative voltage period, the switch transistor is not conducted, and a charging loop of the bootstrap capacitor is cut off; when the high-side GaN device works normally, the control signal is at a low level, the switch transistor is switched on, and the bootstrap capacitor starts to be charged, so that the purpose of protecting the high-side GaN device is achieved.

In addition, it should be noted that the terms "left", "right", and the like in the specification are only used for distinguishing various components, elements, steps, and the like in the specification, and are not used for representing logical relationships or sequential relationships among the various components, elements, steps, and the like, unless specifically stated or indicated.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (5)

1. A capacitor load step-down level shift circuit is characterized by comprising a left channel input end V _IN And a right channel input V _INN Said left channel input end V _IN The output end of the inverter INV1 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with a high side voltage HB, and an RC delay is formed by an internal on-resistance of the inverter INV1 and the capacitor C3 so as to generate a short pulse;

the output end of the inverter INV1 is connected with the input end of the buffer BUFF1, the output end of the buffer BUFF1 is connected with the grid electrode of the high-side input PMOS transistor M1, the source electrode of the PMOS transistor M1 is connected with the high-side voltage HB, the drain electrode of the PMOS transistor M1 is connected with the source electrode of the PMOS transistor M3, and the grid electrode of the PMOS transistor M3 is connected with the left-side channel input end V _IN The drain electrode of the PMOS transistor M3 is connected with one end of the capacitor C1, the other end of the capacitor C1 is connected with the ground GND, so that when the PMOS transistor M1 and the PMOS transistor M3 are simultaneously conducted, short pulse control is performed, and the capacitor C1 is charged by the high-side voltage HB through the PMOS transistor M1 and the PMOS transistor M3;

the drain electrode of the PMOS transistor M3 is connected with the input end of the buffer BUFF5 and the positive electrode end of the diode D1, and the output end of the buffer BUFF5 is connected with the output end V _OUT1 The negative terminal of the diode D1 is connected to the low-side voltage VCC, and the diode D1 serves as a clamping diode for preventing the voltage on the left shift channel from exceeding the low-side voltage VCC.

2. The capacitive load buck level-shifting circuit of claim 1, wherein the left channel input V _IN The output end of the inverter INV3 is connected with one end of a capacitor C5, the other end of the capacitor C5 is connected with a high side voltage HS, and an RC delay is formed by an internal on-resistance of the inverter INV3 and the capacitor C5;

the output end of the inverter INV3 is connected with the input end of the buffer BUFF3, the output end of the buffer BUFF3 is connected with the grid electrode of the PMOS transistor M5 at the high side, the output end of the buffer BUFF1 is connected with the input end of the inverter INV5, the output end of the inverter INV5 is connected with the grid electrode of the PMOS transistor M7, the source electrode of the PMOS transistor M5 is connected with the high-side voltage HB, the drain electrode of the PMOS transistor M5 is connected with the source electrode of the PMOS transistor M7, the drain electrode of the PMOS transistor M7 is connected with the ground GND through the resistor R1, so that when the PMOS transistor M5 and the PMOS transistor M7 are simultaneously conducted, the short pulse control is carried out, and the drain electrode of the PMOS transistor M7 is at the high level;

the drain of the PMOS transistor M7 is connected to the gate of the NMOS transistor M9, the drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M3, and the source of the NMOS transistor M9 is connected to the GND, so that the gate of the NMOS transistor M9 is turned on when the voltage is high, and the capacitor C1 forms a discharge circuit through the NMOS transistor M9.

3. The capacitively loaded buck level shifting circuit of claim 2, wherein the left channel input V is coupled to the input terminal V _IN The pulse signal at the output end of the inverter INV0 enters the right channel to form a right channel input end V _INN 。

4. The capacitive load buck level-shifting circuit of claim 3, wherein the right channel input V _INN The output end of the inverter INV2 is connected with one end of a capacitor C4, the other end of the capacitor C4 is connected with a high side voltage HB, and RC delay is formed by an internal on-resistance of the inverter INV2 and the capacitor C4 so as to generate short pulses;

the output end of the inverter INV2 is connected with the input end of the buffer BUFF2, the output end of the buffer BUFF2 is connected with the grid electrode of the PMOS transistor M2 with high-side input, the source electrode of the PMOS transistor M2 is connected with high-side voltage HB, and the input end V of a right channel _INN The high-side voltage HB is controlled by a short pulse when the PMOS transistor M2 and the PMOS transistor M4 are simultaneously conducted, and the capacitor C2 is charged by the high-side voltage HB through the PMOS transistor M2 and the PMOS transistor M4;

the drain electrode of the PMOS transistor M4 is connected with the input end of the buffer BUFF6 and the positive electrode end of the diode D2, and the output end of the buffer BUFF6 is connected with the output end V _OUT2 And the cathode end of the diode D2 is connected with the low-side voltage VCC, and the diode D2 is used as a clamping diode and used for preventing the voltage on the right-side shift channel from exceeding VCC.

5. The capacitive load buck level-shifting circuit of claim 1, wherein the right channel input V _INN The output end of the inverter INV4 is connected with one end of a capacitor C6, the other end of the capacitor C6 is connected with a high side voltage HS, and RC delay is formed by an internal on-resistance of the inverter INV4 and the capacitor C6;

the output end of the inverter INV4 is connected with the input end of the buffer BUFF4, the output end of the buffer BUFF4 is connected with the grid electrode of the PMOS transistor M6 at the high side, the source electrode of the PMOS transistor M6 is connected with the high side voltage HB, the output end of the buffer BUFF2 is connected with the input end of the inverter INV6, the output end of the inverter INV6 is connected with the grid electrode of the PMOS transistor M8, the drain electrode of the PMOS transistor M6 is connected with the source electrode of the PMOS transistor M8, the drain electrode of the PMOS transistor M8 is connected with the ground GND through the resistor R2, so that when the PMOS transistor M6 and the PMOS transistor M8 are simultaneously conducted, short pulse control is carried out, and the drain electrode of the PMOS transistor M8 is at the high level;

the drain of the transistor M8 is connected to the gate of the NMOS transistor M10, the drain of the NMOS transistor M10 is connected to the drain of the PMOS transistor M4, and the source of the NMOS transistor M10 is connected to the GND, so that the gate of the NMOS transistor M10 is turned on when the gate is at a high level, and the capacitor C2 forms a discharge loop through the NMOS transistor M10.

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