CN115171598B - Blanking circuit and chip - Google Patents
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- CN115171598B CN115171598B CN202210890115.7A CN202210890115A CN115171598B CN 115171598 B CN115171598 B CN 115171598B CN 202210890115 A CN202210890115 A CN 202210890115A CN 115171598 B CN115171598 B CN 115171598B
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- 238000000034 method Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 206010047571 Visual impairment Diseases 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 208000031361 Hiccup Diseases 0.000 description 1
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- 238000010168 coupling process Methods 0.000 description 1
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- 238000007599 discharging Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
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Abstract
The invention relates to a blanking circuit and a chip, which are applied to a scanning display screen comprising a plurality of line channels, wherein the blanking circuit comprises: the scanning module is used for providing driving voltage for the line channel so as to scan the line channel; the control module is used for controlling the scanning module to scan a plurality of line channels line by line; a blanking module controlled by the control module to execute: in the scanning period of a plurality of line channels, blanking the line channels for a preset time length for a plurality of times, wherein intervals exist among the blanking for a plurality of times.
Description
Technical Field
The invention relates to the technical field of electronic display screens, in particular to a blanking circuit and a chip.
Background
In the existing LED display screen, a row driver chip and a column driver chip are usually provided, and both of them drive the LED display screen together, wherein, in order to ensure the display effect of the LED display screen, the row driver chip generally has an "upper blanking" function, and the column driver chip generally has a "lower blanking" function. In the current "top blanking" mode, blanking is typically performed only once for each line channel, and application number 2018112500745 discloses: when the display control chip starts scanning on the current scanning line in the display screen in the line scanning process, the blanking unit does not perform line blanking operation on the current scanning line, and when any other scanning line in the display screen starts scanning, the blanking unit performs line blanking operation on the current scanning line to discharge parasitic charges of the current scanning line. However, this technique has certain problems: the blanking action is continued till the scanning is finished from the scanning start of the second row of scanning lines, so that the energy consumption of the LED display screen is greatly increased.
Disclosure of Invention
In order to avoid the occurrence of afterimages when the display screen works and reduce the energy consumption of the blanking circuit, the invention provides the blanking circuit and a chip.
In a first aspect, an embodiment of the present application provides a blanking circuit, which is applied to a scanning display screen including a plurality of line channels, and includes:
the scanning module is used for providing driving voltage for the line channel so as to scan the line channel;
the control module is used for controlling the scanning module to scan a plurality of line channels line by line;
a blanking module controlled by the control module to execute: and in the scanning period of a plurality of line channels, blanking the line channels for a preset time length for a plurality of times, wherein intervals exist among the blanking for a plurality of times.
In a second aspect, an embodiment of the present application provides a blanking chip, including the blanking circuit provided in the first aspect.
Through the implementation of this application embodiment, in the scanning cycle of a plurality of line passageway, carry out the blanking of predetermineeing the duration to the line passageway many times, there is the interval between blanking many times, can avoid the display screen during operation to appear the ghost, compares with the continuous blanking of prior art, reducible blanking circuit's energy consumption.
Drawings
FIG. 1 is a circuit framework of an embodiment of the present invention;
FIG. 2 is a schematic diagram of row lane scanning according to an embodiment of the present invention;
FIG. 3 is another schematic diagram of row lane scanning according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a blanking period providing unit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a blanking voltage providing circuit according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a blanking module according to an embodiment of the present invention;
fig. 7 is a further circuit schematic of a blanking module of an embodiment of the blanking circuit of the present invention.
Description of reference numerals:
1. a control module; 2. a scanning module; 3. a blanking module; 4. a row channel; 5. a column driver; 6. a voltage dividing unit; 7. the discharge circuit corresponds to the non-enhanced blanking unit; 8. the discharge circuit corresponds to the enhanced blanking unit; 9. a clamping module; 10. a scanning module; 11. a delay unit; 12. and an overcurrent protection module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to fig. 1-7 and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
"coupled" or "connected" in this application includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; but also may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are known to those skilled in the art for achieving the same or similar functional objectives.
Taking the common anode display screen shown in fig. 1 as an example, at a certain time, the control module 1 usually controls only one row channel 4 to be turned on, the control module 1 controls the scanning module 2 to scan the row channels 4 line by line according to a preset scanning sequence, when the scanning module 2 scans a certain row channel 4, the scanning module 2 provides a driving voltage to the row channel 4, and synchronously, the column driver 5 provides a driving current to each column of pixel units on the row channel 4, so that the pixel units in the common anode display screen emit light. For example, the control signals S1, S2, and S3 are sequentially at a low level to control the corresponding row channel 4 to be turned on. Before or after a certain row channel 4 is opened or closed, the PMOS corresponding to the row channel 4 is in an off state, but is limited by factors such as parasitic electricity of each row channel 4 in the common-anode display screen, the row channel 4 (in a high-resistance state) is coupled with the adjacent opened row channel 4, the voltage of the parasitic capacitor corresponding to the row channel 4 is continuously increased, so that the voltage of the positive electrode of the pixel unit in the row channel is synchronously increased, the pixel unit is slightly bright, and the display screen ghost phenomenon is caused. In addition, when the row channel 4 is turned off (i.e., scanning is finished), the PMOS corresponding to the row channel 4 may generate a leakage current, which further increases the voltage rising speed of the parasitic capacitor corresponding to the row channel 4, further deteriorates the display screen image sticking problem, and seriously affects the display effect.
In the prior art, for a certain row channel 4, in a period except for scanning, the row channel 4 is blanked, and although this way can eliminate the charges accumulated by the parasitic capacitance in time, it needs the chip to provide a current for discharging the parasitic capacitance for a long time, and the actual measurement finds that the energy consumption of the row driver is too high. In addition, in general, in the scanning process of scanning the multiple row channels 4 of the display screen, there may be a clamping time period after the scanning of the row channels 4 is finished, so that it is ensured that the voltage of the row channels 4 is kept stable, and the display effect of the pixel units corresponding to the row channels 4 is not affected by too large or too small voltage of the row channels 4. It can be seen that the continuous blanking scheme of the prior art has significant drawbacks.
The above-mentioned problems of the prior art can be solved by the blanking circuit provided by the following embodiments of the present application.
As shown in fig. 1, the present embodiment provides a blanking circuit, which is applied to a scanning display screen including a plurality of line channels 4, and includes a control module 1, a scanning module 2, and a blanking module 3. The scanning module 2 is configured to provide a driving voltage to the row channel 4 to scan the row channel 4. The control module 1 is used for controlling the scanning module 2 to scan a plurality of line channels 4 line by line. The blanking module 3 is controlled by the control module 1 to execute: in the scanning period of a plurality of line channels 4, blanking of the line channels 4 for a preset time length is performed for a plurality of times, and intervals exist among blanking for a plurality of times.
In this embodiment, the scanning display screen may include a common-anode display screen and a common-cathode display screen, and the circuit architecture diagram shown in fig. 1 illustrates a situation that the blanking circuit provided in this embodiment is applied to the common-anode display screen.
In this embodiment, the control module 1 may receive a control signal to control the working states of the scanning module 2 and the blanking module 3.
In some examples, the control module 1 may include a decoder to control the scan module 2 to scan a certain row channel 4 at a certain time. For example, when there are 8 row channels 4 in the scanning display screen, the decoder may be a three-eight decoder, and the control module 1 may receive a binary signal for controlling three data bits output by the three-eight decoder.
In some examples, the control signal may include a CLK signal, an SDI signal, a SET signal, a TBK signal, etc., and the control module 1 may control the blanking module 3 based on one or more of the CLK signal, the SDI signal, the SET signal, the TBK signal, etc., thereby enabling control of blanking voltage, blanking type, blanking time, and blanking duration.
For example, the control module 1 may determine the on-time of the row channel 4 based on the CLK signal and the SDI signal: the method comprises the steps of receiving a CLK signal and an SDI signal, performing logic operation based on the CLK signal and the SDI signal, and controlling one of the row channels OUT0 to be opened when the CLK signal and the SDI signal meet a row opening condition. Taking a CLK signal as a reference signal, controlling the opening of a row channel OUT1 after the row channel OUT0 is opened for a preset time period, controlling the opening of the row channel OUT1 after the row channel OUT0 is opened for the preset time period, and so on, and controlling the opening of the row channel OUT0 after the row channel OUT7 is opened for the preset time period on the assumption that the number of the row channels 4 is 8. Thus, the CLK signal may be considered a delayed reference signal.
FIG. 2 is a schematic diagram of signals applied to a CLK signal, an SDI signal, and each row channel 4 corresponding to a common cathode display, where LINE [0] to LINE [4] respectively represent the row channels OUT0 to OUT4, and indicate that the row channel OUT0 is closed when LINE [0] is high and indicate that the row channel OUT0 is open when LINE [0] is low. The SDI signal may indicate a total scan line number.
As shown in fig. 1, in a scanning period of a plurality of line channels 4, the control module 1 controls the blanking module 3 to blank the line channel 4 for a preset time length for a plurality of times, and there is an interval between the plurality of times of blanking. Because there is interval between blanking many times, make blanking module 3 not work continuously during scanning, but in blanking and rest the course that is carried on alternatively, and the duration of blanking and duration of rest can be set up according to the actual need, so can reduce the energy consumption of the blanking module 3.
In this embodiment, the driving transistor only needs to be driven to operate in a certain time period within the row driving scanning period, so that the voltage of the row channel 4 is maintained at the preset blanking level, and the energy consumption is reduced while the occurrence of the afterimage is prevented.
For a certain line channel 4, the number of times of blanking can be not less than 3, which can ensure to achieve the purpose of eliminating the ghost shadow of the line channel 4, and for a scanning display screen with more line channels 4, the number of times of blanking can also be properly increased, and the number of times of blanking can be set according to actual needs.
In some embodiments, the blanking module 3 may also be controlled by the control module 1 to perform: after one of the line channels 4 is scanned, the other line channels 4 are blanked for a preset time.
For example, the CLK signal may be used as a reference signal, and after the current line channel 4 is switched from on to off, the current line channel is not blanked, and at the same time, the other line channels 4 are blanked, and the blanking duration may be preset.
As shown in fig. 3, during a plurality of scanning periods of the row channel 4, the row channel 4 is blanked for a preset duration for a plurality of times, and the blanking start time for the other row channels 4 is performed at the end of the current channel scanning.
Because the blanking is performed for a preset time length immediately after one line channel 4 is scanned, compared with the prior art in which the blanking is started when the next line channel 4 is scanned, the blanking is more timely and the blanking effect is better.
It should be noted that: when the current row channel 4 is turned off, the blanking function of the current row channel 4 is not turned on, when the next row channel 4 is turned off, the blanking function of the current row channel 4 is turned on, when the other row channel 4 is turned off, the blanking function of the current row channel 4 is turned on again, and so on. That is, during the process of the line driving chip scanning the plurality of line channels 4 successively, for a certain line channel 4, except for a time interval when the power supply of the line channel 4 is stopped, as long as there is a turn-off of other line channels 4, the blanking function is turned on for the present line channel 4, that is, assuming that there are N line channels 4, the number of times of performing blanking for the present line channel 4 may be N-1, assuming that N =8, the number of times of performing blanking for the present line channel 4 is 7, and compared with the aforementioned number of times of blanking which is not less than 3 (which may be selected between 4 and 7), it can be ensured that the present line channel is blanked in time when the scanning of the other line channels 4 is finished, that is, the present line channel is not blanked, an adjacent line channel is blanked, an adjacent line channel does not cause the accumulated charges of the parasitic capacitance of the present line, and the loss of the blanking circuit can be reduced while ensuring the blanking effect. Here, the blanking function described in this embodiment means that the row path 4 is subjected to discharge processing for a certain period of time by a discharge circuit.
In some embodiments, as shown in fig. 4, the control module 1 may include a blanking duration providing unit, where the blanking duration providing unit includes a plurality of delay units 11 and a plurality of delay switches, each delay switch correspondingly controls the number of the delay units 11 to be turned on, and the delay switches are controlled to be turned on according to an externally input control signal to implement blanking of a preset duration.
Specifically, as shown in fig. 4, the blanking period providing unit may include three delay units 11 and three delay switches, the three delay units 11 are connected in series, the delay switch S1 is connected in parallel with the three delay units 11 after being connected in series, the delay switch S2 is connected in parallel with the two delay units 11 after being connected in series, and the delay switch S3 is connected in parallel with one delay unit 11. The control signal received by the control module 1 may include a TBK signal, the blanking duration may be determined based on the TBK signal, and may specifically be determined by a mapping relationship between the TBK signal and the blanking duration, for example, when the blanking duration is selected as a, the control switch S1 is turned on, a current flows through the delay switch S1, all three delay units 11 are short-circuited, and when the blanking duration is selected as B, the control switch S2 is turned on, a current flows through the first delay unit 11 and the delay switch S2 on the left, two delay units 11 on the right are short-circuited, and when the blanking duration is selected as C, the control switch S3 is turned on, a current flows through the two delay units 11 on the left and the delay switch S3 on the right, and one delay unit 11 on the right is short-circuited, therefore, a < B < C, a delay time corresponding to each delay unit 11 may be set correspondingly, for a manufacturer, an appropriate blanking duration may be set according to LED arrays of different products, and only the TBK signal needs to be configured, which is very convenient.
In some embodiments, the blanking module 3 may include a non-enhanced blanking unit and an enhanced blanking unit for providing a discharge circuit for the parasitic capacitance corresponding to the row channel 4, the current of the discharge circuit 7 corresponding to the non-enhanced blanking unit being smaller than the current of the discharge circuit 8 corresponding to the enhanced blanking unit; the control module 1 controls one of the non-enhanced blanking units and the enhanced blanking units to operate.
In particular, the control module 1 may determine the blanking type, which may include enhanced blanking and non-enhanced blanking, based on the data bit level in the received SET signal. And if the blanking type is selected to be enhanced blanking, adopting an enhanced blanking unit to blank, and if the blanking type is selected to be non-enhanced blanking, adopting a non-enhanced blanking unit to blank. Two bits of data bit information of the SET signal may be preset to correspond to enhanced blanking and non-enhanced blanking, respectively.
In this embodiment, the scanning module 2 may include a fifth switch, a first end of the fifth switch may be connected to a power source, a second end of the fifth switch may be connected to the row channel 4, and a third end of the fifth switch may be connected to the control module 1.
The fifth switch tube can be a field effect tube or a triode. As shown in fig. 6, the fifth switching transistor may be a PMOS transistor P0, a source of the PMOS transistor P0 is connected to the power supply, a drain of the PMOS transistor P0 is connected to the row channel 4, and a gate of the PMOS transistor P0 is connected to the control module 1 to be controlled by the control module 1. When the PMOS transistor P0 is turned on, the row channel 4 connected to the drain of the PMOS transistor P0 enters a scan state.
In this embodiment, the discharge circuit 7 corresponding to the non-enhanced blanking unit may include a first switch tube, a second switch tube, and a first resistor, where a controlled end of the first switch tube is used to input the control signal, a first end of the first switch tube is connected to the current input end of the row channel, a second end of the first switch tube is connected to one end of the first resistor, another end of the first resistor is connected to a second end of the second switch tube, a first end of the second switch tube is grounded, and a controlled end of the second switch tube is used to input the control signal.
The first switch tube and the second switch tube can be field effect tubes, triodes and the like. Specifically, the first switching tube and the second switching tube may be P-type tubes, N-type tubes, or the like. When the first switch tube is a P-type tube and the second switch tube is an N-type tube, the first end of the first switch tube may be a source electrode and the second end may be a drain electrode; the first end of the second switch tube may be a source electrode, and the second end may be a drain electrode. As shown in fig. 6, the first switch transistor may be a PMOS transistor P1, the second switch transistor may be an NMOS transistor N1, and the first resistor may be R1.
In this embodiment, the discharge circuit 8 corresponding to the enhanced blanking unit may be regarded as a discharge circuit 7 corresponding to the non-enhanced blanking unit, and a third switching tube, a second resistor, and a third resistor are provided, where one end of the second resistor is connected to the power supply, the other end of the second resistor is connected to a first end of the third switching tube, a second end of the third switching tube is connected to one end of the third resistor, the other end of the third resistor R2 is connected to an input current end of the row channel, and a controlled end of the third switching tube is used for inputting the control signal.
The third switch tube can be a field effect tube, a triode and the like. Specifically, the third switching tube may be a P-type tube, an N-type tube, or the like. When the third switching tube is an N-type tube, the first end of the third switching tube may be a source electrode, and the second end may be a drain electrode. As shown in fig. 6, the third switch tube may be an NMOS tube N2, the second resistor may be an NMOS tube R2, and the third resistor may be an NMOS tube R3.
In this embodiment, as shown in fig. 6, the blanking module may further include a clamping module 9 for connecting to the line channel, and the clamping module 9 may include a fourth switching tube and a fourth resistor, a first end of the fourth switching tube is for connecting to the line channel, a second end of the fourth switching tube is connected to one end of the fourth resistor, another end of the fourth resistor is grounded, and a controlled end of the fourth switching tube is used for inputting the control signal.
The fourth switch tube can be a field effect tube, a triode and the like. Specifically, the fourth switching tube may be a P-type tube, an N-type tube, or the like. When the fourth switching tube is a P-type tube, the first end of the fourth switching tube may be a source, the second end may be a drain, and the controlled end is a gate. As shown in fig. 6, the fourth switch transistor may be a PMOS transistor P2, and the fourth resistor may be R4.
When the PMOS transistor P0 is turned on, it indicates that the OUT port provides the current drive Iout to the corresponding row channel 4, and when the PMOS transistor P0 is turned off, it indicates that the OUT port stops providing the current drive to the row channel 4, so that the blanking actions performed in this embodiment all occur when the PMOS transistor P0 is turned off, and other channels are blanked immediately, and the blanking effect can be improved by timely blanking. The conduction and cut-off states of the PMOS pipe P0 and the NMOS pipe N1 are opposite.
However, due to the influence of factors such as parasitic capacitance of a PCB (printed Circuit Board), the OUT voltage coupling of the current channel can be raised if the adjacent channels are opened, so that an LED lamp externally connected with the OUT is slightly bright, and a residual image can be caused.
When non-enhanced blanking is needed, the PMOS tube P1 and the NMOS tube N1 are conducted, the PMOS tube P0 and the NMOS tube N2 are cut off, and the PMOS tube P2 is cut off, at the moment, because the PMOS tube P1 and the NMOS tube N1 are conducted, the blanking current at the moment is generally the current of the parasitic capacitor corresponding to the row channel 4, the current of the parasitic capacitor is weak, the current flows through the PMOS tube P1, the first resistor R1 and the NMOS tube N1 to discharge the parasitic capacitor, and the charge accumulation of the row channel 4 is prevented, so that the ghost is effectively avoided.
When the enhanced blanking is needed, the NMOS tube N2, the NMOS tube N1, the PMOS tube P1 and the PMOS tube P2 are conducted, the NMOS tube N2, the NMOS tube N1, the PMOS tube P1 and the PMOS tube P2 are equivalent to form an internal circuit, the voltage of an OUT port is fixed at a preset blanking voltage through the internal circuit, the NMOS tube N2 supplies power to the PMOS tube P1 and the PMOS tube P2, the influence of the current of a parasitic capacitor is small, and stable blanking is achieved. At this time, mainly the NMOS transistor N2/PMOS transistor P1 functions (the PMOS transistor P2 plays a role of clamping the voltage of the OUT port and preventing overshoot), and stabilizes the voltage of the OUT port.
Compared with the non-enhanced blanking, the enhanced blanking is performed, the discharge current is provided by the internal circuit, so that the discharge current is more stable and has smaller fluctuation.
On the basis of enhanced blanking, in order to prevent the problem that internal devices are damaged due to the fact that the voltage of the OUT port is too high, a clamping module 9 is added in the blanking module 3, the OUT port can be clamped through a PMOS pipe P2 and a fourth resistor R4, and the phenomenon that the internal devices are damaged due to overshoot is avoided.
In some embodiments, the blanking module 3 may further include an overcurrent protection module 12, where the overcurrent protection module 12 is configured to periodically detect the current of the row channel 4, and stop scanning the row channel 4 when the overcurrent of the row channel 4 is detected for a preset number of periods.
Specifically, as shown in fig. 7, when the overcurrent protection module 12 detects that it is in an overcurrent state, the PMOS transistor P0 is controlled to be turned off.
In addition, the over-current protection module 12 can detect whether the current channel is in an over-current state according to a hiccup mode, that is, the scanning of the row channel 4 is stopped when the current of the row channel 4 is detected to be over-current for a preset number of cycles. The row channel 4 is prevented from being controlled to stop working as long as one-time overcurrent occurs. And controlling the scanning module 2 of the row channel 4 to resume working when the current of the row channel 4 is not over-current is detected again.
It should be noted that the OUT enable signal is active low and the over-current protection module 12 is active high. Specifically, when the row channel 4 is detected to be in a scanning state, the OUT enable signal is at a low level, when the row channel 4 is detected to be in a non-scanning state, the OUT enable signal is at a high level, when the overcurrent protection module 12 detects that the row channel 4 is overcurrent, the overcurrent protection module 12 outputs the high level, and when the overcurrent protection module 12 detects that the current of the row channel 4 is normal, the overcurrent protection module 12 outputs the low level. Taking the circuit structure shown in fig. 7 as an example, when it is detected that the row channel 4 is in a scanning state and the row channel 4 is overcurrent, the row channel 4 is controlled to stop working. No particular limitation is imposed on the logic gate or combination of logic gates specifically used therein. For example, the control of the row channel 4 can be implemented using a combination of OR, NOT, AND, NOR, NAND gates.
In some embodiments, as shown in fig. 5, the control module 1 may further include a blanking voltage providing circuit, the blanking voltage providing circuit adopts a voltage-dividing circuit structure, and includes a plurality of voltage-dividing units 6 and a plurality of switches, the plurality of voltage-dividing units 6 are connected in series and then connected between a power supply and ground, each voltage-dividing unit 6 is connected in parallel with one switch, as shown in fig. 5, the plurality of switches are K1, K2 to Kn, the blanking voltage Vbk may be determined based on the data bits in the SET signal of fig. 2, and the blanking voltage Vbk corresponds to the data bit information one to one. As shown in fig. 5, the data bit information may be associated with the states of the switches K1 to Kn, so as to control the blanking voltage Vbk, and meet the requirements of the blanking voltage Vbk under different conditions. For example, several bits of data bit information of the SET signal correspond to the blanking voltage Vbk.
In the present embodiment, the blanking type and the blanking voltage, etc. may be configured by a preset data bit and/or the number of pulses of the SET signal. The chip of the product is used for different LED arrays, the effect is different, before leaving the factory, the blanking type and the blanking voltage can be configured according to actual needs, and only the SET signal needs to be configured, so that the LED blanking circuit is very convenient.
In some embodiments, the control module 1 is configured to receive an external control signal and determine the preset duration based on each data bit signal of the control signal. For example, the control module 1 may receive an external control signal through a certain port, and in a data period, the level of each data bit of the external control signal may be used to control a blanking mode, a blanking duration, a blanking type, and the like, so that the setting of ports in a chip may be reduced, and port multiplexing may be implemented.
The embodiment of the application further provides a blanking chip, which comprises the blanking circuit of any one of the embodiments, and the blanking circuit is integrated on one chip, so that the blanking chip is convenient to use and small in occupied space.
The foregoing is a preferred embodiment of the present application and is not intended to limit the scope of the application in any way, and any features disclosed in this specification (including the abstract and drawings) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
Claims (9)
1. A blanking circuit for use in a scanning display screen including a plurality of line channels, comprising:
the scanning module is used for providing driving voltage for the line channel so as to scan the line channel;
the control module is used for controlling the scanning module to scan a plurality of line channels line by line;
a blanking module controlled by the control module to perform: blanking the line channel for a preset time length for a plurality of times in the scanning period of a plurality of line channels, wherein intervals exist among the blanking for a plurality of times,
and blanking the other line channels for the preset time length after the scanning of one line channel is finished.
2. The blanking circuit of claim 1, wherein: the control module comprises a blanking time length providing unit, the blanking time length providing unit comprises a plurality of delay units and a plurality of delay switches, each delay switch correspondingly controls the conduction number of the delay units, and the delay switches are controlled to be conducted according to an externally input control signal so as to realize blanking of the preset time length.
3. The blanking circuit of claim 1, wherein the blanking module comprises a non-enhanced blanking unit and an enhanced blanking unit for providing a discharge circuit for a parasitic capacitance corresponding to the row channel, a current of the discharge circuit corresponding to the non-enhanced blanking unit being smaller than a current of the discharge circuit corresponding to the enhanced blanking unit; the control module controls operation of one of the non-enhanced blanking units and the enhanced blanking units.
4. The blanking circuit of claim 3, wherein the discharge circuit comprises a first switch tube, a second switch tube and a first resistor, the controlled terminal of the first switch tube is used for inputting a control signal, the first terminal of the first switch tube is connected to the current input terminal of the row channel, the second terminal of the first switch tube is connected to one terminal of the first resistor, the other terminal of the first resistor is connected to the second terminal of the second switch tube, the first terminal of the second switch tube is grounded, and the controlled terminal of the second switch tube is used for inputting a control signal.
5. The blanking circuit as claimed in claim 4, wherein the discharge circuit further comprises a third switch tube, a second resistor and a third resistor, one end of the second resistor is connected to the power supply, the other end of the second resistor is connected to the first end of the third switch tube, the second end of the third switch tube is connected to one end of the third resistor, the other end of the third resistor R2 is connected to the input current end of the row channel, and the controlled end of the third switch tube is used for inputting the control signal.
6. The blanking circuit of claim 4, wherein the blanking module comprises a clamping module for connecting to the row channel, the clamping module comprises a fourth switch tube and a fourth resistor, a first end of the fourth switch tube is used for connecting to the row channel, a second end of the fourth switch tube is connected to one end of the fourth resistor, the other end of the fourth resistor is grounded, and a controlled end of the fourth switch tube is used for inputting a control signal.
7. The blanking circuit of claim 1, wherein the blanking module further comprises an overcurrent protection module, and wherein the overcurrent protection module is configured to periodically detect a current of a row channel and stop scanning the row channel when the current of the row channel is detected to be overcurrent for a predetermined number of periods.
8. The blanking circuit of any one of claims 1 to 7, wherein the control module is configured to receive an external control signal and to determine the preset duration based on each data bit signal of the control signal.
9. Blanking chip, characterized in that it comprises a blanking circuit according to any one of claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210890115.7A CN115171598B (en) | 2022-07-27 | 2022-07-27 | Blanking circuit and chip |
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| CN202210890115.7A CN115171598B (en) | 2022-07-27 | 2022-07-27 | Blanking circuit and chip |
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| CN115171598B true CN115171598B (en) | 2023-04-18 |
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Address after: 518000, Building 101, Fuman Microelectronics Group Co., Ltd., Intersection of Renmin East Road and Shouhe Road, Jinsha Community, Kengzi Street, Pingshan District, Shenzhen City, Guangdong Province Patentee after: Fuman microelectronics Group Co.,Ltd. Country or region after: China Address before: 518048 1701, building 1, Shenzhen new generation industrial park, No. 136, Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen, Guangdong Province Patentee before: Fuman microelectronics Group Co.,Ltd. Country or region before: China |