CN115167885B - Method and system for loading program after power-on of multi-FPGA system - Google Patents
Method and system for loading program after power-on of multi-FPGA system Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
- G06F8/63—Image based installation; Cloning; Build to order
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F8/71—Version control; Configuration management
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
A program loading method and system after powering on of multiple FPGA system, the method compiles the program file of N FPGAs into PROM file according to the order; controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces; configuring a first FPGA into an active BPI mode, and configuring a second FPGA to an N-th FPGA into a passive SelectMAP mode; after the first FPGA is powered on and initialized, the program file of the first FPGA is loaded from the default address of the external memory, and a CCLK clock signal is output. The invention can reduce the device cost of the whole scheme, greatly reduce the number of external memories required by the FPGA and obviously reduce the device cost; the dependence on external MCU is reduced, and a large amount of MCU interface resources are not required to be consumed and are specially used for burning FPGA programs.
Description
Technical Field
The invention relates to the technical field of computer software deployment, in particular to a method and a system for loading a program after power-on of a multi-FPGA system.
Background
With the continuous development and progress of technology, the market demands are gradually diversified, the functions of electronic devices are more and more complex, the requirements on performance are also higher and higher, the functions and the performance requirements of products are often difficult to be met by a single processor, and the system architecture adopting multiple FPGAs is a trend under the condition. In a multi-FPGA system, how to quickly and reliably load programs to multiple FPGAs after the FPGAs are started is a critical issue.
The current program loading mode of the FPGA mainly comprises the following schemes:
program loading is carried out by using a JTAG interface of the FPGA. However, JTAG is used as a program debugging interface of the FPGA, and is required to be connected with a burner device matched with the FPGA, and a program loading function can be realized by using specific FPGA upper computer software, so that the JTAG is generally only used in a debugging stage and is not suitable for program loading of a formal product.
And the second scheme is to actively read the program from the external memory. After the FPGA finishes the power-on initialization, the FPGA is used for leading to read the bit stream from an external memory, and the bit stream is in an FPGA active loading mode. According to different interfaces, the active loading mode can be further divided into an active serial loading mode and an active parallel loading mode, which are different in terms of data transmission rate, pin use quantity and hardware connection relation. The active mode has the advantages that an external MCU is not needed for control, the FPGA can independently complete starting and program loading, but the active mode uses an additional memory chip, usually NOR/NAND FLASH, and programs are burnt into the memory chip in advance, so that the subsequent program upgrading is inconvenient.
And thirdly, controlling the FPGA to load the program through an external MCU. After the external main control MCU is powered on and initialized by the FPGA, the external main control MCU actively controls and transmits program data to the corresponding FPGA to load the program, and the FPGA is in a passive receiving state at the moment and is in a passive loading mode of the FPGA. The passive loading mode can be equally subdivided into a passive serial loading mode and a passive parallel loading mode. The passive mode has the advantages that an additional memory chip is not needed for loading the program, the MCU is used for controlling the loading of the program, the loading of the program is flexible, the subsequent upgrading is convenient, the MCU resources are additionally used, the MCU has higher requirements, and the system scheme cost can be possibly increased.
In the prior art, if the active mode is used, N memories are additionally needed, and the N memories are burned in advance in the production process of the product, so that the cost is greatly increased, and the production efficiency is reduced; if a passive mode is used, N FPGAs occupy a large amount of interface resources of the MCU, so that most of interfaces of the MCU are used for program loading, and the requirements of other functions of the system cannot be met.
Disclosure of Invention
Therefore, the invention provides a method and a system for loading a program after power-on of a multi-FPGA system, which are used for solving the problems that the cost of the traditional scheme is too high, the MCU interface resource occupation is too large and the subsequent upgrading is inconvenient.
In order to achieve the above object, the present invention provides the following technical solutions: a program loading method after power-on of a multi-FPGA system comprises the following steps:
compiling the program files of the N FPGAs into PROM files in sequence;
controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces;
configuring a first FPGA into an active BPI mode, and configuring a second FPGA to an N-th FPGA into a passive SelectMAP mode;
after the first FPGA is powered on and initialized, the program file of the first FPGA is loaded from the default address of the external memory, and a CCLK clock signal is output.
As a preferable scheme of the program loading method after power-on of the multi-FPGA system, in the process of loading the first FPGA program file, synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check of the first FPGA program file are carried out, and after the first FPGA program file is loaded, the first FPGA enters a starting state.
As a preferable scheme of the program loading method after the power-on of the multi-FPGA system, after the first FPGA enters a starting state, loading a second FPGA program file, and carrying out synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check on the second FPGA program file, wherein after the second FPGA program file is loaded, the second FPGA enters the starting state.
As a preferable scheme of the program loading method after the power-on of the multi-FPGA system, the program file loading process is repeated until the program file loading of the N-th FPGA is completed.
As a preferable scheme of the program loading method after the power-on of the multi-FPGA system, when the program file of the first FPGA stops loading, the first FPGA starts, and after the first FPGA outputs a CSO_B signal to the second FPGA, the second FPGA starts to read and load the program file corresponding to the external memory.
The invention also provides a program loading system after power-on of the multi-FPGA system, which comprises:
the compiling module is used for compiling the program files of the N FPGAs into PROM files in sequence;
the burning module is used for controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces;
the configuration module is used for configuring the first FPGA into an active BPI mode, and configuring the second FPGA to the N-th FPGA into a passive SelectMAP mode;
and the loading module is used for starting to load the program file of the first FPGA from the default address of the external memory after the first FPGA is powered on and initialized, and outputting a CCLK clock signal.
As a preferable scheme of the program loading system after the power-on of the multi-FPGA system, the loading module performs synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check of the first FPGA program file in the loading process of the first FPGA program file, and the first FPGA enters a starting state after the first FPGA program file is loaded.
As a preferable scheme of the program loading system after the power-on of the multi-FPGA system, the loading module starts loading a second FPGA program file after the first FPGA enters a starting state, and performs synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check of the second FPGA program file, and the second FPGA enters the starting state after the second FPGA program file is loaded.
As a preferable scheme of the program loading system after the power-on of the multi-FPGA system, the program file loading process is repeated through the loading module until the program file loading of the Nth FPGA is completed.
As a preferable scheme of the program loading system after the power-on of the multi-FPGA system, in the loading module, when the program file of the first FPGA stops loading, the first FPGA is started, and after the first FPGA outputs a CSO_B signal to the second FPGA, the second FPGA starts to read and load the program file corresponding to the external memory.
The invention has the following advantages: compiling the program files of the N FPGAs into PROM files in sequence; controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces; configuring a first FPGA into an active BPI mode, and configuring a second FPGA to an N-th FPGA into a passive SelectMAP mode; after the first FPGA is powered on and initialized, the program file of the first FPGA is loaded from the default address of the external memory, and a CCLK clock signal is output. The invention can reduce the device cost of the whole scheme, greatly reduce the number of external memories required by the FPGA, reduce N to 1, and obviously reduce the device cost; the dependence on external MCU is reduced, and in the MCU+multi-FPGA system, a large amount of MCU interface resources are not required to be consumed and are specially used for FPGA program burning, so that the specification of the selected MCU is reduced, and the method is more economical and practical; the method is convenient for updating the program in the later stage of the product, and when the FPGA program is updated in the later stage, the updating operation of a plurality of FPGAs is not needed, and only the executable files in the external memory are needed to be updated independently, so that the workload is greatly reduced, and the maintainability of the product is improved; the programming flow of the production link is simplified, in the production stage, an operator is not required to carry out program programming on a plurality of FPGAs respectively, and only the first FPGA is required to be controlled to program the executable file into the external memory, so that the flow is greatly simplified, the manufacturability of the product is improved, and the production quality of the product is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It will be apparent to those skilled in the art from this disclosure that the drawings described below are merely exemplary and that other embodiments may be derived from the drawings provided without undue effort.
The structures, proportions, sizes, etc. shown in the present specification are shown only for the purposes of illustration and description, and are not intended to limit the scope of the invention, which is defined by the claims, so that any structural modifications, changes in proportions, or adjustments of sizes, which do not affect the efficacy or the achievement of the present invention, should fall within the scope of the invention.
Fig. 1 is a flow chart of a program loading method after powering up of the multi-FPGA system provided in embodiment 1 of the present invention;
fig. 2 is a schematic diagram of a framework principle and a corresponding circuit of a multi-FPGA system in a program loading method after powering up the multi-FPGA system according to embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a program loading system after power-up of the multi-FPGA system according to embodiment 2 of the present invention.
Detailed Description
Other advantages and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, which, by way of illustration, is to be read in connection with certain specific embodiments, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Due to the existing active and passive program loading modes, the method can be applied to the use of a single FPGA, and the difference of the advantages and disadvantages is not large for the whole system. However, in the case of multiple FPGAs, their respective drawbacks are amplified, which affects the complexity and cost of the overall system. If N FPGAs need to be loaded with programs, N memories are additionally needed if an active mode is used, and the N memories are burned with programs in advance in the production process of the product, so that the cost is greatly increased, and the production efficiency is reduced; if a passive mode is used, N FPGAs occupy a large amount of interface resources of the MCU, so that most of interfaces of the MCU are used for program loading, and the requirements of other functions of the system cannot be met.
In view of this, the invention provides a method and a system for loading a program after powering up a multi-FPGA system, in which a plurality of FPGAs are connected together in a daisy chain manner, a first FPGA is configured into an active parallel mode, connected with an external memory chip, and outputs a CSO signal as a chip select signal of a second FPGA, and so on, the FPGA of the previous stage outputs the CSO signal to the FPGA of the next stage; the data signals between the external memory chip and the first FPGA are all connected with all FPGAs at the later stage in a bus mode. Therefore, the problems of high cost, excessive occupation of MCU interface resources and the like in the scheme can be solved. The following is a specific implementation case of the technical scheme of the invention.
Example 1
Referring to fig. 1, embodiment 1 of the present invention provides a method for loading a program after power-up of a multi-FPGA system, wherein a first FPGA is configured into an active parallel mode through hardware, a chip select signal is set to an enabled state, and is connected to an external memory, and simultaneously outputs a CSO control signal and a clock signal to a second FPGA, and so on, the CSO control signal and the clock signal of an N-1 FPGA are connected to the N-th FPGA. The second to nth FPGAs are configured in a passive parallel mode by hardware. All data signals of the FPGA are connected together in a bus form and are connected with an external memory chip; the control and address signals of the external memory chip are connected only to the first FPGA.
Auxiliary fig. 2, the procedure of loading the program after powering up the multi-FPGA system is as follows:
s1, compiling program files of N FPGA into PROM files in sequence;
s2, controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces;
s3, configuring a first FPGA into an active BPI mode, and configuring a second FPGA to an N FPGA into a passive SelectMAP mode;
s4, after the first FPGA is powered on and initialized, loading the program file of the first FPGA from the default address of the external memory, and outputting a CCLK clock signal.
In this embodiment, in the process of loading the first FPGA program file, the synchronization byte confirmation, the device ID check, the Bitstream data loading and the CRC check of the first FPGA program file are performed, and after the first FPGA program file is loaded, the first FPGA enters the start state. When the program file of the first FPGA stops loading, the first FPGA starts, after the first FPGA outputs a CSO_B signal to the second FPGA, the second FPGA starts to read and load the program file corresponding to the external memory, and performs synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check of the program file of the second FPGA, and after the loading of the program file of the second FPGA is finished, the second FPGA enters a starting state. And repeating the program file loading process until the program file of the Nth FPGA is loaded.
Specifically, in step S1, program files (Bitstream files) corresponding to the first to nth FPGAs are sequentially selected, and converted into a PROM file, typically in MCS format, supported by the external memory through FPGA development software (imact). When in conversion, a Master-bpi-up mode is selected, and the default is loaded from address 0 in turn.
Specifically, in step S3, the first FPGA is configured to be in an active-BPI mode, the second to nth FPGAs are configured to be in a passive SelectMAP mode, and after the first FPGA is powered on and initialized, the loading procedure is automatically started from address 0 of the external memory, and the CCLK clock is started to be output.
In the loading process, four small steps of synchronous byte confirmation, device ID check, bitstream data loading and CRC check are carried out to ensure the smooth proceeding of the process. When Bitstream data loading is performed, the first FPGA will pull the cso_b signal low, enabling the program loading function of the second FPGA, but the second FPGA will not accept the data at this time because the data cannot pass the sync byte validation step of the second FPGA. After the CRC is checked, the loading process of the first FPGA enters a Finish state, at this time, the loading process of the Bitstream file of the first FPGA is ended, and the first FPGA enters a starting state.
After the Bitstream file loading process of the first FPGA is finished, the Bitstream file of the second subsequent FPGA is not read continuously because the first FPGA is not set with Multi-boot mode. At this time, the enable signal of the second FPGA is already pulled high in the previous step, so at this time, the second FPGA starts to enter the loading process, and starts to perform sync byte validation, device ID verification, bitstream data loading, and CRC verification. And the loading process is repeated until the program of the N-th FPGA is loaded, and the program files in the external memory are read out.
In summary, the method compiles the program files of N FPGAs into PROM files in sequence; controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces; configuring a first FPGA into an active BPI mode, and configuring a second FPGA to an N-th FPGA into a passive SelectMAP mode; after the first FPGA is powered on and initialized, the program file of the first FPGA is loaded from the default address of the external memory, and a CCLK clock signal is output. In the loading process of the first FPGA program file, synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check of the first FPGA program file are carried out, and after the first FPGA program file is loaded, the first FPGA enters a starting state. When the program file of the first FPGA stops loading, the first FPGA starts, after the first FPGA outputs a CSO_B signal to the second FPGA, the second FPGA starts to read and load the program file corresponding to the external memory, and performs synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check of the program file of the second FPGA, and after the loading of the program file of the second FPGA is finished, the second FPGA enters a starting state. And repeating the program file loading process until the program file of the Nth FPGA is loaded. The invention can reduce the device cost of the whole scheme, greatly reduce the number of external memories required by the FPGA, reduce N to 1, and obviously reduce the device cost; the dependence on external MCU is reduced, and in the MCU+multi-FPGA system, a large amount of MCU interface resources are not required to be consumed and are specially used for FPGA program burning, so that the specification of the selected MCU is reduced, and the method is more economical and practical; the method is convenient for updating the program in the later stage of the product, and when the FPGA program is updated in the later stage, the updating operation of a plurality of FPGAs is not needed, and only the executable files in the external memory are needed to be updated independently, so that the workload is greatly reduced, and the maintainability of the product is improved; the programming flow of the production link is simplified, in the production stage, an operator is not required to carry out program programming on a plurality of FPGAs respectively, and only the first FPGA is required to be controlled to program the executable file into the external memory, so that the flow is greatly simplified, the manufacturability of the product is improved, and the production quality of the product is improved.
It should be noted that the method of the embodiments of the present disclosure may be performed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the methods of embodiments of the present disclosure, the devices interacting with each other to accomplish the methods.
It should be noted that the foregoing describes some embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Example 2
Referring to fig. 3, embodiment 2 of the present invention provides a program loading system after power-up of a multi-FPGA system, including:
the compiling module 1 is used for compiling the program files of the N FPGA into PROM files in sequence;
the burning module 2 is used for controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces;
a configuration module 3, configured to configure the first FPGA into an active BPI mode, and configure the second FPGA to the nth FPGA into a passive SelectMAP mode;
and the loading module 4 is used for starting to load the program file of the first FPGA from the default address of the external memory after the first FPGA is powered on and initialized, and outputting a CCLK clock signal.
In this embodiment, the loading module 4 performs synchronous byte confirmation, device ID check, bitstream data loading and CRC check on the first FPGA program file during the loading process of the first FPGA program file, and after the loading of the first FPGA program file is completed, the first FPGA enters the start state.
In this embodiment, the loading module 4 starts loading the second FPGA program file after the first FPGA enters the start state, and performs synchronous byte confirmation, device ID verification, bitstream data loading and CRC verification on the second FPGA program file, and after the second FPGA program file is loaded, the second FPGA enters the start state.
In this embodiment, the loading module 4 repeats the program file loading process until the program file of the nth FPGA is loaded.
In this embodiment, in the loading module 4, when the program file of the first FPGA stops loading, the first FPGA starts, and after the first FPGA outputs the cso_b signal to the second FPGA, the second FPGA starts to read and load the program file corresponding to the external memory.
It should be noted that, because the content of information interaction and execution process between the modules/units of the above system is based on the same concept as the method embodiment in embodiment 1 of the present application, the technical effects brought by the content are the same as the method embodiment of the present application, and the specific content can be referred to the description in the foregoing illustrated method embodiment of the present application, which is not repeated herein.
Example 3
Embodiment 3 of the present invention provides a non-transitory computer readable storage medium having stored therein program code of a post-power-on program loading method of a multi-FPGA system, the program code including instructions for executing the post-power-on program loading method of the multi-FPGA system of embodiment 1 or any possible implementation thereof.
Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk, SSD), etc.
Example 4
Embodiment 4 of the present invention provides an electronic device, including: a memory and a processor;
the processor and the memory complete communication with each other through a bus; the memory stores program instructions executable by the processor that invoke the program instructions to perform the post-power-on program loading method of the multi-FPGA system of embodiment 1 or any possible implementation thereof.
Specifically, the processor may be implemented by hardware or software, and when implemented by hardware, the processor may be a logic circuit, an integrated circuit, or the like; when implemented in software, the processor may be a general-purpose processor, implemented by reading software code stored in a memory, which may be integrated in the processor, or may reside outside the processor, and which may reside separately.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.).
It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may alternatively be implemented in program code executable by computing devices, so that they may be stored in a memory device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps within them may be fabricated into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.
While the invention has been described in detail in the foregoing general description and specific examples, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.
Claims (2)
1. The method for loading the program after power-on of the multi-FPGA system is characterized by comprising the following steps of:
compiling the program files of the N FPGAs into PROM files in sequence;
controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces;
configuring a first FPGA into an active BPI mode, and configuring a second FPGA to an N-th FPGA into a passive SelectMAP mode;
after the first FPGA is powered on and initialized, starting to load a program file of the first FPGA from a default address of an external memory, and outputting a CCLK clock signal;
in the loading process of the first FPGA program file, synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check of the first FPGA program file are carried out, and after the first FPGA program file is loaded, the first FPGA enters a starting state;
after the first FPGA enters a starting state, starting loading a second FPGA program file, and performing synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check on the second FPGA program file, wherein after the second FPGA program file is loaded, the second FPGA enters the starting state;
the loading process of the complex program file is completed until the program file of the Nth FPGA is loaded;
when the program file of the first FPGA stops loading, the first FPGA starts, and after the first FPGA outputs a CSO_B signal to the second FPGA, the second FPGA starts to read and load the program file corresponding to the external memory.
2. A post-power-on program loading system for a multi-FPGA system, comprising:
the compiling module is used for compiling the program files of the N FPGAs into PROM files in sequence;
the burning module is used for controlling a first FPGA to burn the PROM file into an external memory through FPGA development software and JTAG debugging interfaces;
the configuration module is used for configuring the first FPGA into an active BPI mode, and configuring the second FPGA to the N-th FPGA into a passive SelectMAP mode;
the loading module is used for starting to load the program file of the first FPGA from the default address of the external memory after the first FPGA is powered on and initialized, and outputting a CCLK clock signal;
the loading module performs synchronous byte confirmation, equipment ID check, bitstream data loading and CRC check of the first FPGA program file in the loading process of the first FPGA program file, and the first FPGA enters a starting state after the first FPGA program file is loaded;
the loading module starts loading a second FPGA program file after the first FPGA enters a starting state, and confirms synchronous bytes of the second FPGA program file, checks equipment ID, loads Bitstream data and performs CRC check, and the second FPGA enters the starting state after the second FPGA program file is loaded;
repeating the program file loading process until the program file of the Nth FPGA is loaded through the loading module;
in the loading module, when the program file of the first FPGA stops loading, the first FPGA starts, and after the first FPGA outputs a CSO_B signal to the second FPGA, the second FPGA starts to read and load the program file corresponding to the external memory.
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