CN115149968A - Equalizer, driver and equalization method based on code pattern selection - Google Patents

Equalizer, driver and equalization method based on code pattern selection Download PDF

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CN115149968A
CN115149968A CN202210735187.4A CN202210735187A CN115149968A CN 115149968 A CN115149968 A CN 115149968A CN 202210735187 A CN202210735187 A CN 202210735187A CN 115149968 A CN115149968 A CN 115149968A
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code pattern
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CN115149968B (en
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盖伟新
盛凯
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Peking University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0475—Circuits with means for limiting noise, interference or distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
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Abstract

The invention discloses an equalizer, a driver and an equalizing method based on code pattern selection. The equalizer comprises a code pattern detection logic unit and an equalizer module, wherein the equalizer module comprises transistors M5-M8; the code pattern detection logic unit is used for generating a pull-down signal PDP or PDN according to an input MSB signal and an input LSB signal; the source electrode of the M5 is connected with the drain electrode of the M6, the grid electrode of the M5 is connected with the PDN output end of the pull-down signal, and the drain electrode of the M5 is connected with the output node OUTN; the source electrode of the M6 is connected with the ground wire, and the grid electrode of the M6 is connected with the output end of a control signal SEL; the source electrode of the M7 is connected with the drain electrode of the M8, the grid electrode of the M7 is connected with the output end of the pull-down signal PDP, and the drain electrode of the M7 is connected with the output node OUTP; the source electrode of the M8 is connected with the ground wire, and the grid electrode of the M8 is connected with the output end of a control signal SEL; the output nodes OUTN and OUTP are output nodes to which the negative electrode and the positive electrode of the PAM4 driver are connected, respectively.

Description

Equalizer, driver and equalization method based on code pattern selection
Technical Field
The invention belongs to the technical field of integrated circuits, relates to a high-speed serial communication circuit, and particularly relates to an equalizer, a driver and an equalizing method thereof based on code pattern selection.
Background
As shown in fig. 1, the transmitter data path is composed of a Pattern Generator (Pattern Generator), a Serializer (Serializer), a shift and feed forward equalizer, and the feed forward driver is used to pre-equalize the data to eliminate the intersymbol interference caused by the attenuation of the transmission channel.
The code pattern generator generates 64 paths of parallel data, the parallel data are divided into two paths of 32-bit data, the two paths of data respectively enter an MSB path and an LSB path, the circuit structures of the MSB path and the LSB path are the same, and the sizes of drivers at the last stage are different; in the MSB path, 32 paths of parallel data are firstly converted into 1 path of serial data by a serializer, and each data width is 1 UI (UI represents the period of an output signal of a transmitter); the serial data enters a feedforward equalizer to be pre-emphasized, in the feedforward equalizer, the data is delayed by 1, 2, 8230, n UI (the delay units can be configured with different numbers, two delay units are taken as examples in figure 1) through a delay unit compared with the original data, the delayed data passes through a multiplier and enters a PAM4 driver with different weights, and a summator adds all the signals to obtain a pre-emphasized signal; the output is impedance matched using a 50 ohm resistor and bandwidth extension is achieved using an inductor.
The implementation of the feed forward equalization circuit is illustrated by taking the three-tap feed forward equalizer shown in fig. 2 as an example. Each tap consists of two differential pairs and respectively receives MSB data and LSB data to form a PAM4 signal; the data of the main tap is the data which needs to be transmitted at the current moment, and the subscript is marked as n; the data subscript of the front mark tap is n +1, which represents the data at the moment after n, and the interference of the front mark tap on the current moment is eliminated; the data subscript of the post-cursor tap is n-1, which represents the data at the moment before n, and the interference of the post-cursor tap on the current moment is eliminated; the current sources of different taps are all adjustable current sources, and different tap coefficients are realized by changing the current magnitude; all currents are summed in resistors to produce a three tap weighted summed signal.
Due to skin effect and dielectric loss, a transmission channel usually exhibits low-pass characteristics, and its amplitude-frequency response decreases with increasing frequency, so that a large degree of attenuation is generated for high-frequency components of a signal, and the low-frequency components are attenuated less, which results in that the edge of the signal becomes slow, a tail is generated, and intersymbol interference is generated for signals at other times, and an eye diagram of the signal after channel attenuation is shown in fig. 3 (a). The effect of the feedforward equalizer is to pre-emphasize the data at the transmitting end, increase the amplitude of the high frequency component to resist the low-pass characteristic of the channel, and the eye diagram after feedforward equalization and channel attenuation is shown in fig. 3 (b).
The conventional feed-forward equalization method performs the same processing on all signals, all intersymbol interference is eliminated according to the same proportion, and an equalized eye diagram is shown in fig. 3. The eye width and the eye height of the eye pattern are limited by certain code pattern jumping edges, and cannot be further opened, which is specifically represented as follows: the upper eye is limited by the-3- +3 edge, the middle eye is limited by the-3- +1 and the + 3- +1 edge, and the lower eye is limited by the + 3- +3 edge. The intersymbol interference generated by these edges is the largest, but the feedforward equalizer can only eliminate all the intersymbol interference according to the same proportion, so the elimination effect of these intersymbol interference is not good, and the quality of the eye pattern is seriously affected.
Disclosure of Invention
The invention aims to provide an equalizer, a driver and an equalizing method thereof based on code pattern selection, aiming at solving the problems in the prior art.
The technical scheme of the invention is as follows:
the equalizer based on code pattern selection is characterized by comprising a code pattern detection logic unit and an equalizer module, wherein the equalizer module comprises transistors M5-M8; wherein, the first and the second end of the pipe are connected with each other,
two input ends of the code pattern detection logic unit are respectively connected with an MSB signal output end and an LSB signal output end and are used for detecting whether the code pattern changes according to the input MSB signal and the LSB signal, and if the code pattern of the MSB signal received at the previous moment is '00' and the code pattern of the MSB signal received at the current moment is '11' or '10', a pull-down signal PDN is generated; if the LSB code pattern received at the previous moment is '00' and the LSB code pattern received at the current moment is '11' or '10', generating a pull-down signal PDN; if the MSB signal code pattern received at the previous moment is '11' and the MSB code pattern received at the current moment is '00' or '01', generating a pull-down signal PDP; if the LSB signal code type received at the previous moment is '11' and the LSB signal code type received at the current moment is '00' or '01', a pull-down signal PDP is generated;
the source electrode of the M5 is connected with the drain electrode of the M6, the grid electrode of the M5 is connected with the output end of the pull-down signal PDN of the code pattern detection logic unit, and the drain electrode of the M5 is connected with the output node OUTN; the source electrode of the M6 is connected with the ground wire, and the grid electrode of the M6 is connected with the output end of a control signal SEL; the source electrode of the M7 is connected with the drain electrode of the M8, the grid electrode of the M7 is connected with the pull-down signal PDP output end of the code pattern detection logic unit, and the drain electrode of the M7 is connected with the output node OUTP; the source electrode of the M8 is connected with the ground wire, and the grid electrode of the M8 is connected with the output end of a control signal SEL; the control signal SEL is used for controlling the equalization intensity based on the code pattern;
the output node OUTN is an output node connected with the negative electrode of the PAM4 driver; the output node OUTP is the output node to which the positive pole of the PAM4 driver is connected.
Furthermore, the device comprises n M6 which are connected in parallel, wherein the source electrode of the ith M6 is connected with the ground wire, the grid electrode of the ith M6 is connected with the output end of an ith control signal SEL, and the drain electrode of the ith M6 is connected with the source electrode of the M5; the ith control signal SEL is used to control the on or off of the ith M6, i =1 to n.
A driver is characterized by a PAM4 driver, a code pattern detection logic unit and an equalizer module, wherein the equalizer module comprises transistors M5-M8; wherein the content of the first and second substances,
two input ends of the code pattern detection logic unit are respectively connected with an MSB signal output end and an LSB signal output end and are used for detecting whether the code pattern changes according to the input MSB signal and the LSB signal, and if the code pattern of the MSB signal received at the previous moment is '00' and the code pattern of the MSB signal received at the current moment is changed into '11' or '10', a pull-down signal PDN is generated; if the LSB code pattern received at the previous moment is '00' and the LSB code pattern received at the current moment is '11' or '10', generating a pull-down signal PDN; if the MSB signal code pattern received at the previous moment is '11' and the MSB code pattern received at the current moment is '00' or '01', generating a pull-down signal PDP; if the LSB signal code type received at the previous moment is 11 and the LSB signal code type received at the current moment is 00 or 01, generating a pull-down signal PDP;
the source electrode of the M5 is connected with the drain electrode of the M6, the grid electrode of the M5 is connected with the PDN output end of the pull-down signal of the code pattern detection logic unit, and the drain electrode of the M5 is connected with an output node OUTN; the source electrode of the M6 is connected with the ground wire, and the grid electrode of the M6 is connected with the output end of a control signal SEL; the source electrode of the M7 is connected with the drain electrode of the M8, the grid electrode of the M7 is connected with the pull-down signal PDP output end of the code pattern detection logic unit, and the drain electrode of the M7 is connected with the output node OUTP; the source electrode of the M8 is connected with the ground wire, and the grid electrode of the M8 is connected with the output end of a control signal SEL; the control signal SEL is used for controlling the equalization intensity based on the code pattern;
the negative pole of PAM4 driver with output node OUTN connects, the positive pole of PAM4 driver with output node OUTP connects.
Further, the PAM4 driver comprises transistors M1-M4 and current sources I1 and I2; the source of M1 is connected with a current source I1, the grid of the M1 is connected with the MSB signal output end, and the drain of the M1 is connected with the output node OUTN; the source electrode of the M2 is connected with the current source I1, the grid electrode of the M2 is connected with the MSB signal inverting output end, and the drain electrode of the M2 is connected with the output node OUTP; the source electrode of the M3 is connected with the current source I2, the grid electrode of the M3 is connected with the LSB signal output end, and the drain electrode of the M3 is connected with the output node OUTN; the source of M4 is connected with the current source I2, the grid is connected with the MSB signal inverting output end, and the drain is connected with the output node OUTP.
Further, the current of the current source I1 is twice the current of the current source I2.
Further, the transistors M1 to M8 are all NMOS.
A method for equalizing a signal based on the driver, comprising the steps of: when the M5 receives a pull-down signal PDN, a pull-down branch formed by the M5 and the M6 is conducted, the falling edge of the output node OUTN is accelerated, the edge speed of the OUTN is kept unchanged, and therefore the rising of a differential output signal OUTP-OUTN is accelerated; when the M7 receives the pull-down signal PDN, the pull-down branch formed by M7 and M8 is turned on, and the falling edge of the output node OUTP is accelerated, while the edge speed of OUTP remains unchanged, so as to accelerate the falling edge of the differential output signal OUTP-OUTN.
The invention has the following advantages:
1) Different intensity equalization is carried out on different code patterns, and intersymbol interference is eliminated more pertinently;
2) Different configurations can be carried out according to the selection of the code pattern so as to adapt to different transmission scenes;
3) The scheme is compatible with the traditional equalization scheme.
Drawings
Fig. 1 is a block diagram of a transmitter data structure.
Fig. 2 is a 4.
FIG. 3 is an eye diagram with channel attenuation;
(a) No feed forward equalization and (b) feed forward equalization.
Fig. 4 is a circuit diagram of a driver incorporating the equalizer of the present invention.
Fig. 5 is a timing diagram illustrating the operation of the equalizer of the present invention.
Detailed Description
The invention will be described in further detail with reference to the following drawings, which are given by way of example only for the purpose of illustrating the invention and are not intended to limit the scope of the invention.
The driver structure of the present invention is shown in fig. 4, and the whole driver structure is composed of a PAM4 driver, a pattern detection logic unit, and an equalizer module. The PAM4 driver corresponds to fig. 1 and is a common module of a PAM4 transmitter; the equalizer selected based on the code pattern is in parallel relation with the PAM4 driver, and the output signals OUTP/OUTN are the sum of the two. The PAM4 driver receives the MSB and the LSB signal, the LSB controls a current I2 to flow through R1 or R2, and the MSB controls a double current I2 (I1 =2 × I2) to flow through R1 or R2, thereby generating a PAM4 signal; the code pattern detection logic unit receives the MSB/LSB signal, judges the jump edge by detecting the data of the current MSB/LSB and the MSB/LSB at the previous moment, if the jump edge of the principle description part is detected, one of the output signals PDP/PDN is changed into high level, otherwise, both are low level, and the PDP and the PDN are respectively connected to M7 and M5; m5-8 form an equalizer module based on code pattern selection, receive two signals of PDP and PDN, output OUTP and OUTN connected in parallel to the PAM4 driver, and generate single-ended pull-down current to change the voltage of OUTP or OUTN (only act on one at the same time) according to the control of PDP/PDN, thereby generating an equalization effect.
As shown in fig. 4, two ends of the resistor R1 are connected to the power supply and the output node OUTN, respectively, and two ends of the resistor R2 are connected to the power supply and the output node OUTP, respectively. The input of the pattern detection logic is connected to the data MSB and LSB for generating a pull-down signal PDP or PDN. The transistors M1 to M8 are all NMOS; the source electrode of the M1 is connected with the current source I1, the grid electrode of the M1 is connected with the data MSB, and the drain electrode of the M1 is connected with the output node OUTN; the source electrode of the M2 is connected with the current source I1, the grid electrode of the M2 is connected with the data MSB in an inverted mode, and the drain electrode of the M2 is connected with the output node OUTP; the source electrode of the M3 is connected with the current source I2, the grid electrode of the M3 is connected with the data LSB, and the drain electrode of the M3 is connected with the output node OUTN; the source electrode of the M4 is connected with the current source I2, the grid electrode of the M4 is connected with the inversion of the data LSB, and the drain electrode of the M4 is connected with the output node OUTP; the source electrode of the M5 is connected with the drain electrode of the M6, the grid electrode of the M5 is connected with the pull-down signal PDN, and the drain electrode of the M5 is connected with the output node OUTN; the source of M6 is connected with the ground, the grid is connected with a control signal SEL, and the drain is connected with the source of M5; the source electrode of the M7 is connected with the drain electrode of the M8, the grid electrode of the M7 is connected with the pull-down signal PDP output end, and the drain electrode of the M7 is connected with the output node OUTP;
the source of M8 is connected to ground, the gate to a control signal SEL, and the drain to the source of M7. Wherein, M6, M8 are n same units connected in parallel, each unit is provided with the same transistor, which is marked by M6, M8, and the grid of all units is connected with n bits SEL [ 1. In SEL [ 1; the ratio of the high level to the low level determines the magnitude of the pull-down current, thereby controlling the equalization strength. The value of the SEL bit number n is determined by the balance strength and the adjustment precision required by an actual system, and is not unique.
The working principle of the present invention is described as follows. Recording the corresponding relation between the MSB/LSB and the PAM4 signal output by the PM4 driver as follows: 00 for-3, 01 for-1, 10 for +1, 11 for +3. The code pattern detection logic unit detects the data code pattern of the transmitting end, when two code patterns of-3- +3, -3- +1 (corresponding to MSB/LSB 00-11, 00-10) are detected, PDN is changed into high level, M5 and M6 pull-down branches are conducted, the falling edge of OUTN node is accelerated, the edge speed of OUTP is kept unchanged, and therefore the rising edge of a differential output signal OUTP-OUTN is accelerated; when two code patterns of + 3-, -3 and + 3-, -1 (corresponding to MSB/LSB of 11-00 and 11-01) are detected, the PDP is changed into high level, the M7 and M8 pull-down branches are conducted, the falling edge of the OUTP node is accelerated, and the edge speed of OUTN is kept unchanged, so that the falling edge of the differential output signal OUTP-OUTN is accelerated; when the selected edge is not detected, PDN and PDP are both 0, and the output edge is not reinforced.
Fig. 5 is a waveform diagram illustrating the operation of the equalizer of the present invention. The MSB has data of 1,0,0,1,0,0, LSB has data of 1,1,0,1, and the corresponding output signal OUTP-OUTN has data of +3, -1, -3, +3, -3, -1 in sequence. At time t =1, a transition occurs from +3 to-1 (MSB/LSB is from 11 to 01), the PDP becomes 1, and the falling edge of the output differential signal OUTP-OUTN changes from the dotted line in the figure to the solid line in the figure through accelerated pull-down; at the time t =2, jumping from-1 to-3 (MSB/LSB from 01 to 00) occurs, the selected code pattern is not belonged to, both PDP and PDN are kept at 0, and the jumping edge of the differential output signal does not change; at time t =3, a transition occurs from-3 to +3 (MSB/LSB goes from 00 to 11), PDN becomes 1, and the rising edge of the output differential signal is strengthened from the dotted line in the figure to the solid line; at time t =4, a transition occurs from +3 to-3 (MSB/LSB from 11 to 00), the PDP becomes 1, and the falling edge of the output differential signal is emphasized from the dotted line to the solid line in the figure; at time t =5, a transition occurs from-3 to-1 (MSB/LSB from 00 to 01), not belonging to the selected pattern, both PDP and PDN remain 0, and the transition edge of the differential output signal does not change.
As can be seen from the waveform diagrams, the slopes of the dotted line transition edges at the time points t =1, 3 and 4 are the same as the slopes of the transition edges at the time points t =2 and 5, the transition amplitude of the latter is small, the signal is quickly established to a required level, but the transition amplitude of the former is large, and the transition edges occupy a large proportion of the signal time, so that the eye width is reduced; after the equalizer of the invention, the jumping edge is changed from a dotted line to a solid line, the edge speed is accelerated, and the effective time of the signal is prolonged.
It should be noted that the above example is only a subset of the present invention, and the present invention is designed in such an equalizing manner that the weakest signal position is strengthened by pattern detection, and a specific pattern detection logic can be customized according to the characteristics of a transmission channel, and can be strengthened for different patterns.
Although specific embodiments of the invention have been disclosed for purposes of illustration, and for purposes of aiding in the understanding of the contents of the invention and its implementation, those skilled in the art will appreciate that: various substitutions, changes and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (8)

1. The equalizer based on code pattern selection is characterized by comprising a code pattern detection logic unit and an equalizer module, wherein the equalizer module comprises transistors M5-M8; wherein the content of the first and second substances,
two input ends of the code pattern detection logic unit are respectively connected with an MSB signal output end and an LSB signal output end and are used for detecting whether the code pattern changes according to the input MSB signal and the LSB signal, and if the code pattern of the MSB signal received at the previous moment is '00' and the code pattern of the MSB signal received at the current moment is changed into '11' or '10', a pull-down signal PDN is generated; if the LSB code pattern received at the previous moment is '00' and the LSB code pattern received at the current moment is '11' or '10', generating a pull-down signal PDN; if the MSB signal code pattern received at the previous moment is '11' and the MSB code pattern received at the current moment is '00' or '01', generating a pull-down signal PDP; if the LSB signal code type received at the previous moment is '11' and the LSB signal code type received at the current moment is '00' or '01', a pull-down signal PDP is generated;
the source electrode of the M5 is connected with the drain electrode of the M6, the grid electrode of the M5 is connected with the output end of the pull-down signal PDN of the code pattern detection logic unit, and the drain electrode of the M5 is connected with the output node OUTN; the source electrode of the M6 is connected with the ground wire, and the grid electrode of the M6 is connected with the output end of a control signal SEL; the source electrode of the M7 is connected with the drain electrode of the M8, the grid electrode of the M7 is connected with the pull-down signal PDP output end of the code pattern detection logic unit, and the drain electrode of the M7 is connected with the output node OUTP; the source electrode of the M8 is connected with the ground wire, and the grid electrode of the M8 is connected with the output end of a control signal SEL; the control signal SEL is used for controlling the equalization intensity based on the code pattern;
the output node OUTN is an output node connected with the negative electrode of the PAM4 driver; the output node OUTP is the output node to which the positive pole of the PAM4 driver is connected.
2. The equalizer according to claim 1, comprising n M6 connected in parallel, wherein the source of the ith M6 is connected to ground, the gate is connected to the ith control signal SEL output terminal, and the drain is connected to the source of M5; the ith control signal SEL is used to control the on/off of the ith M6, and i =1 to n.
3. A driver is characterized by a PAM4 driver, a code pattern detection logic unit and an equalizer module, wherein the equalizer module comprises transistors M5-M8; wherein the content of the first and second substances,
two input ends of the code pattern detection logic unit are respectively connected with an MSB signal output end and an LSB signal output end and are used for detecting whether the code pattern changes according to the input MSB signal and the LSB signal, and if the code pattern of the MSB signal received at the previous moment is '00' and the code pattern of the MSB signal received at the current moment is changed into '11' or '10', a pull-down signal PDN is generated; if the LSB code pattern received at the previous moment is '00' and the LSB code pattern received at the current moment is '11' or '10', generating a pull-down signal PDN; if the MSB signal code pattern received at the previous moment is '11' and the MSB code pattern received at the current moment is '00' or '01', generating a pull-down signal PDP; if the LSB signal code type received at the previous moment is '11' and the LSB signal code type received at the current moment is '00' or '01', a pull-down signal PDP is generated;
the source electrode of the M5 is connected with the drain electrode of the M6, the grid electrode of the M5 is connected with the output end of the pull-down signal PDN of the code pattern detection logic unit, and the drain electrode of the M5 is connected with the output node OUTN; the source electrode of the M6 is connected with the ground wire, and the grid electrode of the M6 is connected with the output end of a control signal SEL; the source electrode of the M7 is connected with the drain electrode of the M8, the grid electrode of the M7 is connected with the pull-down signal PDP output end of the code pattern detection logic unit, and the drain electrode of the M7 is connected with the output node OUTP; the source electrode of the M8 is connected with the ground wire, and the grid electrode of the M8 is connected with the output end of a control signal SEL; the control signal SEL is used for controlling the equalization strength based on the code pattern;
the negative pole of PAM4 driver with output node OUTN connects, the positive pole of PAM4 driver with output node OUTP connects.
4. The driver according to claim 3, comprising n M6 in parallel, wherein the source of the ith M6 is connected to ground, the gate is connected to the ith control signal SEL output terminal, and the drain is connected to the source of M5; the ith control signal SEL is used to control the on or off of the ith M6, i =1 to n.
5. The driver of claim 3 or 4, wherein the PAM4 driver comprises transistors M1-M4 and current sources I1, I2; the source electrode of the M1 is connected with the current source I1, the grid electrode of the M1 is connected with the MSB signal output end, and the drain electrode of the M1 is connected with the output node OUTN; the source electrode of the M2 is connected with the current source I1, the grid electrode of the M2 is connected with the MSB signal inverting output end, and the drain electrode of the M2 is connected with the output node OUTP; the source electrode of the M3 is connected with the current source I2, the grid electrode of the M3 is connected with the LSB signal output end, and the drain electrode of the M3 is connected with the output node OUTN; the source electrode of the M4 is connected with the current source I2, the grid electrode of the M4 is connected with the MSB signal inverting output end, and the drain electrode of the M4 is connected with the output node OUTP.
6. The driver of claim 5, wherein the current of the current source I1 is twice the current of the current source I2.
7. The driver of claim 5, wherein the transistors M1-M8 are all NMOS.
8. A signal equalization method based on the driver of claim 3, comprising the steps of: when the M5 receives the pull-down signal PDN, the pull-down branch formed by the M5 and the M6 is turned on, and the falling edge of the output node OUTN is accelerated, while the edge speed of OUTN remains unchanged, so as to accelerate the rising of the differential output signal OUTP-OUTN; when the M7 receives the pull-down signal PDN, the pull-down branch formed by M7 and M8 is turned on, and the falling edge of the output node OUTP is accelerated, while the edge speed of OUTP remains unchanged, so as to accelerate the falling edge of the differential output signal OUTP-OUTN.
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