CN1151419C

CN1151419C - Resetting method of CPU system containing field programmable gate array

Info

Publication number: CN1151419C
Application number: CNB001195506A
Authority: CN
Inventors: 蔡永明; 曹烨
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2000-07-29
Filing date: 2000-07-29
Publication date: 2004-05-26
Anticipated expiration: 2020-07-29
Also published as: CN1321922A

Abstract

The present invention discloses a method for resetting a CPU system containing a field programmable gate array, which relates to a reset method of a digital communication system. The method of the present invention comprises the following steps: firstly, after the system is powered on, the programming content is downloaded by FPGA; then, after the FPGA download is completed, a CPU starts resetting in a controlled model; after the CPU reset is completed, the CPU judges whether all ICs are completely reset or not; if false, the CPU continues resetting other ICs in the FPGA and the system until all the ICs are completely reset; after all the ICs are fully reset, all the ICs are removed from the reset state, and the whole system normally operates. The method enhances system reliability.

Description

The cpu system repositioning method that contains field programmable gate array

The present invention relates to a kind of repositioning method of digital communication system, being specifically related to CPU is the system reset method that contains on-site programmable gate array FPGA (Field-programmable GateArray) device of core.

Concerning general cpu system, the usually no specific (special) requirements that resets, the flow process of this repositioning method as shown in Figure 1, common practices is that other integrated circuit (IC) (Integrate Circuit) in the reset signal of CPU and the circuit is directly linked to each other, in cpu reset, reset in the lump other IC.The benefit of this way is to have simplified circuit, has shortened the system reset time, but has also brought weak point: in case that certain IC device work has occurred is undesired, CPU can not make its operate as normal again by this device is resetted separately; Also must satisfy a precondition in addition: the reset time that puts on system must be all longer than the reset time of reset time of CPU or other IC device, total system ability operate as normal, any one IC, especially CPU fully do not reset all unpredictable consequence may occur.

In the digital communication field, system is more complicated all generally, except that CPU, use on-site programmable gate array FPGA and other IC device toward contact.Because the FPGA device tends to be comprised in the minimum system of CPU, if the work of FPGA device is undesired, unpredictable consequence will appear in the system of CPU and control thereof.Therefore, when total system powers on, require FPGA from programmable read only memory PROM (Programmable Read-onlyMemory), to download earlier, require CPU in its downloading process, to remain reset mode simultaneously; After the FPGA download finished, CPU worked through the back that fully resets, and then by CPU the register among the FPGA is provided with initial value, and some application-specific integrated circuit also requires to reset under CPU control or download at last.Each device of system just has strict demand to the order of electrification reset like this, adopts original method that total system is resetted together just to be difficult to the requirement of compliance with system, therefore need do a complete consideration again to the repositioning method of total system.

The purpose of this method is exactly the defective that overcomes the conventional reset method, and the conventional reset method is improved, and provides a kind of simple and reliable method to come the cpu system that contains FPGA is carried out effective electrification reset sequential control, thus the normal operation of the system of assurance.

The key that realizes the object of the invention is to make full use of FPGA can pass through device itself after its program download finishes external pin generation level skip signal from low to high, just can learn that by monitoring this signal FPGA downloads the correct time that finishes, and then remove to control the chip that resets of CPU with this signal, allow CPU begin that resetting of control arranged, so just avoided the uncertainty of FPGA reset time.After the normal operation of CPU, just can control the resetting of FPGA and other IC device, download etc. by the I/O mouth of CPU.

System reset method of the present invention can reduce following steps:

A) after system powers on, download its programming content by FPGA;

B) after wait FPGA downloaded and finishes, CPU began that just resetting of control arranged;

C) after cpu reset finishes, other IC in FPGA and the system is resetted by CPU;

D) judging by CPU whether all IC reset finishes;

E) if do not resetted, repeating step c then), reset until all IC and finish;

F) after all IC all fully reset, break away from reset mode, total system is normally moved.

The cpu system repositioning method that contains FPGA that the present invention proposes, can learn that by the level skip signal FPGA downloads the correct time that finishes, and then remove to control the chip that resets of CPU with this signal, and allow CPU begin that resetting of control arranged, avoided the uncertainty of FPGA reset time.After the normal operation of CPU, just can control the resetting of FPGA and other IC device, download etc. by the I/O mouth of CPU, so just overcome the weak point in the conventional reset method, improved the reliability of system.

Below in conjunction with drawings and Examples, further specify technical scheme of the present invention.

Fig. 1 is a kind of process flow diagram of system reset method commonly used;

Fig. 2 is the process flow diagram of system reset method of the present invention;

Fig. 3 is a system architecture diagram involved in the present invention.

In Fig. 3, be that the FPGA of EPF10K30E is an example with the model of ALTERA company, FPGA download state level output pin is remembered as INIT_D in EPF10K30E.This pin keeps low level in downloading process, finish in case download, and jumps to high level immediately; This pin is received the voltage monitoring end of the chip that resets, and the reset output terminal of the chip that resets connects the input that resets of CPU.Can appoint the I/O mouth of getting CPU, get and this I/O mouth is defined as output pin after fixed, receive the RESET input of FPGA and other IC chip.

Specify the process of utilizing the inventive method to carry out system reset in conjunction with Fig. 2 again:

At first, in step 201, after system powers on, download its programming content by FPGA earlier.This moment, the INIT_D pin was a low level, and it is low that the chip that resets detects voltage, and just output low level always makes CPU and other IC device be in reset mode;

Step 202, after FPGA downloads, CPU begins that just resetting of control arranged, and this moment, INIT_D became high level, after the chip that resets detects, start reseting procedure, can continue this moment to keep being output as low level a period of time so that CPU during this period of time can fully reset, during this period of time after, output becomes high level, and CPU stops to reset;

Step 203, CPU begins to carry out the initialization of self, and with its I/O mouth zero clearing (or set), CPU carries out reset operation to register and other IC of the FPGA inside in the system simultaneously;

Whether step 204 is judged by CPU that all IC reset and is finished; If do not finish, then repeating step 203, and resetting until all IC finishes; Finish in case reset, then with this I/O mouth set (or zero clearing);

Step 205, so far resetting of total system finished.

According to the actual needs of system, can also add corresponding hand-reset and watchdog reset.In case program fleet then forces total system to carry out above-mentioned reseting procedure again by hand-reset and these two kinds of methods of watchdog reset.Now many chips that reset are all entered above-mentioned functions is integrated, only need a CPU provide an I/O mouth regularly to remove the clear terminal of house dog clearly, externally connect a touch-switch simultaneously and get final product.

Claims

1, a kind of cpu system repositioning method that contains field programmable gate array is characterized in that may further comprise the steps:

A) after system powers on, download its programming content (201) by FPGA;

B) after wait FPGA downloaded and finishes, CPU just began to have reset (202) of control;

C) after cpu reset finishes, by CPU to other IC in FPGA and the system reset (203);

D) judge all IC finish (204) that whether reset by CPU;

E) if do not have, repeating step c then) (203), resetting until all IC finishes;

F) after all IC all fully reset, break away from reset mode, total system is normally moved (205).

2, a kind of cpu system repositioning method that contains field programmable gate array as claimed in claim 1 is characterized in that it is to learn by the level skip signal from low to high that monitoring FPGA is produced that described FPGA downloads the correct time that finishes after its program download finishes.