CN1308789C

CN1308789C - Reset method

Info

Publication number: CN1308789C
Application number: CNB021107629A
Authority: CN
Inventors: 李鹏; 马建军
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2002-01-29
Filing date: 2002-01-29
Publication date: 2007-04-04
Anticipated expiration: 2022-01-29
Also published as: CN1435743A

Abstract

The present invention provides a reset method, and relates to the reset realization of a control system. The present invention carries out frequency division on an oscillation signal of a central processing unit (CPU), and the signal with the frequency division is used as an input count pulse of a counter. During work, the CPU pays a call on a programmable device within the certain time. If the CPU pays a call on a programmable logic device, the counter clears to zero, and the counter recounts. If the CPU does not pay a call on the programmable logic device, the programmable device generates a reset signal, and the procedures are circulated and repeated. The pulse width (Tms is radix) of the reset signal is adjustable through changing the counting number of the counter. When the power of the present invention is supplied, the pulse signal with frequency division is used as a counting signal of the counter. After the set counting finishes, a power supply reset signal is output. The present invention can distinguish the power supply reset signal and a watchdog reset signal, the dog feeding time of the watchdog can be optionally adjusted, the idle programmable logic device can be fully utilized, and the hardware resources of the system can be furthest applied.

Description

A kind of repositioning method

Technical field

The present invention relates to the implementation method that communication, electron trade, Based Intelligent Control dispatch control system reset, be specifically related to a kind of method of utilizing programmable logic device (PLD) to realize system reset.

Background technology

Reset circuit is an electron trade intelligence system (MPU) at the circuit that powers on and the deadlock state must reset to CPU or other chips, and this circuit is the basic circuit of intelligence control system indispensability.Present most of digital intelligent control system all adopts traditional special use chip that resets; The general intelligence control system " deadlock " phenomenon may occur when normal operation, in this case, reset circuit must reset to system CPU or other parts control chip, but traditional chip that resets can't be distinguished electrification reset and " deadlocks " phenomenon that resets, so just can't solve different reset signals is provided under this two states; Secondly traditional special use chip that resets can't be accomplished adjustablely arbitrarily to the dog time of feeding of " house dog ", generally is to immobilize or several selectable time; And traditional special use chip that resets can't satisfy different reset levels and the adjustable problem of reset level pulsewidth are arranged on the same chip.Generally all use programmable logic device (PLD) in the large-scale intelligent control system at present, and all do not utilize the resource in the programmable logic device (PLD) fully, cause the wasting of resources to a certain degree.

Summary of the invention

Technical matters to be solved by this invention is that to make full use of the resource of programming device more single to overcome the reset signal that special-purpose reset coil sheet exists in the prior art, can't realize electrification reset and " deadlocks " resetted and distinguish and shortcoming that, reset level pulsewidth can't be any adjustable to " house dog " hello dog time can't be adjustable.

The present invention proposes a kind of repositioning method based on programmable logic device (PLD), its core concept is to utilize controller external clock or internal clocking as the clock that clocks, do not visit programmable logic device (PLD) in the official hour internal controller and just produce reset signal, the specific implementation method is as follows:

At first get the CPU oscillator signal and carry out frequency division, the signal behind the frequency division is the pulse signal of certain frequency (f), and the cycle of pulse signal is T, the input count pulse of this pulse signal as counter;

When work, in the regular hour, if CPU conducts interviews to programmable logic device (PLD), counter O reset, counting again; If when CPU did not conduct interviews to programmable logic device (PLD), programmable logic device (PLD) just produced reset signal; Make this reset signal pulse width adjustable (Tms is a radix) by the counting number that changes counter;

When powering on, utilize pulse signal behind the frequency division as the rolling counters forward signal, finish to finish the back and export a power-on reset signal setting counting.This signal does not influence the output reset signal of " house dog ", thereby guarantees that power-on reset signal separates fully with " house dog " reset signal.

Adopt the method for the invention, can distinguish power-on reset signal and " house dog " reset signal; " feeding dog " any scalable of time of feasible " house dog ", and made full use of idle programmable logic device (PLD), the hardware resource of system is farthest used.For the cpu reset of digital intelligent control system and " house dog " circuit provide new approaches, can reduce cost for system.

Description of drawings

Fig. 1 is a synoptic diagram of realizing the method for the invention.

Fig. 2 the present invention is based on reset circuit that EPLD realizes to be applied in part schematic diagram in the side circuit.

Fig. 3 is the reset circuit part among Fig. 2.

Embodiment

The present invention is described further below in conjunction with the drawings and specific embodiments.

Fig. 1 utilizes the programmable logic device (PLD) hardware description language to realize the control chart of the method for the invention.As shown in Figure 1: get the system oscillation signal, carry out frequency division by frequency divider then, the signal of frequency divider frequency division (adjustable) is system's reference signal, this reference signal is counted to counting, by count signal setting " house dog " time is set, when rolling counters forward finishes (when counting down to), if system not to chip conduct interviews (not having chip selection signal) just produce " house dog " (i.e. " deadlock " reset) signal that resets.If when rolling counters forward, system conducts interviews to this chip (programmable logic device (PLD)), and counter O reset is counted again; Cycle count like this;

When system powered on, counter was counted the count value of setting (adjustable), produced power-on reset signal when rolling counters forward finishes.This reset signal pulse can be adjustable by counter;

As seen, power-on reset signal and " house dog " reset signal are separated fully, can realize reset signal separately by programming so, and reset level is adjustable, and reset pulse is adjustable.

Fig. 2 the present invention is based on reset circuit that EPLD (programmable logic device (PLD)) realized to be applied in part schematic diagram in the side circuit.

Table 1 is the signal definition explanation of the main pin of part.

Pin	Signal name	Signal definition	Remarks
Pin	Signal name	Signal definition	Remarks	55	WDT_CS	Chip selection signal	Low level is effective
56	Rst	The electrification reset output signal (can be used separately, only produce reset level at powered on moment, the width of level can be regulated as required)	The output of electrification reset high level	55	WDT_CS	Chip selection signal	Low level is effective
56	Rst		The output of electrification reset high level	57	Set	The hand-reset input signal	High level is effective
12	Reset	Reset signal (goes up electric and manual, house dog (the house dog time can be adjusted arbitrarily as required)	Produce high level when resetting	57	Set	The hand-reset input signal	High level is effective
12	Reset		Produce high level when resetting	54	Clk11m	Clock input (timing signal)	Link to each other with crystal oscillator, crystal oscillator frequency is pressed the 11.0592MHz design during program design

The specific implementation method is as follows:

1. get CPU oscillator 11.0592MHz and be input to 54 pin (CLK11M) of EPLD, after EPLD handles, produce the 100HZ pulse signal as fractional frequency signal.

2.CPU 7 pin (WDT_CS) link to each other with 55 pin of EPLD, chip selection signal as programmable logic device (PLD) (EPLD), when the CPU working procedure, constantly EPLD is conducted interviews, this signal (WDT_CS) is a pulse signal so, and EPLD detects signal always, just counter is carried out zero clearing when visiting EPLD at every turn, if (can regulate easily in regulation, in this embodiment for 1.6S) time in this signal keep high level always, just produce a reset signal, CPU is reruned.

3. when powering on, oscillator will produce oscillator signal, the counter of this signal after EPLD handles also begins counting so, just produces a power-on reset signal (level of signal and pulse width can be regulated by the logical diagram of revising EPLD) when the counting down to of regulation.

Fig. 3 is the schematic diagram that utilizes the compiling of VHDL (very high speed integrated circuit hardware descriptionlanguage) language to produce based on EPLD (programmable logic device (PLD)) in the example shown in Figure 2.This part schematic diagram only is about the reset circuit part, with other irrelevant part schematic diagrams omissions of this method in the application example.

In sum, this method makes full use of limited resources, has solved the problem that present special-purpose reset circuit can't be realized, provides application flexibility to the user, and has reduced device cost, has improved the competitive power in market.

Claims

1, a kind of repositioning method is at first got the CPU oscillator signal and is carried out frequency division, and the signal behind the frequency division is that certain frequency is the pulse signal of f, the input count pulse of this pulse signal as counter;

During work, in the regular hour, if CPU conducts interviews to programmable logic device (PLD), counter O reset, counting again; If when CPU did not conduct interviews to programmable logic device (PLD), programmable logic device (PLD) just produced reset signal; Make that by the counting number that changes counter this reset signal pulse width is adjustable, the T millisecond is a radix;

When powering on, utilize pulse signal behind the frequency division as the rolling counters forward signal, finish to finish the back and export a power-on reset signal setting counting.