CN115104259A - 一种集成电路、控制方法及*** - Google Patents
一种集成电路、控制方法及*** Download PDFInfo
- Publication number
- CN115104259A CN115104259A CN202080096598.2A CN202080096598A CN115104259A CN 115104259 A CN115104259 A CN 115104259A CN 202080096598 A CN202080096598 A CN 202080096598A CN 115104259 A CN115104259 A CN 115104259A
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- CN
- China
- Prior art keywords
- pull
- switch
- resistor
- integrated circuit
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018557—Coupling arrangements; Impedance matching circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
一种集成电路、控制方法及***,用以提高集成电路的可靠性。其中,集成电路主要包括电源管脚(P1)、配置管脚(P4,P5)、上拉开关电阻(KR1,KR2)和控制单元(2011),该集成电路能够通过其配置管脚(P4,P5)为目标芯片(202)提供控制信号。在集成电路中,上拉开关电阻(KR1,KR2)的第一端与电源管脚(P1)连接,上拉开关电阻(KR1,KR2)的第二端与配置管脚(P4,P5)连接,上拉开关电阻(KR1,KR2)的控制端与控制单元(2011)连接;电源管脚(P1)可以接收集成电路的供电电压;控制单元(2011)可以在目标芯片(202)上电之前,控制上拉开关电阻(KR1,KR2)处于断开状态。有利于防止目标芯片(202)在上电之前从集成电路的配置管脚(P4,P5)接收到误差信号,从而有利于提高集成电路的可靠性。此外,还有利于简化集成电路的***电路的结构。
Description
PCT国内申请,说明书已公开。
Claims (17)
- PCT国内申请,权利要求书已公开。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2020/075421 WO2021159526A1 (zh) | 2020-02-14 | 2020-02-14 | 一种集成电路、控制方法及*** |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115104259A true CN115104259A (zh) | 2022-09-23 |
Family
ID=77292952
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202080096598.2A Pending CN115104259A (zh) | 2020-02-14 | 2020-02-14 | 一种集成电路、控制方法及*** |
Country Status (4)
Country | Link |
---|---|
US (1) | US11855616B2 (zh) |
EP (1) | EP4099566A4 (zh) |
CN (1) | CN115104259A (zh) |
WO (1) | WO2021159526A1 (zh) |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100729916B1 (ko) * | 2004-04-08 | 2007-06-18 | 주식회사 하이닉스반도체 | 온 다이 터미네이션 회로 |
JP4337711B2 (ja) * | 2004-11-17 | 2009-09-30 | 株式会社デンソー | 半導体素子制御装置 |
US7921231B2 (en) * | 2008-01-04 | 2011-04-05 | Silicon Image, Inc. | Discovery of electronic devices utilizing a control bus |
DE102009052947B3 (de) * | 2009-11-12 | 2010-12-16 | Sinitec Vertriebsgesellschaft Mbh | Energiesparschaltung für ein Peripheriegerät, Peripheriegerät, Vermittlungsgerät und Arbeitsverfahren |
JP5671269B2 (ja) * | 2010-06-24 | 2015-02-18 | ラピスセミコンダクタ株式会社 | バス接続回路を備えた半導体装置及びそのバス接続方法 |
CN103545784B (zh) * | 2012-07-12 | 2017-04-12 | 上海电科电器科技有限公司 | 控制与保护开关电器的脉冲控制器 |
KR102226370B1 (ko) * | 2015-01-13 | 2021-03-15 | 삼성전자주식회사 | 집적 회로 및 집적 회로를 포함하는 스토리지 장치 |
US10139894B2 (en) * | 2016-04-01 | 2018-11-27 | Platina Systems Corp. | Heterogeneous network in a modular chassis |
US10289589B2 (en) * | 2016-08-31 | 2019-05-14 | Intel Corporation | Apparatuses to resolve roles for dual role serial bus devices |
CN206251066U (zh) * | 2016-12-13 | 2017-06-13 | 深圳Tcl数字技术有限公司 | 芯片复位电路及电子设备 |
US10141045B2 (en) * | 2016-12-15 | 2018-11-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual rail device with power detector for controlling power to first and second power domains |
CN106787031B (zh) * | 2017-03-28 | 2019-03-29 | 湖南科技大学 | 一种串联电池组快平衡充电装置 |
CN106685023B (zh) * | 2017-03-28 | 2019-03-29 | 湖南科技大学 | 仪器内部供电串联电池组的平衡管理模块 |
US10637462B1 (en) * | 2019-05-30 | 2020-04-28 | Xilinx, Inc. | System and method for SoC power-up sequencing |
TWI715498B (zh) * | 2020-05-19 | 2021-01-01 | 瑞昱半導體股份有限公司 | 連接埠控制裝置 |
-
2020
- 2020-02-14 CN CN202080096598.2A patent/CN115104259A/zh active Pending
- 2020-02-14 WO PCT/CN2020/075421 patent/WO2021159526A1/zh unknown
- 2020-02-14 EP EP20918402.7A patent/EP4099566A4/en active Pending
-
2022
- 2022-08-12 US US17/887,176 patent/US11855616B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20220393677A1 (en) | 2022-12-08 |
US11855616B2 (en) | 2023-12-26 |
EP4099566A4 (en) | 2023-01-25 |
WO2021159526A1 (zh) | 2021-08-19 |
EP4099566A1 (en) | 2022-12-07 |
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