CN115084245A - LDMOS device, preparation method thereof and chip - Google Patents

LDMOS device, preparation method thereof and chip Download PDF

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Publication number
CN115084245A
CN115084245A CN202210875450.XA CN202210875450A CN115084245A CN 115084245 A CN115084245 A CN 115084245A CN 202210875450 A CN202210875450 A CN 202210875450A CN 115084245 A CN115084245 A CN 115084245A
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dielectric layer
region
silicon dioxide
drift region
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CN115084245B (en
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赵东艳
王于波
郁文
陈燕宁
刘芳
付振
余山
邓永峰
吴波
王帅鹏
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides an LDMOS device, a preparation method thereof and a chip, and belongs to the technical field of semiconductor integrated circuits. The method comprises the following steps: the gate structure comprises an electrode layer and a gate dielectric layer, and the gate dielectric layer consists of a plurality of silicon dioxide layers and a plurality of high-K dielectric layers; a silicon dioxide layer and a high-K dielectric layer adjacent to the silicon dioxide layer are adjacently arranged above the body region and the drift region; and a plurality of silicon dioxide layers and a plurality of high-K dielectric layers which are alternately stacked are also arranged on the high-K dielectric layer above the drift region. The gate dielectric layer above the body region is of a double-layer structure, the conductive channel formed in the body region is not affected, and the gate dielectric layer above the drift region is of a stacked structure, so that the voltage resistance of the device is effectively improved. The silicon dioxide layer inserted between the high-K dielectric layers can block the influence of high-K dielectric dipole conduction on a channel and reduce the influence of a carrier phonon scattering phenomenon on the speed of the device.

Description

LDMOS device, preparation method thereof and chip
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to an LDMOS device, a preparation method of the LDMOS device and a chip.
Background
With the development of the times, the application fields of semiconductors have also been expanded from traditional industrial control, communication, computers, consumer electronics to new fields such as new energy, smart grid, rail transit, automotive electronics, and the like. The power semiconductor device pursues the handling of electric energy, and is required to have high withstand voltage and large current characteristics itself. As a Lateral power device, an LDMOS (Lateral Double-Diffused MOSFET) has the advantages of high withstand voltage, large gain, good linearity, high efficiency, good broadband matching performance, and the like, and is widely applied to power integrated circuits, especially low-power and high-frequency circuits.
What is more important is that the quality of the LDMOS structure design and the reliability of the operation of the LDMOS determine the performance of the whole power integrated circuit. Therefore, it is necessary to ensure the electrical characteristics and reliability of the device and ensure the stability and reliability of the industrial-scale application of the device through the optimized design and process improvement of the device.
The traditional device adopts polysilicon as a gate electrode, and in order to prevent gate oxide breakdown and active region breakdown of the device, a shallow trench isolation region or a local oxidation of silicon (LOCOS) isolation region or oxide isolation for reducing a surface electric field is required to be arranged between the gate electrode and a drift region, so that a conductive path is prolonged, a characteristic on-resistance is increased, the area of the device is occupied, and the high performance and small size design of the LDMOS device cannot be realized.
On the other hand, the high-K value of the high-K dielectric material is beneficial to an internal dipole structure, but the dipole near the lower surface of the gate dielectric layer can vibrate and is transmitted to silicon atoms of a channel, so that lattice vibration is caused, carrier phonon scattering is formed, and the speed of the device is reduced.
Disclosure of Invention
The LDMOS device and the preparation method and the chip thereof are provided, the gate dielectrics alternately stacked in multiple layers are adopted, the high-K dielectric layers can improve the speed of the device due to the characteristics of the high-K dielectric layers, and the silicon dioxide layer inserted between the high-K dielectric layers can block the influence of dipole conduction of the high-K dielectric on a channel, reduce the influence of a carrier phonon scattering phenomenon on the speed of the device and improve the speed of the device; and the multilayer films are arranged at intervals, so that the interlayer stress can be relieved, and the problem of GOI reliability caused by interlayer point defects and surface defects is reduced.
In order to achieve the above object, a first aspect of the present invention provides an LDMOS device comprising: the semiconductor device comprises a semiconductor substrate, a gate structure, a source region, a drain region, a body region and a drift region, wherein the body region and the drift region are formed in the semiconductor substrate; the grid structure is arranged above the semiconductor substrate, one end of the grid structure is positioned above the body region, and the other end of the grid structure is positioned above the drift region; the source region is formed in the body region and is positioned on one side of the gate structure; the drain region is formed in the drift region and positioned at the other side of the gate structure; the grid structure comprises an electrode layer and a grid dielectric layer, wherein the grid dielectric layer is composed of a plurality of silicon dioxide layers and a plurality of high-K dielectric layers; a silicon dioxide layer and a high-K dielectric layer adjacent to the silicon dioxide layer are adjacently arranged above the body region and the drift region; and a plurality of silicon dioxide layers and a plurality of high-K dielectric layers which are alternately stacked are also arranged on the high-K dielectric layer above the drift region. The gate dielectric layer above the body region is of a double-layer structure, the conductive channel formed in the body region is not affected, and the gate dielectric layer above the drift region is of a stacked structure, so that the voltage resistance of the device is effectively improved. The interface state can be reduced by the contact of the silicon dioxide layer with the semiconductor substrate.
Optionally, the high-K dielectric layer is a high-K metal oxide layer.
Optionally, the top layer of the gate dielectric layer above the drift region is a silicon dioxide layer, and the electrode layer is a polysilicon electrode layer. When the top layer of the stacked gate dielectric layer is a silicon dioxide layer, the matching degree and compatibility of the gate dielectric layer and the electrode layer can be effectively improved by adopting the polysilicon electrode layer, and the interface characteristic is better.
Optionally, the top layer of the gate dielectric layer above the drift region is a high-K dielectric layer, and the electrode layer is a metal electrode layer made of a metal having the same metal element as the high-K metal oxide layer. When the uppermost time of the stacked gate dielectric layers is the high-K dielectric layer, the matching degree and compatibility of the gate dielectric layers and the electrode layers can be effectively improved by adopting the metal electrode layers, and the interface characteristics are better.
The invention provides a method for preparing an LDMOS device, which is used for preparing the LDMOS device and comprises the following steps:
s1: forming a drift region and a body region in the semiconductor substrate by adopting an ion implantation process;
s2: preparing a gate dielectric layer above the semiconductor substrate, wherein the gate dielectric layer is composed of a plurality of silicon dioxide layers and a plurality of high-K dielectric layers; a silicon dioxide layer and a high-K dielectric layer adjacent to the silicon dioxide layer are adjacently arranged above the body region and the drift region; the high-K dielectric layer above the drift region is also provided with a plurality of alternately stacked silicon dioxide layers and a plurality of high-K dielectric layers;
s3: growing an electrode material, and photoetching and etching to define an electrode layer;
s4: and forming a drain region in the drift region and a source region in the body region by adopting an ion implantation process. The preparation method can be effectively compatible with the existing method, and the process is simple.
Optionally, the high-K dielectric layer is a high-K metal oxide layer.
Further, the preparing a gate dielectric layer above the semiconductor substrate includes:
s201: growing a silicon dioxide material on the surface of the semiconductor substrate to form a silicon dioxide layer;
s202: preparing a high-K dielectric layer above the silicon dioxide layer;
s203: defining a graph of the gate dielectric layer above the drift region by adopting a photoetching process;
s204: and forming a plurality of silicon dioxide layers and a plurality of high-K dielectric layers which are alternately stacked on the pattern of the defined gate dielectric layer by adopting an ALD process.
Optionally, the top layer of the gate dielectric layer above the drift region is a silicon dioxide layer, and the electrode material in step S3 is a polysilicon material. When the top layer of the stacked gate dielectric layer is a silicon dioxide layer, the electrode layer is made of a polycrystalline silicon material, so that the matching degree and compatibility of the gate dielectric layer and the electrode layer can be effectively improved, and the interface characteristic is better.
Optionally, the top layer of the gate dielectric layer above the drift region is a high-K dielectric layer, and the electrode material in step S3 is made of a metal material that is the same as the metal element of the high-K metal oxide layer. When the top layer of the stacked gate dielectric layers is a high-K dielectric layer, the electrode layer is made of metal materials, so that the matching degree and compatibility of the gate dielectric layers and the electrode layer can be effectively improved, and the stacked gate dielectric layers have better interface characteristics.
Further, the forming a drift region and a body region inside the semiconductor substrate by using an ion implantation process includes:
photoetching and defining a region corresponding to the drift region above the semiconductor substrate, and injecting ions by adopting an ion injection process to form the drift region;
photoetching and defining a region corresponding to the body region above the semiconductor substrate, and implanting ions by adopting an ion implantation process to form the body region;
and annealing the semiconductor substrate on which the drift region and the body region are formed. And the drift region and the body region are simultaneously annealed, so that the process flow is saved.
Further, the metal material is grown by a sputtering process.
A third aspect of the invention provides a chip, which employs the LDMOS device as described above. By adopting the LDMOS device, the size of a chip can be reduced, and the speed of the chip is improved.
By the technical scheme, the LDMOS device is provided, an isolation structure between the drain electrode and the drift region is removed, a conductive path is shortened, and the on-resistance is reduced; meanwhile, the high-K dielectric layers and the substrate are connected by the silicon dioxide layers, so that the interface state can be reduced, the gate dielectrics alternately stacked in multiple layers are adopted, the high-K dielectric layers can improve the speed of the device due to the characteristics of the high-K dielectric layers, the silicon dioxide layers inserted between the high-K dielectric layers can block the influence of dipole conduction of the high-K dielectric on the channel, the influence of carrier phonon scattering phenomena on the speed of the device is reduced, and the speed of the device is improved; and the multilayer films are arranged at intervals, so that the interlayer stress can be relieved, and the problem of GOI reliability caused by interlayer point defects and surface defects is reduced.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a schematic structural diagram of an LDMOS device provided in a first embodiment of the invention;
FIG. 2 is a flow chart of a method for manufacturing an LDMOS device according to a first embodiment of the invention;
fig. 3 is a schematic structural diagram of an LDMOS device provided in a second embodiment of the invention.
Description of the reference numerals
The structure comprises a 1-semiconductor substrate, a 2-body region, a 3-drift region, a 4-drain region, a 5-source region, a 6-gate structure, a 61-electrode layer, a 62-gate dielectric layer, a 621-silicon dioxide layer and a 622-high-K dielectric layer.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
In this application, unless stated to the contrary, use of the directional terms such as "upper, lower, left, right" generally refer to the orientation or positional relationship shown in the drawings, or the orientation or positional relationship that the product is conventionally placed in use.
The terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The terms "horizontal", "vertical", "overhang" and the like do not imply that the components are required to be absolutely horizontal, vertical or overhang, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present application, it is also to be noted that the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited.
Example one
Fig. 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention. As shown in fig. 1, the LDMOS device includes: the semiconductor device comprises a semiconductor substrate 1, a gate structure 6, a source region 5, a drain region 4, a body region 2 and a drift region 3; the body region 2 and the drift region 3 are formed in the semiconductor substrate 1; the gate structure 6 is arranged above the semiconductor substrate 1, and one end of the gate structure 6 is positioned above the body region 2, and the other end of the gate structure 6 is positioned above the drift region 3; the source region 5 is formed in the body region 2 and is positioned at one side of the gate structure 6; the drain region 4 is formed in the drift region 3 and located at the other side of the gate structure 6; the gate structure 6 comprises an electrode layer 61 and a gate dielectric layer 62, wherein the gate dielectric layer 62 is composed of a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622; a silicon dioxide layer 621 and a high-K dielectric layer 622 adjacent to the silicon dioxide layer 621 are adjacently arranged above the body region 2 and the drift region 3; a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622 which are alternately stacked are further disposed on the high-K dielectric layer 622 above the drift region 3. The gate dielectric layer 62 above the body region 2 is of a double-layer structure, so that the formation of a conducting channel on the body region 2 is not influenced, and the gate dielectric layer 62 above the drift region 3 is of a stacked structure, so that the voltage resistance of the device is effectively improved. The interface state can be reduced by the contact of the silicon dioxide layer 621 with the semiconductor substrate 1.
In an embodiment, the high-K dielectric layer 622 is a high-K metal oxide layer. For example: al (Al) 2 O 3 、HfO 2 、ZrO 2 And the like.
The high-K metal oxide has a wider forbidden band width and good temperature stability, and the high-K metal oxide layer can improve the temperature stability of the device under extremely cold and extremely hot conditions, so that the industrial application with the service life of 20 years is realized; the high-K metal oxide layer has less dielectric defects and good insulating property, is favorable for improving the reliability of the device, and is similar to the traditional SiO 2 Compared with a dielectric layer, the high-K metal oxide layer is more compact in film formation, less in defect state and better in temperature stability.
In this embodiment, the top layer of the gate dielectric layer 62 above the drift region 3 is a silicon dioxide layer 621, and the electrode layer 61 is a polysilicon electrode layer. When the top layer of the stacked gate dielectric layer 62 is the silicon dioxide layer 621, the matching degree and compatibility between the gate dielectric layer 62 and the electrode layer 61 can be effectively improved by using the polysilicon electrode layer, and the interface characteristic is better.
Fig. 2 is a method for manufacturing an LDMOS device according to an embodiment of the present invention, where the method is used to manufacture the LDMOS device according to the first embodiment, and as shown in fig. 2, the method includes:
s1: forming a drift region 3 and a body region 2 in a semiconductor substrate 1 by adopting an ion implantation process, which specifically comprises the following steps:
s101: photoetching and defining a region corresponding to the drift region 3 above the semiconductor substrate 1;
s102: implanting ions into a region corresponding to the drift region 3 by adopting an ion implantation process to form the drift region 3, and then removing the photoresist;
s103: photoetching and defining a region corresponding to the body region 2 above the semiconductor substrate 1;
s104: implanting ions into a region corresponding to the body region 2 by adopting an ion implantation process to form the body region 2, and then removing the photoresist;
s105: the semiconductor substrate 1 on which the drift region 3 and the body region 2 are formed is annealed. And the drift region 3 and the body region 2 are simultaneously annealed, so that the process flow is saved. Different ions can be implanted according to different requirements of the device to form the drift region 3 and the body region 2 with different conductivity types. For example, phosphorus ions may be implanted if the N-type drift region 3 needs to be formed, and boron ions may be implanted if the P-type drift region 3 needs to be formed. In the same way, boron implantation is adopted for the NLDMOS device body region 2, and phosphorus implantation is adopted for the PLDMOS device body region 2.
S2: preparing a gate dielectric layer 62 above the semiconductor substrate 1, wherein the gate dielectric layer 62 is composed of a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622; a silicon dioxide layer 621 and a high-K dielectric layer 622 adjacent to the silicon dioxide layer 621 are adjacently arranged above the body region 2 and the drift region 3; a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622 which are alternately stacked are further arranged on the high-K dielectric layer 622 above the drift region 3; the method specifically comprises the following steps:
s201: growing a silicon dioxide material on the surface of the semiconductor substrate 1 to form a silicon dioxide layer 621;
s202: a high-K dielectric layer 622 is formed over the silicon dioxide layer 621, and in this embodiment, a silicon dioxide layer 621 and a high-K dielectric layer 622 are located over the drift region 3 and the body region 2.
S203: defining a graph of the gate dielectric layer 62 above the drift region 3 by adopting a photoetching process;
s204: a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622 which are alternately stacked are formed on the defined pattern of the gate dielectric layer 62 by using an ALD process, in this embodiment, three silicon dioxide layers 621 and two high-K dielectric layers 622 are further formed above the first high-K dielectric layer 622, and the top layer of the gate dielectric layer 62 above the drift region 3 is the silicon dioxide layer 621. The alternating stacking of the silicon dioxide layer 621 and the high-K dielectric layer 622 may be achieved by controlling the growth cycle of the ALD process.
S3: growing an electrode material, and photoetching and etching to define the electrode layer 61, in the embodiment, growing the electrode material by using a sputtering process, then photoetching to define a pattern of the electrode layer 61, and removing redundant material by using an etching method to form the electrode layer 61, wherein the top layer of the gate dielectric layer 62 above the drift region 3 is a silicon dioxide layer 621, and in the embodiment, the electrode material in the step S3 is a polysilicon material;
s4: an ion implantation process is used to form a drain region 4 in the drift region 3 and a source region 5 in the body region 2. In some embodiments, the source region 5 and the drain region 4 are first defined by photolithography, phosphorus ion and arsenic ion implantation is used for NLDMOS devices, boron ion implantation is used for PLDMOS devices, and then rapid annealing is performed on the source region and the drain region. Annealing the drain region 4 and the source region 5 simultaneously saves process flow. The preparation method can be effectively compatible with the existing method, and the process is simple.
Example two
Fig. 3 is a schematic structural diagram of an LDMOS device according to an embodiment of the invention. As shown in fig. 3, the LDMOS device includes: the semiconductor device comprises a semiconductor substrate 1, a gate structure 6, a source region 5, a drain region 4, a body region 2 and a drift region 3; the body region 2 and the drift region 3 are formed in the semiconductor substrate 1; the gate structure 6 is arranged above the semiconductor substrate 1, and one end of the gate structure 6 is positioned above the body region 2, and the other end of the gate structure 6 is positioned above the drift region 3; the source region 5 is formed in the body region 2 and is positioned at one side of the gate structure 6; the drain region 4 is formed in the drift region 3 and is positioned at the other side of the gate structure 6; the gate structure 6 comprises an electrode layer 61 and a gate dielectric layer 62, wherein the gate dielectric layer 62 is composed of a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622; a silicon dioxide layer 621 and a high-K dielectric layer 622 adjacent to the silicon dioxide layer 621 are adjacently arranged above the body region 2 and the drift region 3; a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622 which are alternately stacked are further disposed on the high-K dielectric layer 622 above the drift region 3. The gate dielectric layer 62 above the body region 2 is of a double-layer structure, so that the formation of a conducting channel on the body region 2 is not influenced, and the gate dielectric layer 62 above the drift region 3 is of a stacked structure, so that the voltage resistance of the device is effectively improved. The interface state can be reduced by the contact of the silicon dioxide layer 621 with the semiconductor substrate 1.
In an embodiment, the high-K dielectric layer 622 is a high-K metal oxide layer. For example: al (Al) 2 O 3 、HfO 2 、ZrO 2 And the like.
The high-K metal oxide has a wider forbidden band width and good temperature stability, and the high-K metal oxide layer can improve the temperature stability of the device under extremely cold and extremely hot conditions, so that the industrial application with the service life of 20 years is realized; the high-K metal oxide layer has less dielectric defects and good insulating property, is favorable for improving the reliability of the device, and is similar to the traditional SiO 2 Compared with a dielectric layer, the high-K metal oxide layer is more compact in film formation, less in defect state and better in temperature stability.
In this embodiment, the top layer of the gate dielectric layer 62 above the drift region 3 is a high-K dielectric layer 622, and the electrode layer 61 is a metal electrode layer made of a metal having the same metal element as the metal element of the high-K metal oxide layer. When the top layer of the stacked gate dielectric layer 62 is the high-K dielectric layer 622, the matching degree and compatibility between the gate dielectric layer 62 and the electrode layer 61 can be effectively improved by using the metal electrode layer, and the interface characteristic is better.
The metal electrode layer has strong grid control capability, the temperature stability of the device under the extremely cold and hot conditions can be improved by the grid structure 6 formed by combining the metal electrode layer and the high-K dielectric layer 622, the defects of the high-K dielectric layer 622 are few, the insulating property is good, and the reliability of the device is improved. The metal electrode is made of the same metal element as the high-K metal oxide, so that the matching degree and compatibility of the metal electrode layer and the high-K dielectric layer 622 can be improved, and the interface characteristic is better. For example, the high-K dielectric layer 622 adopts Al 2 O 3 The metal electrode layer is made of Al metal to obtain better interface characteristics; in another example, the high-K dielectric layer 622 is made of HfO 2 The metal electrode layer is made of Hf metal; the following steps are repeated: the high-K dielectric layer 622 is ZrO 2 And the metal electrode layer is made of Zr metal.
Fig. 2 is a method for manufacturing an LDMOS device according to an embodiment of the present invention, where the method is used to manufacture the LDMOS device described in example two, and as shown in fig. 2, the method includes:
s1: forming a drift region 3 and a body region 2 in a semiconductor substrate 1 by adopting an ion implantation process, which specifically comprises the following steps:
s101: photoetching and defining a region corresponding to the drift region 3 above the semiconductor substrate 1;
s102: implanting ions into a region corresponding to the drift region 3 by adopting an ion implantation process to form the drift region 3, and then removing the photoresist;
s103: photoetching and defining a region corresponding to the body region 2 above the semiconductor substrate 1;
s104: implanting ions into a region corresponding to the body region 2 by adopting an ion implantation process to form the body region 2, and then removing the photoresist;
s105: the semiconductor substrate 1 in which the drift region 3 and the body region 2 are formed is annealed. And the drift region 3 and the body region 2 are simultaneously annealed, so that the process flow is saved. Different ions can be implanted according to different requirements of the device to form the drift region 3 and the body region 2 with different conductivity types. For example, phosphorus ions may be implanted if the N-type drift region 3 needs to be formed, and boron ions may be implanted if the P-type drift region 3 needs to be formed. In the same way, boron implantation is adopted for the NLDMOS device body region 2, and phosphorus implantation is adopted for the PLDMOS device body region 2.
S2: preparing a gate dielectric layer 62 above the semiconductor substrate 1, wherein the gate dielectric layer 62 is composed of a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622; a silicon dioxide layer 621 and a high-K dielectric layer 622 adjacent to the silicon dioxide layer 621 are adjacently arranged above the body region 2 and the drift region 3; a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622 which are alternately stacked are further arranged on the high-K dielectric layer 622 above the drift region 3; the method specifically comprises the following steps:
s201: growing a silicon dioxide material on the surface of the semiconductor substrate 1 to form a first silicon dioxide layer 621;
s202: a first high-K dielectric layer 622 is formed over the silicon dioxide layer 621, and in this embodiment, the first silicon dioxide layer 621 and the first high-K dielectric layer 622 are located over the drift region 3 and the body region 2.
S203: defining a graph of the gate dielectric layer 62 above the drift region 3 by adopting a photoetching process;
s204: a plurality of silicon dioxide layers 621 and a plurality of high-K dielectric layers 622 which are alternately stacked are formed on the defined pattern of the gate dielectric layer 62 by using an ALD process, in this embodiment, two silicon dioxide layers 621 and two high-K dielectric layers 622 are further formed above the first high-K dielectric layer 622, and the top layer of the gate dielectric layer 62 above the drift region 3 is the high-K dielectric layer 622. The alternating stacking of the silicon dioxide layer 621 and the K dielectric layer can be achieved by controlling the growth cycle of the ALD process.
S3: growing an electrode material, and defining the electrode layer 61 by photolithography and etching, in this embodiment, a sputtering process is used to grow an electrode material, then a pattern of the electrode layer 61 is defined by photolithography, and excess material is removed by etching, thereby forming the electrode layer 61. In this embodiment, the top layer of the gate dielectric layer 62 above the drift region 3 is the high-K dielectric layer 622, and therefore, the electrode material is made of the same metal material as the metal element of the high-K metal oxide layer.
S4: an ion implantation process is used to form a drain region 4 in the drift region 3 and a source region 5 in the body region 2. In some embodiments, the source region 5 and the drain region 4 are first defined by photolithography, phosphorus ion and arsenic ion implantation is used for NLDMOS devices, boron ion implantation is used for PLDMOS devices, and then rapid annealing is performed on the source region and the drain region. Annealing the drain region 4 and the source region 5 simultaneously saves process flow. The preparation method can be effectively compatible with the existing method, and the process is simple.
The invention also provides a chip, and the chip adopts the LDMOS device. By adopting the LDMOS device, the size of a chip can be reduced, and the speed of the chip is improved.
It should be noted that, in the art, a material having a dielectric constant greater than 3.9 belongs to the high-K material. The dielectric constant of the high-K metal oxide in the present application meets the above range.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.

Claims (12)

1. An LDMOS device comprising: the transistor comprises a semiconductor substrate (1), a gate structure (6), a source region (5), a drain region (4), a body region (2) and a drift region (3); the body region (2) and the drift region (3) are formed in the semiconductor substrate (1); the grid structure (6) is arranged above the semiconductor substrate (1), one end of the grid structure (6) is positioned above the body region (2), and the other end of the grid structure (6) is positioned above the drift region (3); the source region (5) is formed in the body region (2) and is positioned at one side of the gate structure (6); the drain region (4) is formed in the drift region (3) and is positioned at the other side of the gate structure (6);
the grid structure (6) comprises an electrode layer (61) and a grid dielectric layer (62), wherein the grid dielectric layer (62) is composed of a plurality of silicon dioxide layers (621) and a plurality of high-K dielectric layers (622);
a silicon dioxide layer (621) and a high-K dielectric layer (622) adjacent to the silicon dioxide layer (621) are adjacently arranged above the body region (2) and the drift region (3);
and a plurality of silicon dioxide layers (621) and a plurality of high-K dielectric layers (622) which are alternately stacked are further arranged on the high-K dielectric layer (622) above the drift region (3).
2. The LDMOS device of claim 1, wherein the high-K dielectric layer (622) is a high-K metal oxide layer.
3. The LDMOS device as claimed in claim 2, wherein a top layer of the gate dielectric layer (62) above the drift region (3) is a silicon dioxide layer (621) and the electrode layer (61) is a polysilicon electrode layer.
4. The LDMOS device as claimed in claim 2, wherein a top layer of the gate dielectric layer (62) above the drift region (3) is a high-K dielectric layer (622), and the electrode layer (61) is a metal electrode layer made of the same metal as the metal element of the high-K metal oxide layer.
5. A method for fabricating an LDMOS device, the method being used for fabricating the LDMOS device of any one of claims 1-4, the method comprising:
s1: forming a drift region (3) and a body region (2) in a semiconductor substrate (1) by adopting an ion implantation process;
s2: preparing a gate dielectric layer (62) above the semiconductor substrate (1), wherein the gate dielectric layer (62) is composed of a plurality of silicon dioxide layers (621) and a plurality of high-K dielectric layers (622); a silicon dioxide layer (621) and a high-K dielectric layer (622) adjacent to the silicon dioxide layer (621) are adjacently arranged above the body region (2) and the drift region (3); a plurality of silicon dioxide layers (621) and a plurality of high-K dielectric layers (622) which are alternately stacked are further arranged on the high-K dielectric layer (622) above the drift region (3);
s3: growing an electrode material, and photoetching and etching to define an electrode layer (61);
s4: an ion implantation process is used to form a drain region (4) in the drift region (3) and a source region (5) in the body region (2).
6. The method for manufacturing an LDMOS device of claim 5, wherein the high-K dielectric layer (622) is a high-K metal oxide layer.
7. The method for preparing an LDMOS device of claim 6, wherein the preparing a gate dielectric layer (62) over the semiconductor substrate (1) comprises:
s201: growing a silicon dioxide material on the surface of the semiconductor substrate (1) to form a silicon dioxide layer (621);
s202: preparing a high-K dielectric layer (622) above the silicon dioxide layer (621);
s203: defining a graph of a gate dielectric layer (62) above the drift region (3) by adopting a photoetching process;
s204: and forming a plurality of silicon dioxide layers (621) and a plurality of high-K dielectric layers (622) which are alternately stacked on the defined pattern of the gate dielectric layer (62) by adopting an ALD process.
8. The method for manufacturing the LDMOS device of claim 7, wherein a top layer of the gate dielectric layer (62) above the drift region (3) is a silicon dioxide layer (621), and the electrode material in the step S3 is a polysilicon material.
9. The method for manufacturing an LDMOS device of claim 7, wherein a top layer of the gate dielectric layer (62) above the drift region (3) is a high-K dielectric layer (622), and the electrode material in step S3 is a metal material having the same metal element as that of the high-K metal oxide layer.
10. A method for manufacturing an LDMOS device as claimed in claim 5, wherein the forming of the drift region (3) and the body region (2) inside the semiconductor substrate (1) by means of an ion implantation process comprises:
photoetching and defining a region corresponding to the drift region (3) above the semiconductor substrate (1), and injecting ions by adopting an ion injection process to form the drift region (3);
photoetching and defining a region corresponding to the body region (2) above the semiconductor substrate (1), and injecting ions by adopting an ion injection process to form the body region (2);
the semiconductor substrate (1) on which the drift region (3) and the body region (2) are formed is annealed.
11. The method for manufacturing the LDMOS device of claim 5, wherein the electrode material is grown using a sputtering process.
12. A chip, characterized in that the chip employs the LDMOS device of any one of claims 1-4.
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