CN115084235A - LDMOS device, preparation method and chip - Google Patents

LDMOS device, preparation method and chip Download PDF

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Publication number
CN115084235A
CN115084235A CN202210875508.0A CN202210875508A CN115084235A CN 115084235 A CN115084235 A CN 115084235A CN 202210875508 A CN202210875508 A CN 202210875508A CN 115084235 A CN115084235 A CN 115084235A
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metal oxide
layer
oxide layer
semiconductor substrate
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CN115084235B (en
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赵东艳
王于波
郁文
陈燕宁
刘芳
付振
余山
吴波
王帅鹏
刘倩倩
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention provides an LDMOS device, a preparation method and a chip. The device includes: the gate structure comprises a silicon dioxide layer, a high-K metal oxide layer and a metal electrode layer, wherein the silicon dioxide layer is formed above the semiconductor substrate, the high-K metal oxide layer is formed above the silicon dioxide layer, and the metal electrode layer is formed above the high-K metal oxide layer; the high-K metal oxide layer is of a step-shaped structure, and the thickness of the high-K metal oxide layer above the drift region is larger than that of the high-K metal oxide layer above the body region. The device removes an isolation structure between the drain electrode structure and the drift region, shortens a conductive path, reduces the on-resistance, reduces the size of the device and saves the area of a chip; the silicon dioxide layer is connected with the substrate to reduce the interface state; the high-K metal oxide layer is adopted to improve the breakdown voltage of the device, and the defect that the breakdown voltage of the gate structure is reduced after the isolation structure is removed is overcome.

Description

LDMOS device, preparation method and chip
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to an LDMOS device, a preparation method of the LDMOS device and a chip.
Background
With the development of the times, the application fields of semiconductors have also been expanded from traditional industrial control, communication, computers, consumer electronics to new fields such as new energy, smart grid, rail transit, automotive electronics, and the like. The power semiconductor device pursues the handling of electric energy, and is required to have high withstand voltage and large current characteristics itself. As a Lateral power device, an LDMOS (Lateral Double-Diffused MOSFET) has the advantages of high withstand voltage, large gain, good linearity, high efficiency, good broadband matching performance, and the like, and is widely applied to power integrated circuits, especially low-power and high-frequency circuits.
What is more important is that the quality of the LDMOS structure design and the reliability of the operation of the LDMOS determine the performance of the whole power integrated circuit. Therefore, it is highly desirable to fully secure the electrical characteristics and reliability of the device through the optimal design and process improvement of the device.
The traditional device adopts polysilicon as a gate electrode, and in order to prevent gate oxide breakdown and active region breakdown of the device, a shallow trench isolation region or a local oxidation of silicon (LOCOS) isolation region or oxide isolation for reducing a surface electric field is required to be arranged between the gate electrode and a drift region, so that a conductive path is prolonged, a characteristic on-resistance is increased, the area of the device is occupied, and the high performance and small size design of the LDMOS device cannot be realized.
Disclosure of Invention
The LDMOS device removes an isolation structure between a drain region and a drift region, shortens a conducting path, reduces on resistance, reduces the size of the device and saves the area of a chip; meanwhile, the silicon dioxide layer is adopted to connect the high-K metal oxide layer and the substrate, so that the interface state can be reduced; the high-K metal oxide layer can improve the breakdown voltage of the device, and makes up the defect that the breakdown voltage of the gate structure can be reduced after the isolation structure is removed.
In order to achieve the above object, a first aspect of the present invention provides an LDMOS device comprising: the semiconductor device comprises a semiconductor substrate, a gate structure, a source region, a drain region, a body region and a drift region; the body region and the drift region are formed in the semiconductor substrate; the grid structure is arranged above the semiconductor substrate, one end of the grid structure is positioned above the body region, and the other end of the grid structure is positioned above the drift region; the source region is formed in the body region and is positioned on one side of the gate structure; the drain region is formed in the drift region and positioned at the other side of the gate structure; the gate structure comprises a silicon dioxide layer, a high-K metal oxide layer and a metal electrode layer, wherein the silicon dioxide layer is formed above the semiconductor substrate, the high-K metal oxide layer is formed above the silicon dioxide layer, and the metal electrode layer is formed above the high-K metal oxide layer; the high-K metal oxide layer is of a stepped structure, and the thickness of the high-K metal oxide layer above the drift region is larger than that of the high-K metal oxide layer above the body region. The metal electrode layer is beneficial to improving the working speed of a circuit, meanwhile, the metal electrode layer has good grid control capacity and is beneficial to the miniaturization of a device, the grid structure formed by combining the metal electrode layer and the high-K metal oxide layer can improve the temperature stability of the device under the extremely cold and hot conditions, the high-K metal oxide layer has few medium defects and good insulating property, and the reliability of the device is improved.
Optionally, the metal element of the metal electrode layer is the same as the metal element of the high-K metal oxide layer. The matching degree and compatibility of the metal electrode layer and the high-K metal oxide layer are improved, and the interface characteristic is better.
Optionally, a high voltage well region is further formed in the semiconductor substrate, and the drift region and the body region are formed in the high voltage well region.
Optionally, a first shallow trench isolation region and a first protection ring are further disposed in the high-voltage well region, and the first shallow trench isolation region is disposed between the first protection ring and the drift region.
Optionally, a second shallow trench isolation region and a second protection ring are further disposed in the semiconductor substrate, and the second shallow trench isolation region is disposed between the second protection ring and the first protection ring.
Optionally, the first protection ring is a protection ring of a first conductivity type, and the second protection ring is a protection ring of a second conductivity type. The first shallow trench isolation region is used for reducing the voltage drop of the high voltage of the drain electrode, the conduction types of the first protection ring and the second protection ring are different, PN junction isolation can be formed, a circuit outside the second protection ring is protected, the influence of the high voltage of the drain electrode on the circuit outside the second protection ring is reduced, and meanwhile, the influence of external noise on the function of a device can be prevented.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type; or the first conduction type is a P type, and the second conduction type is an N type.
In a second aspect, the present invention provides a method for manufacturing an LDMOS device, the method being used to manufacture the LDMOS device, the method comprising:
s1: forming a high-voltage well region in the semiconductor substrate by adopting an ion implantation process;
s2: forming a drift region and a body region in the semiconductor substrate by adopting an ion implantation process;
s3: growing a silicon dioxide material on the surface of the semiconductor substrate to form the silicon dioxide layer;
s4: preparing a high-K metal oxide by adopting an ALD (atomic layer deposition) process, and forming a high-K metal oxide layer above the silicon dioxide layer;
s5: growing a metal material by adopting a sputtering process, and photoetching and etching to define a metal electrode layer;
s6: and forming a drain region in the drift region and a source region in the body region by adopting an ion implantation process. The process can be completely compatible with the existing LDMOS device preparation method.
Optionally, the step S3 specifically includes:
s401: preparing a high-K metal oxide by adopting an ALD (atomic layer deposition) process, and forming a high-K metal oxide structure above the silicon dioxide layer, wherein the thickness of the high-K metal oxide structure is the same as that of the high-K metal oxide layer above the drift region;
s402: defining a region corresponding to the body region on the formed high-K metal oxide structure by adopting a photoetching process;
s403: and thinning the high-K metal oxide structure in the region range corresponding to the body region by adopting an etching process to obtain a stepped high-K metal oxide layer. The method only adopts one ALD process, and the process is simple.
Optionally, the step S3 specifically includes:
s401: preparing high-K metal oxide by adopting an ALD (atomic layer deposition) process, and forming a first layer of high-K metal oxide structure above the silicon dioxide layer, wherein the thickness of the first layer of high-K metal oxide structure is the same as that of the high-K metal oxide layer above the body region;
s402: defining a region corresponding to the drift region on the formed high-K metal oxide structure by adopting a photoetching process;
s403: and preparing a second layer of high-K metal oxide structure on the high-K metal oxide structure in the range of the corresponding region of the drift region by adopting an ALD (atomic layer deposition) process to obtain the stepped high-K metal oxide layer. According to the method, the high-K metal oxide layer is prepared through the ALD process for two times, and the controllability of the prepared structure is stronger.
Further, the preparation method further comprises the following steps:
after the body region and the drift region are formed, manufacturing a first shallow trench isolation region and a second shallow trench isolation region on the semiconductor substrate;
and after forming the source electrode and the drain electrode, forming a first protection ring and a second protection ring in the semiconductor substrate by adopting an ion implantation process.
A third aspect of the invention provides a chip, which employs the LDMOS device as described above.
According to the technical scheme, the LDMOS device, the preparation method and the chip are provided, the isolation structure between the drain region and the drift region is removed, the conductive path is shortened, the on-resistance is reduced, the size of the device is reduced, and the area of the chip is saved; meanwhile, the silicon dioxide layer is adopted to connect the high-K metal oxide layer and the substrate, so that the interface state can be reduced; the high-K metal oxide layer can improve the breakdown voltage of the device, and makes up the defect that the breakdown voltage of the gate structure can be reduced after the isolation structure is removed. The method is completely compatible with the existing LDMOS preparation process, and the process complexity is low.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for manufacturing an LDMOS device according to an embodiment of the present invention;
FIG. 3 is a flow chart of a process for forming a high-K metal oxide layer in a method for forming an LDMOS device according to a first embodiment of the present invention;
fig. 4 is a flow chart of a process for fabricating a high-K metal oxide layer in a method for fabricating an LDMOS device according to a second embodiment of the present invention.
Description of the reference numerals
The structure comprises a semiconductor substrate 1, a high-voltage well region 2, a drift region 3, a body region 4, a source region 5, a gate structure 6, a metal electrode layer 61, a high-K metal oxide layer 62, a silicon dioxide layer 63, a drain region 7, a shallow trench isolation region 8, a first protection ring 9, a second shallow trench isolation region 10 and a second protection ring 11.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Example one
Fig. 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the invention. As shown in fig. 1, the LDMOS device includes: a semiconductor substrate 1, a gate structure 6, a source region 5, a drain region 7, a body region 4 and a drift region 3; the body region 4 and the drift region 3 are formed in the semiconductor substrate 1; the gate structure 6 is arranged above the semiconductor substrate 1, and one end of the gate structure 6 is positioned above the body region 4, and the other end of the gate structure 6 is positioned above the drift region 3; the source region 5 is formed in the body region 4 and is positioned at one side of the gate structure 6; the drain region 7 is formed in the drift region 3 and located at the other side of the gate structure 6; the gate structure 6 comprises a silicon dioxide layer 63, a high-K metal oxide layer 62 and a metal electrode layer 61, wherein the silicon dioxide layer 63 is formed above the semiconductor substrate 1, the high-K metal oxide layer 62 is formed above the silicon dioxide layer 63, and the metal electrode layer 61 is formed above the high-K metal oxide layer 62; the high-K metal oxide layer 62 has a stepped structure, and the thickness of the high-K metal oxide layer 62 above the drift region 3 is greater than the thickness of the high-K metal oxide layer 62 above the body region 4.
The traditional polycrystalline silicon gate electrode has poor gate control capability and low working speed, and adopts a metal electrodeLayer 61 helps to increase the speed of operation of the circuit. On the other hand, the existence of the polysilicon depletion layer can weaken the gate control capability of the polysilicon gate, and the metal electrode layer 61 adopted by the application has good gate control capability, so that the device is beneficial to being small in size. The stepped structure of the high-K metal oxide layer 62 and the gate structure 6 formed by combining the metal electrode layer 61 and the high-K metal oxide layer 62 better meet the requirements of power devices, the temperature stability of the devices under extremely cold and hot conditions can be improved, and the industrial application with the service life of 20 years can be realized; the high-K metal oxide layer 62 has less medium defects and good insulating property, is favorable for improving the reliability of the device, and is similar to the traditional SiO 2 Compared with the dielectric layer, the high-K metal oxide layer 62 is more compact in film formation, less in defect state and better in temperature stability.
In this embodiment, the metal element of the metal electrode layer 61 is the same as the metal element of the high-K metal oxide layer 62, so that the matching degree and compatibility between the metal electrode layer 61 and the high-K metal oxide layer 62 are increased, and the interface characteristics are better. For example, the high-K metal oxide layer 62 uses Al 2 O 3 The metal electrode layer 61 is made of Al metal to obtain better interface characteristics; as another example, HfO is used for the high-K metal oxide layer 62 2 Then the metal electrode layer 61 is made of Hf metal; the following steps are repeated: the high-K metal oxide layer 62 is ZrO 2 The metal electrode layer 61 is made of Zr metal.
In this embodiment, a high voltage well region 2 is further formed in the semiconductor substrate 1, and the drift region 3 and the body region 4 are formed in the high voltage well region 2.
In this embodiment, a first shallow trench isolation region 8 and a first protection ring 9 are further disposed in the high voltage well region 2, and the first shallow trench isolation region 8 is disposed between the first protection ring 9 and the drift region 3.
In this embodiment, a second shallow trench isolation region 10 and a second protection ring 11 are further disposed in the semiconductor substrate 1, and the second shallow trench isolation region 10 is disposed between the second protection ring 11 and the first protection ring 9.
In this embodiment, the first guard ring 9 is a guard ring of a first conductivity type, and the second guard ring 11 is a guard ring of a second conductivity type. The first shallow trench isolation region 8 is used for reducing the voltage drop of the high voltage of the drain electrode, the first protection ring 9 and the second protection ring 11 are different in conductive type, PN junction isolation can be formed, a circuit outside the second protection ring 11 is protected, the influence of the high voltage of the drain electrode on the circuit outside the second protection ring 11 is reduced, and meanwhile, the influence of external noise on the function of a device can be prevented.
In this embodiment, the guard ring of the first conductivity type is an N-type guard ring, and the guard ring of the second conductivity type is a P-type guard ring. In the present embodiment, the semiconductor substrate 1 is a P-type substrate, and the hvw region 2 is an N-type well.
The LDMOS device provided by the embodiment removes an isolation structure between the drain region and the drift region, shortens a conducting path, reduces the on-resistance, reduces the size of the device and saves the area of a chip; meanwhile, the silicon dioxide layer is adopted to connect the high-K metal oxide layer and the substrate, so that the interface state can be reduced; the high-K metal oxide layer can improve the breakdown voltage of the device, and makes up the defect that the breakdown voltage of the gate structure is reduced after the isolation structure is removed.
Example two
This embodiment provides another LDMOS device, as shown in fig. 1, which includes: a semiconductor substrate 1, a gate structure 6, a source region 5, a drain region 7, a body region 4 and a drift region 3; the body region 4 and the drift region 3 are formed in the semiconductor substrate 1; the gate structure 6 is arranged above the semiconductor substrate 1, and one end of the gate structure 6 is positioned above the body region 4, and the other end of the gate structure 6 is positioned above the drift region 3; the source region 5 is formed in the body region 4 and is positioned at one side of the gate structure 6; the drain region 7 is formed in the drift region 3 and located at the other side of the gate structure 6; the gate structure 6 comprises a silicon dioxide layer 63, a high-K metal oxide layer 62 and a metal electrode layer 61, wherein the silicon dioxide layer 63 is formed above the semiconductor substrate 1, the high-K metal oxide layer 62 is formed above the silicon dioxide layer 63, and the metal electrode layer 61 is formed above the high-K metal oxide layer 62; the high-K metal oxide layer 62 has a stepped structure, and the thickness of the high-K metal oxide layer 62 above the drift region 3 is greater than the thickness of the high-K metal oxide layer 62 above the body region 4.
The traditional polysilicon gate electrode has poor gate control capability and low working speed, and the adoption of the metal electrode layer 61 is beneficial to improving the working speed of a circuit. On the other hand, the existence of the polysilicon depletion layer can weaken the gate control capability of the polysilicon gate, and the metal electrode layer 61 adopted by the application has good gate control capability, so that the device is beneficial to being small in size. The stepped structure of the high-K metal oxide layer 62 and the gate structure 6 formed by combining the metal electrode layer 61 and the high-K metal oxide layer 62 better meet the requirements of power devices, the temperature stability of the devices under extremely cold and hot conditions can be improved, and the industrial application with the service life of 20 years can be realized; the high-K metal oxide layer 62 has less medium defects and good insulating property, is favorable for improving the reliability of the device, and is similar to the traditional SiO 2 Compared with the dielectric layer, the high-K metal oxide layer 62 is more compact in film formation, less in defect state and better in temperature stability.
In this embodiment, the metal element of the metal electrode layer 61 is consistent with the metal element of the high-K metal oxide layer 62, so that the matching degree and compatibility between the metal electrode layer 61 and the high-K metal oxide layer 62 are increased, and the interface characteristics are better. For example, Al is used for the high-K metal oxide layer 62 2 O 3 The metal electrode layer 61 is made of Al metal to obtain better interface characteristics; as another example, HfO is used for the high-K metal oxide layer 62 2 Then the metal electrode layer 61 is made of Hf metal; the following steps are repeated: the high-K metal oxide layer 62 is ZrO 2 The metal electrode layer 61 is made of Zr metal.
In this embodiment, a high voltage well region 2 is further formed in the semiconductor substrate 1, and the drift region 3 and the body region 4 are formed in the high voltage well region 2.
In this embodiment, a first shallow trench isolation region 8 and a first protection ring 9 are further disposed in the hvw region 2, and the first shallow trench isolation region 8 is disposed between the first protection ring 9 and the drift region 3.
In this embodiment, a second shallow trench isolation region 10 and a second protection ring 11 are further disposed in the semiconductor substrate 1, and the second shallow trench isolation region 10 is disposed between the second protection ring 11 and the first protection ring 9.
In this embodiment, the first guard ring 9 is a guard ring of a first conductivity type, and the second guard ring 11 is a guard ring of a second conductivity type. The first shallow trench isolation region 8 is used for reducing the voltage drop of the high voltage of the drain electrode, the first protection ring 9 and the second protection ring 11 are different in conductive type, PN junction isolation can be formed, a circuit outside the second protection ring 11 is protected, the influence of the high voltage of the drain electrode on the circuit outside the second protection ring 11 is reduced, and meanwhile, the influence of external noise on the function of a device can be prevented.
In this embodiment, the guard ring of the first conductivity type is a P-type guard ring, and the guard ring of the second conductivity type is an N-type guard ring. In the present embodiment, the semiconductor substrate 1 is a P-type substrate, and the hvw region 2 is an N-type well.
The LDMOS device provided by the embodiment removes the isolation structure between the drain region and the drift region, shortens the conducting path, reduces the on-resistance, reduces the size of the device and saves the area of a chip; meanwhile, the silicon dioxide layer is adopted to connect the high-K metal oxide layer and the substrate, so that the interface state can be reduced; the high-K metal oxide layer can improve the breakdown voltage of the device, and makes up the defect that the breakdown voltage of the gate structure can be reduced after the isolation structure is removed.
EXAMPLE III
Fig. 2 is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of the present invention, where the method is used to manufacture the LDMOS device, and as shown in fig. 2, the method includes:
s1: the high voltage well region 2 is formed inside the semiconductor substrate 1 using an ion implantation process.
Firstly, defining the position of the high-voltage well region 2 by adopting a photoetching technology, then carrying out ion implantation at the position corresponding to the high-voltage well region 2, then removing photoresist, and then annealing in a nitrogen atmosphere to promote ions to carry out effective diffusion, thereby forming the high-voltage well region 2. Different ions can be implanted into the hvw region 2 according to different requirements of the device to form hvw regions 2 of different conductivity types. For example, if a high voltage N-well is to be formed, phosphorus ions may be implanted, and if a high voltage P-well is to be formed, boron ions may be implanted.
S2: an ion implantation process is used to form a drift region 3 and a body region 4 inside the semiconductor substrate 1.
The specific method of forming the drift region 3 and the body region 4 is the same as the method of forming the hvw region 2, and is not described herein again. Similarly, drift regions 3 and body regions 4 of different conductivity types can be formed according to different requirements of the device, if the N-type drift region 3 is implanted with phosphorus, the P-type drift region 3 is implanted with boron. For NLDMOS devices, boron is used to implant the body region 4, and for PLDMOS devices, phosphorus is used to implant the body region 4. In some embodiments, the drift region 3 and the body region 4 may be annealed simultaneously.
S3: and growing a silicon dioxide material on the surface of the semiconductor substrate 1 to form the silicon dioxide layer 63.
The semiconductor substrate 1 belongs to a silicon-based material, and an ultra-thin silicon dioxide layer is grown on the semiconductor substrate 1 to enhance the interface characteristic between the semiconductor substrate and the silicon dioxide layer.
S4: a high-K metal oxide layer 62 is formed over the silicon dioxide layer 63 using an ALD process to prepare the high-K metal oxide.
In the present embodiment, as shown in fig. 3, the specific steps of forming the high-K metal oxide layer 62 are:
s401: preparing a high-K metal oxide by adopting an ALD (atomic layer deposition) process, and forming a high-K metal oxide structure above the silicon dioxide layer 63, wherein the thickness of the high-K metal oxide structure is the same as that of the high-K metal oxide layer 62 above the drift region 3;
s402: defining a region corresponding to the body region 4 on the formed high-K metal oxide structure by adopting a photoetching process;
s403: and thinning the high-K metal oxide structure in the area range corresponding to the body region 4 by adopting an etching process to obtain a step-shaped high-K metal oxide layer 62 which is thin above the body region 4 and thick above the drift region 3. The method only adopts one ALD process, and the process is simple.
S5: and growing a metal material by adopting a sputtering process, and photoetching and etching to define the metal electrode layer 61.
After the growth of the metal material is completed, the region outside the metal electrode layer 61 is defined by photolithography, and then the excess metal material is removed by etching, and the photoresist is removed, so as to obtain the metal electrode layer 61.
S6: an ion implantation process is used to form a drain region 7 in the drift region 3 and a source region 5 in the body region 4.
The specific method of forming the drain region 7 and the source region 5 is the same as the method of forming the hvw region 2, and is not described herein. The source region 5 and the drain region 7 with different conductive types can be formed according to different requirements of the device, phosphorus and arsenic ion implantation is adopted for the NLDMOS device, and boron ion implantation is adopted for the PLDMOS device. In some embodiments, the source region 5 and the drain region 7 may be annealed simultaneously. The process can be completely compatible with the existing LDMOS device preparation method.
In this embodiment, the preparation method further includes:
after the body region 4 and the drift region 3 are formed, a first shallow trench isolation region 8 and a second shallow trench isolation region 10 are manufactured on the semiconductor substrate 1;
after the source and the drain are formed, a first guard ring 9 and a second guard ring 11 are formed in the semiconductor substrate 1 by using an ion implantation process.
Example four
The embodiment provides a method for manufacturing an LDMOS device, as shown in fig. 2, the method includes:
s1: the high voltage well region 2 is formed inside the semiconductor substrate 1 by an ion implantation process.
Firstly, defining the position of the high-voltage well region 2 by adopting a photoetching technology, then carrying out ion implantation at the position corresponding to the high-voltage well region 2, then removing photoresist, and then annealing in a nitrogen atmosphere to promote ions to carry out effective diffusion, thereby forming the high-voltage well region 2. Different ions can be implanted into the hvw region 2 according to different requirements of the device to form hvw regions 2 of different conductivity types. For example, if a high voltage N-well is to be formed, phosphorus ions may be implanted, and if a high voltage P-well is to be formed, boron ions may be implanted.
S2: an ion implantation process is used to form a drift region 3 and a body region 4 inside the semiconductor substrate 1.
The specific method of forming the drift region 3 and the body region 4 is the same as the method of forming the hvw region 2, and is not described herein again. Similarly, drift regions 3 and body regions 4 of different conductivity types can be formed according to different requirements of the device, if the N-type drift region 3 is implanted with phosphorus, the P-type drift region 3 is implanted with boron. For NLDMOS devices, boron is used to implant the body region 4, and for PLDMOS devices, phosphorus is used to implant the body region 4. In some embodiments, the drift region 3 and the body region 4 may be annealed simultaneously.
S3: and growing a silicon dioxide material on the surface of the semiconductor substrate 1 to form the silicon dioxide layer 63.
The semiconductor substrate 1 belongs to a silicon-based material, and an ultra-thin silicon dioxide layer is grown on the semiconductor substrate 1 to enhance the interface characteristic between the semiconductor substrate and the silicon dioxide layer.
S4: a high-K metal oxide layer 62 is formed over the silicon dioxide layer 63 using an ALD process to prepare the high-K metal oxide.
In this embodiment, as shown in fig. 4, the specific steps of forming the high-K metal oxide layer 62 are:
s401: preparing high-K metal oxide by adopting an ALD (atomic layer deposition) process, and forming a first layer of high-K metal oxide structure above the silicon dioxide layer 63, wherein the thickness of the first layer of high-K metal oxide structure is the same as that of the high-K metal oxide layer 62 above the body region 4;
s402: defining a region corresponding to the drift region 3 on the formed high-K metal oxide structure by adopting a photoetching process;
s403: and preparing a second layer of high-K metal oxide structure on the high-K metal oxide structure in the range of the region corresponding to the drift region 3 by adopting an ALD (atomic layer deposition) process, so as to realize thickening of the high-K metal oxide structure and obtain a step-shaped high-K metal oxide layer 62 which is thin above the body region 4 and thick above the drift region 3. The method prepares the high-K metal oxide layer 62 by two ALD processes, and the controllability of the prepared structure is stronger.
S5: and growing a metal material by adopting a sputtering process, and photoetching and etching to define the metal electrode layer 61.
After the growth of the metal material is completed, the region outside the metal electrode layer 61 is defined by photoetching, then the redundant metal material is removed by etching, and the photoresist is removed, so that the metal electrode layer 61 is obtained.
S6: an ion implantation process is used to form a drain region 7 in the drift region 3 and a source region 5 in the body region 4.
The specific method of forming the drain region 7 and the source region 5 is the same as the method of forming the hvw region 2, and is not described herein. The source region 5 and the drain region 7 with different conductive types can be formed according to different requirements of the device, phosphorus and arsenic ion implantation is adopted for the NLDMOS device, and boron ion implantation is adopted for the PLDMOS device. In some embodiments, the source region 5 and the drain region 7 may be annealed simultaneously. The process can be completely compatible with the existing LDMOS device preparation method.
In this embodiment, the preparation method further includes:
after the body region 4 and the drift region 3 are formed, a first shallow trench isolation region 8 and a second shallow trench isolation region 10 are manufactured on the semiconductor substrate 1;
after the source and the drain are formed, a first guard ring 9 and a second guard ring 11 are formed in the semiconductor substrate 1 by using an ion implantation process.
A third aspect of the invention provides a chip, which employs the LDMOS device as described above. The LDMOS device is beneficial to reducing the size of a chip.
It should be noted that, in the art, a material having a dielectric constant greater than 3.9 belongs to the high-K material. The dielectric constant of the high-K metal oxide in the present application meets the above range.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention. It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.

Claims (12)

1. An LDMOS device comprising: the transistor comprises a semiconductor substrate (1), a gate structure (6), a source region (5), a drain region (7), a body region (4) and a drift region (3); the body region (4) and the drift region (3) are formed in the semiconductor substrate (1); the grid structure (6) is arranged above the semiconductor substrate (1), one end of the grid structure (6) is positioned above the body region (4), and the other end of the grid structure (6) is positioned above the drift region (3); the source region (5) is formed in the body region (4) and is positioned at one side of the gate structure (6); the drain region (7) is formed in the drift region (3) and is positioned at the other side of the gate structure (6); characterized in that the gate structure (6) comprises a silicon dioxide layer (63), a high-K metal oxide layer (62) and a metal electrode layer (61), the silicon dioxide layer (63) being formed above the semiconductor substrate (1), the high-K metal oxide layer (62) being formed above the silicon dioxide layer (63), the metal electrode layer (61) being formed above the high-K metal oxide layer (62); the high-K metal oxide layer (62) is of a stepped structure, and the thickness of the high-K metal oxide layer (62) above the drift region (3) is larger than that of the high-K metal oxide layer (62) above the body region (4).
2. The LDMOS device as set forth in claim 1, characterized in that a metal element of said metal electrode layer (61) is identical to a metal element of said high-K metal oxide layer (62).
3. An LDMOS device as claimed in claim 1, wherein a hvw region (2) is further formed in the semiconductor substrate (1), the drift region (3) and the body region (4) being formed in the hvw region (2).
4. An LDMOS device as claimed in claim 3 wherein a first shallow trench isolation region (8) and a first guard ring (9) are further disposed within the hvw region (2), the first shallow trench isolation region (8) being disposed between the first guard ring (9) and the drift region (3).
5. LDMOS device according to claim 4, characterized in that a second shallow trench isolation region (10) and a second guard ring (11) are further arranged within the semiconductor substrate (1), the second shallow trench isolation region (10) being arranged between the second guard ring (11) and the first guard ring (9).
6. LDMOS device according to claim 5, characterized in that the first guard ring (9) is a guard ring of a first conductivity type and the second guard ring (11) is a guard ring of a second conductivity type.
7. The LDMOS device of claim 6, wherein the first conductivity type is N-type and the second conductivity type is P-type; or the first conduction type is a P type, and the second conduction type is an N type.
8. A method of fabricating an LDMOS device, the method being for fabricating the LDMOS device of any one of claims 1 to 7, wherein the method of fabricating comprises:
s1: forming a high-voltage well region (2) in the semiconductor substrate (1) by adopting an ion implantation process;
s2: forming a drift region (3) and a body region (4) in the semiconductor substrate (1) by adopting an ion implantation process;
s3: growing a silicon dioxide material on the surface of the semiconductor substrate (1) to form the silicon dioxide layer (63);
s4: preparing a high-K metal oxide using an ALD process, forming a high-K metal oxide layer (62) over the silicon dioxide layer (63);
s5: growing a metal material by adopting a sputtering process, and photoetching and etching to define a metal electrode layer (61);
s6: an ion implantation process is used to form a drain region (7) in the drift region (3) and a source region (5) in the body region (4).
9. The method for manufacturing the LDMOS device set forth in claim 8, wherein step S3 specifically includes:
s401: preparing a high-K metal oxide by adopting an ALD (atomic layer deposition) process, and forming a high-K metal oxide structure above the silicon dioxide layer (63), wherein the thickness of the high-K metal oxide structure is the same as that of the high-K metal oxide layer (62) above the drift region (3);
s402: defining a region corresponding to the body region (4) on the formed high-K metal oxide structure by adopting a photoetching process;
s403: and thinning the high-K metal oxide structure in the area range corresponding to the body area (4) by adopting an etching process to obtain a stepped high-K metal oxide layer (62).
10. The method for manufacturing the LDMOS device set forth in claim 8, wherein step S3 specifically includes:
s401: preparing high-K metal oxide by adopting an ALD (atomic layer deposition) process, and forming a first layer of high-K metal oxide structure above the silicon dioxide layer (63), wherein the thickness of the first layer of high-K metal oxide structure is the same as that of the high-K metal oxide layer (62) above the body region (4);
s402: defining a region corresponding to the drift region (3) on the formed high-K metal oxide structure by adopting a photoetching process;
s403: and preparing a second layer of high-K metal oxide structure on the high-K metal oxide structure in the range of the region corresponding to the drift region (3) by adopting an ALD (atomic layer deposition) process to obtain the step-shaped high-K metal oxide layer (62).
11. The method of making an LDMOS device set forth in claim 8 further comprising:
after the body region (4) and the drift region (3) are formed, a first shallow trench isolation region (8) and a second shallow trench isolation region (10) are manufactured on the semiconductor substrate (1);
after the source electrode and the drain electrode are formed, a first protection ring (9) and a second protection ring (11) are formed in the semiconductor substrate (1) by adopting an ion implantation process.
12. A chip employing the LDMOS device of any one of claims 1 to 7.
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