CN115064523B

CN115064523B - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN115064523B
Application number: CN202210944285.9A
Authority: CN
Inventors: 蓝天; 华文宇; 刘藩东
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2022-08-08
Filing date: 2022-08-08
Publication date: 2022-12-13
Anticipated expiration: 2042-08-08
Also published as: CN115064523A

Abstract

The embodiment of the application provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a transistor array; the transistor array comprises a plurality of transistors; the conductive channels of the transistors are vertical to the arrangement direction of the transistor array; an isolation structure located between the transistors; wherein, a trench is arranged in the isolation structure between any two adjacent rows of the transistors; a first charge extraction structure located in the trench; and the second charge leading-out structure is positioned at least part of the opening of the groove and is electrically connected with the first charge leading-out structure.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method for fabricating the same.

Background

In recent years, a transistor array is used in various memories, in which a Memory cell of a Dynamic Random Access Memory (DRAM) is configured by one transistor and one capacitor, and charges are stored by the capacitor to record data. In general, bit Lines (BL) in memory cells of a dram are connected to capacitors of a plurality of memory cells, and the memory cells connected to the same Bit line may affect each other, thereby generating a phenomenon similar to Coupling (Coupling) or Row Hammer (Row Hammer) effect, and causing a performance degradation of a transistor array.

Disclosure of Invention

Embodiments of the present application provide a semiconductor structure and a method for fabricating the same.

In a first aspect, an embodiment of the present application provides a semiconductor structure, including:

an array of transistors; the transistor array comprises a plurality of transistors; the conductive channels of the transistors are vertical to the arrangement direction of the transistor array;

an isolation structure located between the transistors; wherein, a trench is arranged in the isolation structure between any two adjacent rows of the transistors;

a first charge extraction structure located in the trench;

and the second charge leading-out structure is positioned at least part of the opening of the groove and is electrically connected with the first charge leading-out structure.

In some embodiments, the semiconductor structure further comprises:

the word line leading-out structure is connected with one end of a word line coupled with the transistor; wherein the transistors in the same row in the direction parallel to the trench are coupled to the same word line; the word line leading-out structure is positioned on one side of the groove.

In some embodiments, the second charge-extracting structure comprises:

the first conducting layer, the second conducting layer and the conducting sheet layer are sequentially stacked in the extending direction of the conducting channel; the contact surface of the first conductive layer and the second conductive layer is higher than the surface of the word line extraction structure;

the second conductive layer is connected with the first conductive layer and extends to the peripheral region of the transistor array;

the conductive sheet layer is located in the peripheral region and is connected with the second conductive layer.

In some embodiments, the transistor array comprises dummy transistors;

the first conductive layer is connected to the first charge extraction structure at a position adjacent to the dummy transistor.

In some embodiments, the first conductive layer is further connected to the conductive channel of the dummy transistor on both sides of the trench.

In some embodiments, the dummy transistor is located at an edge of the transistor array and adjacent to the peripheral area.

In some embodiments, the word line extraction structure is located in the peripheral region.

In some embodiments, the first conductive layer, the second conductive layer, and the conductive sheet layer are comprised of the same conductive material.

In some embodiments, the isolation structure is comprised of an insulating material and the first charge extraction structure is comprised of a metal.

In a second aspect, embodiments of the present application further provide a method for manufacturing a semiconductor structure, where the method includes:

forming a transistor array; wherein the transistor array comprises a plurality of transistors; the conductive channels of the transistors are vertical to the arrangement direction of the transistor array;

forming an isolation structure between the transistors; wherein, a trench is arranged in the isolation structure between any two adjacent rows of the transistors;

forming a first charge extraction structure in the trench;

and forming a second charge leading-out structure electrically connected with the first charge leading-out structure at least part of the opening of the groove.

In some embodiments, the transistors in the same row in a direction parallel to the trench are coupled to the same word line, the method further comprising:

forming a word line leading-out structure on one side of the groove; the word line leading-out structure is connected with one end of the word line coupled with the transistor; the word line leading-out structure is located in the peripheral area of the transistor array.

In some embodiments, the forming a second charge extraction structure electrically connected to the first charge extraction structure comprises:

sequentially stacking a first conductive layer, a second conductive layer and a conductive sheet layer along the extending direction of the conductive channel; the contact surface of the first conductive layer and the second conductive layer is higher than the surface of the word line extraction structure;

the second conductive layer is connected with the first conductive layer and extends to the peripheral area;

In some embodiments, the forming isolation structures between the transistors comprises:

sidewalls of conductive channels of the transistors in a column direction are filled with an insulating material, and sidewalls of conductive channels of the transistors in a row direction are covered with the insulating material to form the trench in the isolation structure between any two adjacent rows of the transistors.

In some embodiments, the forming a first charge extraction structure in the trench includes:

and filling metal in the groove to form the first charge leading-out structure.

The embodiment of the application provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure isolates adjacent transistors through a first charge leading-out structure positioned between the transistors, and leads coupling charges between the adjacent transistors out of the semiconductor structure through a second charge leading-out structure electrically connected with the first charge leading-out structure, so that the electrical interference and the line hammer effect between storage units can be reduced, and the reliability of the semiconductor structure is improved.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1A is a schematic structural diagram of a buried channel transistor array according to an embodiment of the present application;

fig. 1B is a schematic structural diagram of a buried channel transistor according to an embodiment of the present disclosure;

fig. 2A is a top view of a semiconductor structure according to an embodiment of the present disclosure;

FIG. 2B is a cross-sectional view of the semiconductor structure shown in FIG. 2A along section aa';

FIG. 2C is a top view of a semiconductor structure according to another embodiment of the present application;

FIG. 2D is a side view of the semiconductor structure shown in FIG. 2C;

fig. 3 is a schematic structural diagram of a semiconductor structure according to yet another embodiment of the present application;

fig. 4 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 5A is a first schematic diagram illustrating a process for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 5B is a second schematic diagram illustrating a process for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 5C is a third schematic view of a semiconductor structure fabrication process according to an embodiment of the present disclosure;

FIG. 5D is a fourth schematic diagram illustrating a process for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 5E is a fifth schematic view illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure;

fig. 5F is a sixth schematic view illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure;

fig. 5G is a seventh schematic diagram illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure;

fig. 5H is an eighth schematic diagram illustrating a process for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 5I is a schematic diagram nine illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present application clearer, exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In some embodiments, some technical features that are well known in the art are not described in order to avoid confusion with the present application; that is, not all features of an actual embodiment may be described herein, and well-known functions and structures may not be described in detail.

Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

In some embodiments, the Transistor Array of mainstream memory includes a Planar (Planar) Transistor Array and a Buried Channel Array (BCAT) Transistor Array, however, the source and drain are structurally located on both horizontal sides of the gate, whether the Planar Transistor Array or the Buried Channel Transistor Array.

Fig. 1A shows a schematic structural diagram of a buried channel transistor array, and fig. 1B is a schematic structural diagram of one of the buried channel transistors in fig. 1A. In this configuration, the source 11 and the drain 12 of the transistor are located on the horizontal sides of the gate 13, and the substrates 15 of the memory cells on the same bit line 14 are connected together (not shown), so that the memory cells are affected by each other, thereby generating a phenomenon similar to an electrical coupling or a line hammer.

As shown in fig. 2A and 2B, the present embodiment provides a semiconductor structure. Fig. 2A is a top view of the semiconductor structure, and fig. 2B is a cross-sectional view of the semiconductor structure along a section aa' in fig. 2A. The semiconductor structure includes:

an array of transistors; the transistor array comprises a plurality of transistors; the conductive channels 21 of the plurality of transistors are perpendicular to the arrangement direction of the transistor array; i.e. the direction perpendicular to the substrate surface;

isolation structures 22 between the transistors; wherein, a trench 23 is arranged in the isolation structure 22 between any two adjacent rows of the transistors;

a first charge extraction structure 24 located in the trench 23;

and the second charge leading-out structure 25 is positioned at least part of the opening of the groove 23 and is electrically connected with the first charge leading-out structure.

In the embodiment of the present application, the transistor may have a buried channel structure as shown in fig. 1A and 1B, or may have a vertical channel structure as shown in fig. 2A and 2B, that is, the extending direction of the conductive channel 21 of the transistor is perpendicular to the arrangement direction of the transistor array. For example, the plurality of transistors may be arranged at intervals in the row direction and the column direction in the horizontal direction, and the conductive channel 21 extends in the vertical direction.

Specifically, referring to fig. 2B, each transistor further includes a gate oxide layer 26 and a gate conductive layer 27. Here, a gate oxide layer 26, which may be composed of silicon oxide, silicon nitride or other insulating material, is located between the gate conductive layer 27 and the conductive channel 21 for electrically isolating the gate conductive layer 27.

Illustratively, the gate conductive layer 27 in the embodiment of the present application, like the conductive channel 21, may extend in a direction perpendicular to the arrangement direction of the transistor array, and the gate conductive layer 27 between two adjacent transistors may be separated by the insulating layer 28. The insulating layer 28 is formed by filling a dielectric material between the transistors during the fabrication of the transistors, and will not be described herein.

In some embodiments, the transistor array may be located on a substrate, where the substrate may include, but is not limited to, a Silicon (Si) substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon On Insulator (SOI) substrate, or a Germanium On Insulator (GOI) substrate, and the like, and the substrate may be P-type doped or N-type doped.

Further, referring to fig. 2B, in addition to the insulating layer 28 between the gate conductive layers 27, the conductive channels 21 may be spaced apart between adjacent transistors by the isolation structures 22. The isolation structure 22 here may also consist of an insulating material. Illustratively, the transistors may be filled with an insulating material, and then a partial depth of the insulating material is removed by an etching process to form an isolation structure 22 and a trench 23 between two adjacent rows of transistors. It will be appreciated that in the cross-section shown in fig. 2B, the isolation structure 22 between two adjacent transistors covers the sidewalls of the conductive channel 21; in a plane perpendicular to the cross section shown in fig. 2B, two adjacent rows of the transistors are connected by the isolation structure 22.

Note that, in the drawings of the present application, a transistor having a symmetrical structure is taken as an example, and as shown in fig. 2B, an insulating layer 28 separates two symmetrical transistors. There is an isolation structure 22 between two adjacent pairs of transistors. However, in practical applications, the isolation structure 22 may be located between any two transistors, that is, there may be one isolation structure 22 between every two transistors, that is, there may be one isolation structure between every other transistor.

In the present embodiment, the trench 23 may be filled with a conductive material to form the first charge extraction structure 24. It will be appreciated that the first charge extraction structure 24 is here located in the trench 23 at a height less than or equal to the depth of the trench 23 and is electrically isolated from the conductive channel 21 by an isolation structure.

Further, referring to fig. 2B, the second charge extraction structure 25 at the opening of the trench 23 may be electrically connected to the first charge extraction structure 24 in the trench 23. It should be noted that the second charge extraction structure 25 in the embodiment of the present application may be located above the transistor array, or may be located in a peripheral region on one side of the transistor array, so as to reduce electrical interference to the transistors.

Therefore, in the embodiment of the present application, the semiconductor structure isolates the adjacent transistors through the first charge extraction structure 24 located between the transistors, and extracts the coupled charges between the adjacent transistors through the second charge extraction structure electrically connected with the first charge extraction structure, so that the electrical interference and the line hammer effect between the memory cells can be reduced, thereby improving the reliability of the semiconductor structure.

In some embodiments, as shown in fig. 2C and 2D, the semiconductor structure further comprises:

a word line extraction structure 29 connected to one end of a word line coupled to the transistor; wherein the transistors in the same row in the direction parallel to the trench 23 are coupled to the same word line; the word line extraction structure 29 is located at one side of the trench 23.

Fig. 2C is a top view of the semiconductor structure, and fig. 2D is a side view of the semiconductor structure shown in fig. 2C.

Referring to fig. 2C, the word lines of the transistors are connected to the gate conductive layers 27 of the transistors in the same row or the same column. It is emphasized that in fig. 2B, the gate conductive layer 27 of each transistor is buried in the insulating layer 28, and therefore, the dashed line in fig. 2C indicates the connection relationship between the word line extraction structure 29 and the word line in the insulating layer 28, and does not necessarily have to be the position of the actual structure.

Illustratively, word line out structure 29 may be a Pad (Pad) or other conductive structure for connecting to a word line driver and electrically connecting to a voltage generator in a peripheral circuit. In this way, the word line voltage generated by the voltage generator can be transmitted to the corresponding word line drawing structure 29 via the word line driver, and finally applied to the gate conductive layer of the transistor.

Illustratively, the word line extraction structure 29 may be located on one side of the transistor array, specifically, on one side of the trench 23 described above. In this way, word lines coupled to transistors in the same row and the trenches 23 can be arranged in parallel, thereby reducing the difficulty of wiring and increasing the convenience of operation.

In some embodiments, as shown in fig. 3, the second charge extracting structure 25 includes:

a first conductive layer 31, a second conductive layer 32, and a conductive sheet layer 33 stacked in this order in the extending direction of the conductive channel 21; the contact surface of the first conductive layer 31 and the second conductive layer 32 is higher than the surface of the word line leading-out structure 29;

the second conductive layer 32 is connected to the first conductive layer 31 and extends to a peripheral region 34 of the transistor array;

the conductive sheet layer 33 is located in the peripheral region 34 and connected to the second conductive layer 32.

It is noted that fig. 3 is an alternative side view of the semiconductor structure based on fig. 2D. In the embodiment of the present application, the peripheral region 34 in fig. 3 is a general expression of the region outside the transistor array, and in other embodiments, the peripheral region 34 may also be a peripheral circuit of the memory, which is not limited herein,

specifically, the second charge extraction structure 25 in the embodiment of the present application is electrically connected to the first charge extraction structure 24 in the transistor array through the first conductive layer 31. The first conductive layer 31 may be made of a first conductive material, such as titanium-metal or titanium nitride-metal, so as to enhance the performance of the electrical contact. In the embodiment of the present application, the first conductive layer 31 may be a contact Plug (Plug).

Further, a conductive material may be deposited on the upper surface of the first conductive layer 31 to form the second conductive layer 32. Second conductive layer 32 may be made of a second conductive material, such as a metal, so that a metal interconnection structure may be formed. In the embodiment of the present application, the second conductive layer 32 may be a Metal interconnection line (Metal), and may extend in a horizontal plane into the peripheral region 34 after contacting the first conductive layer 31. It will be appreciated that only a portion of second conductive layer 32 is shown in fig. 3 within peripheral region 34.

For example, a conductive sheet layer 33 may be stacked on the upper surface of the second conductive layer 32, where the conductive sheet layer 33 may be made of a third conductive material, such as an alloy, which may have good ductility, greater hardness and better heat resistance than metal. In the embodiment of the present application, the conductive sheet layer 33 may be a pad or other electrical leading structure for leading out the charges generated between the transistors due to the electrical coupling to the outside of the transistor array.

It should be noted that, in other embodiments, the first conductive layer 31, the second conductive layer 32 and the conductive sheet layer 33 may be connected through a conductive Via (Via), and the thicknesses, heights and material properties of the first conductive layer 31, the second conductive layer 32 and the conductive sheet layer 33 need to be determined according to actual production requirements, which is not limited herein.

Referring to fig. 3, in the extending direction of the conductive channel 21, the height of the first conductive layer 31 may be greater than the height of the word line extracting structure 29, so that in the peripheral region 34, the lower surface of the second conductive layer 32, that is, the contact surface between the first conductive layer 31 and the second conductive layer 32 is higher than the upper surface of the word line extracting structure 29, thereby electrically isolating the word line extracting structure 29 from the second charge extracting structure 25, reducing electrical interference between devices, and improving reliability of the transistor array.

In some embodiments, the transistor array comprises dummy transistors;

the first conductive layer 31 is connected to the first charge extraction structure 24 at a position adjacent to the dummy transistor.

In the embodiment of the present application, a plurality of transistors which can be divided into a transistor serving as a memory and a dummy transistor serving as a support according to a use function are included in a transistor array. Wherein the conductive channel of the dummy transistor has no free charge available for the memory function.

Illustratively, the embodiment of the present application may dispose the second charge extraction structure 25 in an adjacent position to the dummy transistor. Specifically, the opening of the trench 23 may be filled with a conductive material through photolithography, etching, deposition, planarization, and the like to form the first conductive layer 31.

In the embodiment of the present application, the bottom surface of the first conductive layer 31 is connected to the first charge extraction structure 24, the isolation structure 22, and the conductive channels of the dummy transistors on two sides, so that the width of the first conductive layer 31 can be increased, thereby reducing the difficulty of the photolithography process and the subsequent processes.

In the embodiments of the present application, the transistors are arranged in a row direction and a column direction to form the transistor array, and at least one dummy transistor may be included at an edge of the transistor array. Further, the second charge leading-out structure is connected with the first charge leading-out structure and a part of the conductive channel between the conductive channels of the dummy transistors, so that the length of the second conductive layer 32 can be reduced, the cost is saved, and the wiring difficulty is reduced.

In some embodiments, the word line extraction structures 29 are located in the peripheral region 34.

The word line leading-out structure 29 according to the embodiment of the present invention is coupled to word lines of transistors, and gates of the transistors in the same row are connected to the same word line, so that the word line leading-out structure 29 according to the embodiment of the present invention can be connected to one end of the word line coupled to the transistors.

Further, the word line extraction structure 29 may be located in a peripheral region beside the transistor array, which may make the storage density of the transistor array greater; on the other hand, it is possible to facilitate connection of electronic components such as word line drivers and voltage generators in the peripheral region.

In some embodiments, the first conductive layer 31, the second conductive layer 32, and the conductive sheet layer 33 are composed of the same conductive material.

In the above embodiments, the first conductive layer 31, the second conductive layer 32 and the conductive sheet layer 33 may be made of different materials to meet different use requirements of the transistor array. In the embodiment of the present application, the first conductive layer 31, the second conductive layer 32, and the conductive sheet layer 33 may also be made of the same conductive material, such as metal, alloy, or other conductive materials, so that the second charge extraction structure may be formed sequentially through a deposition process, thereby reducing process steps. On the other hand, when the electric charge is extracted, the electric interference generated due to the difference of the conductive materials can be reduced, thereby improving the reliability of the memory.

In some embodiments, the isolation structure 22 is comprised of an insulating material and the first charge extraction structure 24 is comprised of a metal.

In the embodiment of the present application, the isolation structure 22 is used for electrically isolating the conductive channels 21 of the adjacent transistors, and may be made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials; the first charge extraction structure 24 is located in the trench 23 between the transistors, and is used for extracting charges generated by the electric coupling between the transistors and the line hammer effect, where the first charge extraction structure 24 may be made of metal, such as tungsten, copper or other metal materials, so that the first charge extraction structure has better conductivity, and facilitates extracting charges related to electric interference from the transistor array as soon as possible.

Referring to fig. 4, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, where the method includes:

step S401, forming a transistor array; wherein the transistor array comprises a plurality of transistors; the conductive channels of the transistors are vertical to the arrangement direction of the transistor array;

step S402, forming an isolation structure between the transistors; wherein, a trench is arranged in the isolation structure between any two adjacent rows of the transistors;

step S403, forming a first charge extraction structure in the trench;

and S404, forming a second charge leading-out structure electrically connected with the first charge leading-out structure at least part of the opening of the groove.

In step S401, the transistor array may be formed on a wafer through etching, deposition, and other processes. The wafer may be a single crystal silicon wafer used for manufacturing the semiconductor structure, a silicon wafer on which devices or circuits are mounted after processing, or a chip base made of another material as known to those skilled in the art.

Fig. 5A and 5B show partial cross-sectional views of a transistor array during fabrication.

Specifically, as shown in fig. 5A, two adjacent transistors 510 may be spaced apart by a silicon substrate 520. Further, referring to fig. 5B, the silicon substrate 520 is subjected to a photolithography or etching process to form a deep trench 530.

In the embodiment of the present application, the conductive channel 21 of each transistor 510 in the transistor array is perpendicular to the surface of the silicon substrate 520 and is buried in the silicon substrate 520, and thus, the transistor in the embodiment of the present application is a BCAT structure, i.e., a buried channel transistor. Illustratively, each transistor 510 further includes a gate oxide layer 26 overlying sidewalls of the conductive channel 21, a gate conductive layer 27 overlying sidewalls of the gate oxide layer 26, and an insulating layer 28 between adjacent gate conductive layers 27.

In step S402, an insulating material may be filled in the deep trench 530 through a deposition process to form the isolation structure 22. The Deposition process herein may include, but is not limited to, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), and the like.

Illustratively, referring to fig. 5C, the deep trenches 530 are filled with silicon nitride, silicon oxide, or other insulating material by a thin film deposition process to electrically isolate adjacent transistors 510. Further, in the embodiment of the present application, a partial depth of the insulating material may be removed between any two adjacent rows of transistors 510 through an etching process to form the isolation structure 22 and the trench 23. It will be appreciated that in the cross-section shown in fig. 5C, the isolation structure 22 between two adjacent transistors covers the sidewalls of the conductive channel 21; in a plane perpendicular to the cross section shown in fig. 5C, any two adjacent rows of the transistors 510 are connected by the isolation structure 22. In other embodiments, the isolation structure 22 may be formed by a deposition process only, and the application is not limited thereto.

In step S403, referring to fig. 5D, a conductive material, such as a metal, may be filled in the trench 23 through a thin film deposition process to form the first charge extracting structure 24. In the present embodiment, the first charge extraction structure 24 is electrically isolated from the conductive channel 21 of the transistor 510 by the isolation structure 22.

It should be noted that after the deposition processes of step S402 and step S403, the excess insulating material and the conductive material on the upper surface of the transistor array may be removed by a surface planarization process, such as Chemical Mechanical Polishing (CMP), respectively.

Further, as shown in fig. 5E, after filling the conductive material, an etching process may be employed to remove a portion of the first charge extraction structure at the top of the trench 23 to form an opening 570. The Etching process herein may include, but is not limited to, one or more of Ion mill Etching (Ion Neam Milling Etching), plasma Etching (Plasma Etching), reactive Ion Etching (Reactive Ion Etching), laser Ablation (Laser Ablation), wet Etching, or photolithography.

In step S404, referring to fig. 5F, a conductive material is filled in the opening 570 at the top of the trench 23 to form a second charge extraction structure 25 electrically connected to the first charge extraction structure 24. In other embodiments, referring to fig. 5G, the second charge extracting structure 25 may also be at least partially in contact with the conducting channel 21 of the transistor. It is emphasized that the transistors are dummy transistors in the transistor array, i.e. transistors not used for storing data, which can reduce the difficulty of the etching process and increase the contact area, so that the charges can be better led out of the transistor array.

According to the manufacturing method of the semiconductor structure provided by the embodiment of the application, the first charge extraction structures 24 are formed between the transistors 510, adjacent transistors can be isolated, the second charge extraction structures 25 electrically connected with the first charge extraction structures 24 are formed, and coupled charges between the adjacent transistors can be extracted out of the semiconductor structure. In this manner, electrical interference between memory cells and row hammer effects may be reduced, thereby improving the reliability of the semiconductor structure.

In some embodiments, referring to fig. 5H, the transistors in the same row in the parallel direction with the trench 23 are coupled to the same word line, and the method further includes:

forming a word line leading-out structure 29 on one side of the groove 23; wherein the word line leading-out structure 29 is connected with one end of the word line coupled with the transistor; the word line extraction structures 29 are located in the peripheral region of the transistor array.

It is understood that fig. 5H is a top view of the semiconductor structure shown in fig. 5A to 5G. In the embodiment of the present application, the word line extracting structure 29 may be pre-disposed in the peripheral region of the transistor array before the transistor array is formed, that is, before step S401, or may be formed in the peripheral region by etching, depositing, and other processes after the transistor array is formed, which is not limited herein.

In some embodiments, the word line out structure 29 may be a Pad (Pad) or other conductive structure for connecting to a word line driver and electrically connecting to a voltage generator in a peripheral circuit. In this way, the word line voltage generated by the voltage generator can be transmitted to the corresponding word line drawing structure 29 via the word line driver, and finally applied to the gate conductive layer of the transistor.

In some embodiments, referring to fig. 5I, the forming of the second charge extraction structure 25 electrically connected to the first charge extraction structure 24 includes:

sequentially stacking a first conductive layer 31, a second conductive layer 32 and a conductive sheet layer 33 along the extending direction of the conductive channel 21; the contact surface of the first conductive layer 31 and the second conductive layer 32 is higher than the surface of the word line extraction structure 29;

the second conductive layer 32 is connected to the first conductive layer 31 and extends to the peripheral region;

the conductive sheet layer 33 is located in the peripheral region and is connected to the second conductive layer 32.

Specifically, the second charge extraction structure 25 according to the embodiment of the present application may fill the opening 570 at the top of the trench with the first conductive material to form the first conductive layer 31; further, a second conductive material and a third conductive material are sequentially deposited on the first conductive layer 31 to form a stacked second conductive layer 32 and a conductive sheet layer 33, respectively.

It should be noted that the first conductive material, the second conductive material and the third conductive material are only used for distinguishing the process, and in the actual operation process, the conductive materials may be the same, so that the process steps may be simplified, and the electrical interference caused by the difference of the materials may be reduced.

Exemplarily, referring to fig. 5I, in the extending direction of the conductive channel 21, the height of the first conductive layer 31 may be greater than the height of the word line extracting structure 29, so that in the peripheral region, the lower surface of the second conductive layer 32, i.e., the contact surface between the first conductive layer 31 and the second conductive layer 32, is higher than the upper surface of the word line extracting structure 29, thereby electrically isolating the word line extracting structure 29 from the second charge extracting structure 25, reducing the electrical interference between devices, and improving the reliability of the transistor array.

In step S401 of the embodiment of the present application, referring to fig. 5B, a plurality of transistors in the transistor array are spaced from each other by the deep trench 530. Further, fig. 5C is a schematic diagram of the transistor array after forming the isolation structure 22 and the trench 23. It will be appreciated that the isolation structures 22 fill the deep trenches 530 between two adjacent transistors in a direction perpendicular to the cross-section shown in fig. 5B and 5C.

Illustratively, fig. 5B and 5C show schematic cross-sectional views in the row direction of the transistor array, the conductive channels of the transistors in the column direction are filled with an insulating material, and the conductive channels of the transistors in the row direction are covered with an insulating material, to form trenches 23 as shown in fig. 5C.

and filling metal in the groove to form the first charge leading-out structure.

In step S403 of the present embodiment, as shown in fig. 5D, the trenches 23 are filled with a metal, such as tungsten, copper, or other metal materials, by a thin film deposition process, so as to improve the conductivity of the first charge extraction structure 24.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A semiconductor structure, comprising:

the first charge leading-out structure is positioned in the groove, and the height of the first charge leading-out structure is less than or equal to the depth of the groove;

the second charge leading-out structure is positioned at least part of the opening of the groove and is electrically connected with the first charge leading-out structure; at least a portion of the second charge extraction structure is located outside of the transistor array.

2. The semiconductor structure of claim 1, further comprising:

3. The semiconductor structure of claim 2, wherein the second charge extraction structure comprises:

the first conducting layer, the second conducting layer and the conducting sheet layer are sequentially stacked in the extending direction of the conducting channel; wherein,

the contact surface of the first conductive layer and the second conductive layer is higher than the surface of the word line leading-out structure;

4. The semiconductor structure of claim 3, wherein the array of transistors comprises dummy transistors;

5. The semiconductor structure of claim 4, wherein the first conductive layer is further connected to a conductive channel of the dummy transistor on both sides of the trench.

6. The semiconductor structure of claim 4, wherein the dummy transistor is located at an edge of the array of transistors and adjacent to the peripheral region.

7. The semiconductor structure of claim 3, wherein the word line extraction structure is located in the peripheral region.

8. The semiconductor structure of claim 3, wherein the first conductive layer, the second conductive layer, and the conductive sheet layer are comprised of the same conductive material.

9. The semiconductor structure of claim 1, wherein the isolation structure is comprised of an insulating material and the first charge extracting structure is comprised of a metal.

10. A method of fabricating a semiconductor structure, the method comprising:

forming a first charge extraction structure in the trench, wherein the height of the first charge extraction structure is less than or equal to the depth of the trench;

and forming a second charge leading-out structure electrically connected with the first charge leading-out structure at least part of the opening of the groove, wherein at least part of the second charge leading-out structure is positioned outside the transistor array.

11. The method of manufacturing of claim 10, wherein the transistors in the same row in a direction parallel to the trench are coupled to a same wordline, the method further comprising:

12. The method of manufacturing of claim 11, wherein the forming a second charge extraction structure electrically connected to the first charge extraction structure comprises:

sequentially stacking along the extending direction of the conductive channel to form a first conductive layer, a second conductive layer and a conductive sheet layer; wherein,

13. The method of manufacturing of claim 10, wherein the forming isolation structures between the transistors comprises:

14. The method of manufacturing of claim 11, wherein the forming a first charge extraction structure in the trench comprises:

and filling metal in the groove to form the first charge leading-out structure.