CN111564442A

CN111564442A - Semiconductor structure and preparation method

Info

Publication number: CN111564442A
Application number: CN202010280451.0A
Authority: CN
Inventors: 崔锺武; 金成基
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2020-04-10
Filing date: 2020-04-10
Publication date: 2020-08-21
Anticipated expiration: 2040-04-10
Also published as: CN111564442B

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor structure, which comprises: a semiconductor substrate in which a first trench and a second trench are provided; the second grooves are arranged between the first grooves; the gate stack structure is filled at the lower part of the first groove; and the groove isolation structure is arranged in the second groove and comprises an air gap. The air gap can reduce the dielectric constant of the trench isolation structure due to the smaller dielectric constant of the air, so that the coupling effect of adjacent word lines is reduced, the row hammering effect between adjacent active regions is reduced, and the reliability of a semiconductor device is improved.

Description

Semiconductor structure and preparation method

Technical Field

The application relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background

With the development of semiconductor memory technology, users have increasingly high requirements for device reliability, especially for Dynamic Random Access Memory (DRAM) devices. However, the current DRAM faces the following problems: one Row (Row) in the memory matrix is activated, which when repeatedly refreshed generates noise or interference to adjacent rows. If the activation frequency of the row is too high before the adjacent Cell (Cell) is activated or refreshed, the adjacent Cell becomes weak, and a problem of Charge Loss or Leakage occurs. Which in turn causes errors in the Data (Data) of one or more cells in an adjacent row, a phenomenon known as the so-called row hammer Effect (RowHammer Effect).

Disclosure of Invention

The present application addresses, at least to some extent, the above-mentioned technical problems in the related art. Therefore, the present application provides a semiconductor structure and a manufacturing method thereof to improve the reliability of the conventional semiconductor device.

In order to achieve the above object, a first aspect of the present application provides a semiconductor structure comprising:

a semiconductor substrate in which a first trench and a second trench are provided; the second grooves are arranged between the first grooves;

the gate stack structure is filled at the lower part of the first groove;

and the groove isolation structure is arranged in the second groove and comprises an air gap.

In a second aspect, the present application provides a method for fabricating a semiconductor structure, comprising the steps of:

forming two adjacent first trenches in a semiconductor substrate;

forming a gate stack structure at the lower part of the first trench;

forming a second groove on the semiconductor substrate of two adjacent first grooves;

and depositing and forming a trench isolation structure with an air gap in the second trench.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram illustrating a portion of a buried channel array transistor in a semiconductor structure according to an embodiment of the present application;

FIG. 2 shows a schematic view of the structure after a dielectric layer is formed over the structure shown in FIG. 1;

FIG. 3 is a schematic diagram of the structure of FIG. 2 after the dielectric layer overlying the first mask pattern layer is removed;

FIG. 4 is a schematic diagram showing a structure after etching and a second mask pattern layer is deposited on the structure shown in FIG. 3;

FIG. 5 is a schematic diagram illustrating the structure of FIG. 4 after sidewall spacers are deposited thereon;

FIG. 6 shows a schematic view of the structure after etching to form a second trench on the structure shown in FIG. 5;

FIG. 7 shows a schematic view of the structure after deposition of a trench isolation structure and a sacrificial layer on the structure shown in FIG. 6;

FIG. 8 is a schematic diagram of the structure of FIG. 7 after deposition of SiN after removal of the sacrificial layer;

FIG. 9 shows a schematic view of the structure of FIG. 8 after a third mask pattern layer is deposited and etched;

fig. 10 shows a schematic diagram of the structure after deposition of a bit line contact over the structure of fig. 9.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

Referring to fig. 10, a cross-sectional view of a semiconductor structure 100 is illustrated, in accordance with some embodiments of the present invention. A first aspect of the present application provides a semiconductor structure 100, the semiconductor structure 100 comprising:

a semiconductor substrate 10 having at least one active area (ActiveArea)102 defined by a device isolation structure 101, the semiconductor substrate 10 in this embodiment being, for example, a bulk silicon semiconductor substrate, a silicon-on-insulator (SOI) semiconductor substrate, a germanium-on-insulator (GOI) semiconductor substrate, a silicon germanium semiconductor substrate, a III-V compound semiconductor substrate, or an epitaxial thin film semiconductor substrate obtained by performing Selective Epitaxial Growth (SEG).

When the semiconductor substrate 10 is a silicon-based semiconductor substrate, the semiconductor substrate 10 may include, for example, dangling bonded silicon atoms that are not bonded to oxygen ions. The operating characteristics of the transistor may be stabilized by a hydrogen annealing process by which hydrogen atoms are bonded to dangling-bonded silicon atoms of the semiconductor substrate 10. In this case, the hydrogen atom may be easily separated from the silicon atom, but boron may increase the binding energy between the silicon atom and the hydrogen atom. Thus, the variable retention time or charge retention time of a memory cell (e.g., capacitor CP) in a semiconductor structure may be improved.

Each active region 102 may have source/drain regions therein and may have a conductivity different from that of the semiconductor substrate 10. For example, the source/drain regions may have P-type conductivity to form a PMOS transistor. In one embodiment, the source/drain region may include a trivalent impurity element. The source/drain regions may include, for example, boron (B) or indium (In).

Since the atomic weight of indium is larger than that of other trivalent impurity elements, indium may be uniformly dispersed in the source/drain regions in one embodiment. Thus, an improved distribution of the threshold voltage can be achieved, and electron leakage between the word line WL and the capacitor CP can be reduced or prevented.

In the present embodiment, the active region 102 defined by the device isolation structure 101 electrically isolates adjacent memory cells (cells) from each other. In some embodiments, the device isolation structure 101 comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (k) dielectric material, other suitable materials, or combinations thereof. In some embodiments, the device isolation structure 101 is formed by using isolation techniques, such as local oxidation of semiconductor (LOCOS), trench isolation, and the like. For example, the device isolation structure 101 may be a Deep Trench Isolation (DTI) structure formed by using a trench isolation technique.

A first trench 103 and a second trench 104 are opened in the semiconductor substrate 10 corresponding to the active region 102. Two gate stack structures 11 respectively disposed in the first trenches 103; a Trench Isolation (Trench Isolation) structure 12 is disposed in the second Trench 104, and an Air Gap (Air Gap)120 is formed in the Trench Isolation structure 12.

In some embodiments, the semiconductor structure 100 further comprises: the first mask pattern layer 13 is disposed on the semiconductor substrate 10, and the first trench 103 is formed by etching the semiconductor substrate 10 using the first mask pattern layer 13 as an etching mask. In some embodiments, the first mask pattern layer 13 is a hard mask pattern layer and may be made of silicon oxide or other suitable hard mask material.

In some embodiments, the depth of the second trench 104 is greater than the depth of the first trench 103 and less than the depth of the device isolation structure 101. Further, the top of the gate stack structure 11 is lower than the top of the first trench 103. I.e. the gate stack 11 does not completely fill the first trench 103.

15. In some embodiments, the gate stack 11 is a word line, including: a gate metal layer 111, wherein the gate metal layer 111 is formed on the side wall and the bottom wall of the first trench 103; the gate dielectric layer 112 is sandwiched between the gate metal layer 111 and the semiconductor substrate 10. The gate dielectric layer 112 may comprise titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (k) dielectric material, other suitable materials, or combinations thereof. In addition, the gate metal layer 111 may include a metal or other suitable electrode material, and in the present embodiment, the gate metal layer 111 may be metal tungsten.

In the present embodiment, the trench isolation structure 12 is made of silicon oxide or other suitable insulating material. In some embodiments, the upper surface of the trench isolation structure 12 is lower than the upper surface of the device isolation structure 101. Furthermore, the upper surface of the trench isolation structure 12 is higher than the upper surface of the gate stack structure 11, and the lower surface of the trench isolation structure 12 is lower than the lower surface of the gate stack structure 11. In some embodiments, the length direction of the gate stack structure 11 is substantially parallel to the length direction of the trench isolation structure 12, as viewed from the top view direction. For example, the gate stack structure 11 and the trench isolation structure 12 may be rectangular when viewed from the top, and the two are parallel to each other in the length extending direction.

In this embodiment, the semiconductor structure 100 further includes: a dielectric layer 14, wherein the dielectric layer 14 is located above the first mask pattern layer 13 and fills the first trench 103 to cover the gate stack 11. In some embodiments, the dielectric layer 14 provides protection for the gate stack 11 and may be made of silicon nitride or other suitable insulating material. In some embodiments, a third trench 140 is opened in the dielectric layer 14, the third trench 140 is located above the second trench 104, and the bottom of the third trench 140 exposes the trench isolation structure 12.

In this embodiment, the semiconductor structure 100 further includes: a bit line contact 15, the bit line contact 15 being disposed in the third trench 140, a portion of a lower surface of the bit line contact 15 contacting the trench isolation structure 12, and a portion of the bit line contact 15 being located above the second trench 104. The bit line contact 15 may serve as a common source electrode for the gate stack 11. Since the upper surface of the trench isolation structure 12 is higher than the upper surface of the gate stack structure 11, the bit line contact 15 does not electrically contact the gate stack structure 11. In some embodiments, the bit line contact 15 is comprised of polysilicon or other suitable electrode material. For example, the bit line contact 15 may be a polysilicon layer having an n-type dopant.

Fig. 1-10 illustrate cross-sectional views of intermediate stages of semiconductor structure fabrication, in accordance with some embodiments of the present application. Referring to fig. 1, fig. 1 is a schematic diagram of a structure of a Buried Channel Array Transistor (BCAT) in a memory cell, which illustrates a semiconductor substrate 10. The semiconductor substrate 10 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The semiconductor substrate 10 may also be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 10 may include silicon, germanium, a compound semiconductor, an alloy semiconductor, or a combination thereof.

In the present embodiment, the device isolation structure 101 may be formed by using an isolation technique (e.g., local oxidation of semiconductor (LOCOS), trench isolation, etc.) in the semiconductor substrate 10 to define at least one active region 102. For example, the device isolation structure 101 may be a Deep Trench Isolation (DTI) structure, and may be fabricated by etching a trench in the semiconductor substrate 10 and then filling the trench with an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (k) dielectric material, other suitable materials, or a combination thereof. Thereafter, a Chemical Mechanical Polishing (CMP) process may be performed to remove the excess insulating material and planarize the upper surface of the device isolation structure 101.

Next, a first mask pattern layer 13 may be formed on the semiconductor substrate 10 by a conventional deposition (e.g., Chemical Vapor Deposition (CVD) process or spin-on coating (spin-on) process), photolithography, and etching (e.g., dry etching or wet etching). Thereafter, the semiconductor substrate 10 is etched by using the first mask pattern layer 13 as an etching mask to form two adjacent first trenches 103 in the semiconductor substrate 10 of the active region 102. In some embodiments, the depth of the first trench 103 is less than the depth of the device isolation structure 101.

Thereafter, a gate stack structure 11 is formed in each first trench 103. The top of the gate stack structure 11 is lower than the top of the first trench 103. For example, a gate dielectric layer 112 is formed in each first trench 103. The gate dielectric layer 112 may comprise titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (k) dielectric material, other suitable materials, or combinations thereof. Furthermore, the gate dielectric layer 112 may be formed by a CVD process or a thermal oxidation process. After the gate dielectric layer 112 is formed, a gate metal layer 111, such as tungsten (Wu), may be formed in each first trench 103. The gate metal layer 111 may be formed by a Physical Vapor Deposition (PVD) process, a CVD process, or other suitable processes. After the gate metal layer 111 is formed, the gate metal layer 111 and the gate dielectric layer 112 may be sequentially etched back, so that the gate metal layer 111 and the gate dielectric layer 112 do not completely fill the first trench 103. In the present embodiment, the gate dielectric layer 112 and the gate metal layer 111 form a gate stack structure 11.

Referring to fig. 2 and 3, the fabrication of the dielectric layer 14 is illustrated. As shown in fig. 2, a dielectric layer 14 is formed on the first mask pattern layer 13 and filled in the first trench 103 above the gate stack structure 11. In some embodiments, dielectric layer 14 may be comprised of silicon nitride or other suitable insulating material. Furthermore, the dielectric layer 14 may be formed by a CVD process or a spin-on process.

Next, a dielectric layer 14 is filled in the first trench 103 on the first mask pattern layer 13 and above the gate stack structure 11, specifically, a Chemical Mechanical Polishing (CMP) process is used to remove a portion of the dielectric layer 14 covering the first mask pattern layer 13, and a portion of the dielectric layer 14 in the first trench 103 is remained to form the dielectric layer 14.

Next, referring to fig. 4, a second Mask pattern layer (Mask)200 is formed on the first Mask pattern layer 13, and then dry etching is performed using an oxide, in this embodiment, a high selective etchant sin (high selective etchto sin) is used to remove the second Mask pattern layer 200 to cover a portion between the two first trenches 103.

Then, referring to fig. 5, the first mask pattern layer 13 between the first trenches 103 is removed to form openings, and sidewalls 300 are respectively formed on opposite sidewalls of the openings by a deposition process using an oxide

(space formation), and then the second mask pattern layer 200 on the first mask pattern layer 13 is removed using an Etch back (Etch back) process.

Then, referring to fig. 6, a second trench is formed by self-aligned etching using the sidewall spacers 300 as masks to form the second trench 104.

Next, referring to fig. 7, the trench isolation structure 12 having an air gap is filled in the second trench 104 by a deposition process using an oxide, and a sacrificial layer 400 is formed on the upper surface of the first mask pattern layer 13, specifically, in the present embodiment, SiH is used₄+O₂Or SiH₄+N₂O is realized by controlling step coverage (step coverage control).

Then, referring to fig. 8, an Etch back (Etch back) is performed using an oxide to remove the sacrificial layer 400 on the upper surface of the first mask pattern layer 13, and then sin (sin dep) is deposited to form the dielectric layer 14.

Next, referring to fig. 9, a third Mask pattern layer 500(Mask) is formed on the dielectric layer 14, and then dry etching is performed using oxide, wherein the third Mask pattern layer 500 has an opening above the semiconductor substrate 10 between the gate stack structures 11, and then the dielectric layer 14 under the opening is removed by an etching process to transfer the opening pattern of the third Mask pattern layer 500 into the dielectric layer 14 to form a Mask pattern layer having an opening. The opening exposes the dielectric layer 14 above between the gate stack structures 11 and contacts the trench isolation structure 12.

Then, referring to fig. 10, a bit line contact 15 is formed on the sidewall and the bottom of the opening by a polysilicon deposition process, and then the third mask pattern layer 500 is removed by etching back.

In some embodiments, dielectric layer 14 is comprised of silicon nitride.

Thereafter, a capacitor contact electrode (not shown) and a capacitor element (not shown) may be sequentially formed in and/or over the structure of fig. 10 by a conventional fabrication process to complete the fabrication of the semiconductor structure 100.

The semiconductor structure 100 prepared by the preparation method in this embodiment may be a DRAM, a Flash, and a Logic, and may be used in a chip.

According to the above embodiments, since the trench isolation structure is disposed between the adjacent word lines, when a row of word lines in the memory matrix can block noise or interference from the adjacent row of word lines through the trench isolation structure, the row interference effect can be prevented or reduced. Moreover, an air gap is formed in the trench isolation structure, and the air gap can reduce the dielectric constant of the trench isolation structure due to the fact that the dielectric constant of the air is small, so that the coupling effect of adjacent word lines is reduced, the row hammering effect between adjacent active regions is reduced, and the reliability of a semiconductor device is improved.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A semiconductor structure, comprising:

the gate stack structure is filled at the lower part of the first groove;

2. The semiconductor structure of claim 1, wherein an upper portion of the first trench is filled with a dielectric layer.

3. The semiconductor structure of claim 1, wherein a depth of the second trench is greater than a depth of the first trench.

4. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a device isolation structure having a depth greater than a depth of the second trench.

5. The semiconductor structure of claim 1, wherein an upper surface of the trench isolation structure is higher than an upper surface of the gate stack structure.

6. The semiconductor structure of claim 1, wherein the gate stack structure is a word line.

7. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a bit line contact over the second trench.

8. A method for fabricating a semiconductor structure, comprising:

forming two adjacent first trenches in a semiconductor substrate;

forming a gate stack structure at the lower part of the first trench;

9. The method of claim 8, wherein the step of forming two adjacent first trenches comprises: depositing a first mask pattern layer in an active area on a semiconductor substrate, and etching the semiconductor substrate by using the first mask pattern layer as an etching mask.

10. The method of claim 9, wherein the step of forming the second trench comprises: filling a dielectric layer in a first groove on the first mask pattern layer and above the gate laminated structure;

removing the first mask pattern layer between the first grooves to form openings;

forming a side wall of the dielectric layer in the opening;

and forming a second groove by self-aligned etching by taking the side wall as a mask.

11. The method for fabricating a semiconductor structure according to claim 10, further comprising the following steps after the second trench deposition for forming the trench isolation structure with air gaps:

depositing a sacrificial layer on the upper surface of the first mask pattern layer;

removing the sacrificial layer on the upper surface of the first mask pattern layer, and depositing a dielectric layer;

depositing a third mask pattern layer on the dielectric layer, and etching an opening between the third mask pattern layer and the trench isolation structure, wherein the opening extends to the dielectric layer above the word lines;

and depositing and forming a bit line contact part on the side wall and the bottom of the opening, and then etching back to remove the third mask pattern layer.

12. The method for manufacturing a semiconductor structure according to claim 8, wherein the gate stack structure comprises a gate dielectric layer and a gate metal layer, and the step of forming the gate stack structure in the lower portion of the first trench comprises the following steps:

sequentially depositing a gate dielectric layer and a gate metal layer in the first groove;

and sequentially etching back the gate metal layer and the gate dielectric layer to ensure that the gate metal layer and the gate dielectric layer do not completely fill the first groove.

13. The method for fabricating a semiconductor structure according to claim 8, wherein the reaction conditions for depositing the trench isolation structure with air gaps in the second trench are as follows:

the reaction gas is selected from SiH₄+O₂Or SiH₄+N₂And O, and is realized by controlling the step coverage rate.

14. The method of claim 11, wherein the step of forming the bit line contact comprises: bit line contacts are formed on sidewalls and bottom of the openings by a polysilicon deposition process.