CN114995565B

CN114995565B - Short-circuit protection method, circuit and bus driver

Info

Publication number: CN114995565B
Application number: CN202210540904.8A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shenzhen Nanyun Microelectronics Co ltd
Current assignee: Shenzhen Nanyun Microelectronics Co ltd
Priority date: 2022-05-17
Filing date: 2022-05-17
Publication date: 2024-02-09
Anticipated expiration: 2042-05-17
Also published as: CN114995565A

Abstract

The invention discloses a short-circuit protection method, a circuit and a bus driver, wherein the short-circuit protection method comprises the following steps: judging whether the upper branch is conducted or not; when the judgment result is that the upper branch is conducted, the following steps are further executed: comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result; comparing the output voltage with a first loading threshold voltage to obtain a first loading comparison result; and controlling the current flowing in the upper branch according to the first short circuit comparison result and the first load comparison result, wherein when the upper branch is in heavy load or short circuit, the current flowing in the upper branch is determined by different injected currents respectively. The invention can decouple the mutual restriction relation between the internal resistance of the switching tube and the short-circuit current in the driving circuit and improve the amplitude of the differential driving voltage output by the circuit node on the bus.

Description

Short-circuit protection method, circuit and bus driver

Technical Field

The present invention relates to the field of bus drivers, and in particular, to a short-circuit protection method and circuit for a bus driver, and a bus driver.

Background

Interface devices for standard data exchange, such as RS485, RS232, CAN and other interface chips, are designed to not only conform to the specification of the electrical characteristic standard of the corresponding communication protocol, but also have to be able to resist various risks from the bus, especially the bus driver thereof, not only considering the situation when the bus driver is not powered on, but also considering the situation that the output port of the bus driver may be in a conducting or high-resistance state when the bus driver is powered on, whether the bus driver CAN exit from the current state, and whether the signal paths between the power rail and the bus driver and the bus CAN be opened or closed, so as to ensure that the paths of current flowing caused by risks are controlled and ensure that the bus driver is not damaged. In addition, the bus driver must also be able to withstand overvoltage events that may occur in certain circumstances.

FIG. 1 is a schematic diagram of a conventional circuit of a prior art bus driver, in which only the driver stage portion relevant to the present invention is shown, including an upper leg, a lower leg, a power port VCC, a ground port GND, and an output port OUT, one end of the upper leg being used as a power port for connecting to a power rail, the other end of the upper leg being connected to one end of the lower leg as an output port for outputting the output voltage of the bus driver, and the other end of the lower leg being used as a ground port for grounding; each branch circuit comprises a switch unit and a backflow preventing unit. The diodes DP and DN in fig. 1 are anti-backflow units of the upper branch and the lower branch, respectively, which may be conventional diodes or diodes configured based on different connection modes from other semiconductor devices for lower voltage drop in the forward conduction condition; the PMOS transistor MP1 and the NMOS transistor N1 are switching units of an upper branch and a lower branch, respectively, and when the actual chip is designed, the switching transistors in each branch may be designed as a plurality of switching transistors of the same type connected in parallel, for example, the MOS transistor MP1 is designed as two PMOS transistors connected in parallel, and the MOS transistor MN1 is designed as two NMOS transistors connected in parallel.

Fig. 2 is a schematic diagram of an application of the bus driver shown in fig. 1 to a bus, wherein the bus driver includes two buses, at least one circuit node, the circuit node is connected to a point a with one of the buses and to a point B with the other bus, the circuit node (a, B) is configured with two bus drivers shown in fig. 1, an output port of a first bus driver is connected to a point a, and an output port of a second bus driver is connected to a point B, and at the same time, only one of (1) and (2) paths operates, so that the nodes (a, B) output a differential driving voltage, and thus only one branch of the bus driver in fig. 1 operates.

The protection strategy of a conventional bus driver in case of output overload or output port short circuit is generally designed as follows: when the output voltage of the output port is at a high level, namely the upper branch P switch tube is turned on, the lower branch N switch tube is turned off, and when the output voltage of the output port is too low and is lower than an upper branch short circuit threshold value due to overload or short circuit, a control signal turns off most of the P switch tubes connected in parallel in multiple tubes, so that the current drawn by the output port from a power rail is limited; on the contrary, when the output voltage of the output port is low level, and the output voltage of the output port is too high and is higher than the short-circuit threshold of the lower branch circuit due to overload or short circuit, the control signal turns off most of the N switch tubes connected in parallel with the multiple tubes, so that the current poured into the ground from the output port is limited, and the short-circuit protection effect on the bus driver is achieved. However, this approach has the following disadvantages:

(1) In order to ensure the amplitude of the differential driving voltage output by the nodes (A, B), the internal resistance of the switch tube is generally designed to be as small as possible during the chip design. However, before the voltage of the output port reaches the corresponding short-circuit threshold value point, the corresponding switching tube enters a saturation region, the smaller the internal resistance is, the larger the saturation current is, and the saturation current flows from the power rail to the output port through the upper branch circuit or flows from the output port to the ground through the lower branch circuit, so that the temperature rise of the bus driver is obvious, and the reliability is greatly reduced;

(2) When the bus driver is in a short circuit state, the short circuit recovery point is hard to reach due to the fact that the number of the switching tubes of the driving stage is small and the internal resistance is large, for example: when the internal resistance of the switching tube in the short circuit state is 3 times of that in the normal state, the current required to flow through the switching tube is required to be reduced to 1/3 of that in the normal state when the short circuit state is recovered, the output voltage of the output port can be recovered to the threshold point, and most of the switching tubes are opened again.

For the application of the schematic diagram of fig. 2, the output voltages of the output ports of the bus driver comprise: an output voltage VA of the first bus driver output port and an output voltage VB of the second bus driver output port; the common mode level of the bus driver output refers to: half of the sum of the output voltage of the first bus driver output port and the output voltage of the second bus driver output port, i.e., (va+vb)/2; the differential drive voltages output by nodes (a, B) refer to: the difference between the output voltage of the first bus driver output port and the output voltage of the second bus driver output port, i.e. (VA-VB).

The above-mentioned drawbacks limit the internal resistance of the switching tube not to be too small, in fact limiting the load carrying capacity of the bus driver.

Disclosure of Invention

In view of the above, the present invention provides a driving short-circuit protection method and a driving short-circuit protection method that at least partially solves one of the technical problems existing in the prior art.

As a first aspect of the present invention, short-circuit protection method embodiments are provided as follows:

the short circuit protection method is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switching tube in the upper branch is a PMOS tube, a switching tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is conducted, the short circuit protection method comprises the following steps:

judging whether the upper branch circuit is conducted or not;

when the judgment result is that the upper branch is conducted, the following steps are further executed:

comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with a first loading threshold voltage to obtain a first loading comparison result;

And controlling the current flowing in the upper branch according to the first short circuit comparison result and the first load comparison result, wherein control logic is as follows:

when the output voltage is less than or equal to the first short-circuit threshold voltage, the current flowing in the upper branch is determined by a first preset current injected into the upper branch;

when the first short-circuit threshold voltage is less than the output voltage and less than or equal to the first load threshold voltage, the current flowing in the upper branch is determined by a second preset current injected into the upper branch;

when the first load threshold voltage is less than the output voltage and less than or equal to the power rail voltage, the current flowing in the upper branch circuit is determined by the driving load of the bus driver;

the first preset current is less than the second preset current.

Further, whether the upper branch is conducted or not is judged according to the high or low of the switch tube grid driving signal in the upper branch.

Judging whether the lower branch circuit is conducted or not;

when the judgment result is that the lower branch circuit is conducted, the following steps are further executed:

comparing the output voltage of the output port of the bus driver with a second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with a second load threshold voltage to obtain a second load comparison result;

and controlling the current flowing in the lower branch according to the second short circuit comparison result and the second load comparison result, wherein the control logic is as follows:

when the output voltage is more than or equal to 0 and less than or equal to the second load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

when the second load threshold voltage is less than the output voltage and less than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

when the second short-circuit threshold voltage is less than the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

the third preset current is greater than the fourth preset current.

Further, whether the lower branch circuit is conducted or not is judged according to the high and low of the switch tube grid driving signal in the lower branch circuit.

judging whether the upper branch circuit is conducted or not;

judging whether the lower branch circuit is conducted or not;

The first preset current is less than the second preset current; the third preset current is greater than the fourth preset current.

Further, judging whether the upper branch is conducted or not according to the height of a switch tube grid driving signal in the upper branch; and judging whether the lower branch circuit is conducted or not according to the high or low of the switch tube grid driving signal in the lower branch circuit.

As a second aspect of the present invention, a short-circuit protection circuit is provided as follows:

the short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switching tube in the upper branch is a PMOS tube, a switching tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short-circuit protection circuit comprises a first short-circuit protection unit;

the first short-circuit protection unit includes:

a first judging unit, configured to judge whether the upper leg is turned on;

the first execution unit is used for further executing the following actions when the judgment result of the first judgment unit is that the upper branch circuit is conducted:

the first preset current is less than the second preset current.

Further, the first judging unit judges whether the upper branch is conducted or not according to the high or low of the switch tube gate driving signal in the upper branch.

The utility model provides a short-circuit protection circuit, is applied to bus driver, bus driver includes upper arm and lower arm, the switching tube in the upper arm is the PMOS tube, the switching tube in the lower arm is the NMOS tube, when bus driver normally works, upper arm with only one of lower arm switches on, short-circuit protection circuit includes:

The positive phase input end of the first comparator is used for inputting the output voltage of the output port of the bus driver, and the negative phase input end of the first comparator is used for inputting the first short-circuit threshold voltage; the setting end of the first comparator is used for inputting a gate driving signal of a switching tube in the upper branch circuit to judge whether the upper branch circuit is conducted or not; when the grid driving signal of the switching tube in the upper branch circuit is at a high level, the output end of the first comparator is set at the high level; when the grid driving signal of the switching tube in the upper branch circuit is in a low level, the output end of the first comparator outputs the first short circuit comparison result;

the input end of the first delay unit is used for receiving the output end level of the first comparator, and when the output end level of the first comparator is high level, the first delay unit is used for shaping and transmitting the high level, and the output end of the first delay unit outputs corresponding high level; when the output end level of the first comparator is low level, the first delay unit is used for outputting the low level through the output end after the first delay time;

the control end of the first voltage control current unit is connected with the output end of the first delay unit, and when the control end of the first voltage control current unit receives a high level, the output end of the first voltage control current unit outputs a first constant current; when the control end of the first voltage control current unit receives a low level, the output end of the first voltage control current unit outputs a second constant current, and the first constant current is larger than the second constant current;

The first current proportion unit comprises a PMOS tube MP2 and a PMOS tube MP3, wherein the source electrode of the PMOS tube MP2 and the source electrode of the PMOS tube MP3 are connected together and then are used for being connected with a power rail, the drain electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP2 and the grid electrode of the PMOS tube MP3 are connected together and then are connected with the output end of the first voltage control current unit, and the drain electrode of the PMOS tube MP3 is used for being connected with the anode of the backflow prevention diode of the upper branch.

As a specific embodiment of the first delay unit, it includes: PMOS tube MP4, NMOS tube MN4, capacitor C1 and Schmidt inverter SMT1; the grid of the PMOS tube MP4 is connected with the grid of the NMOS tube MN4 and then used as the input end of the first delay unit, the source of the PMOS tube MP4 is used for being connected with the power rail, the drain of the PMOS tube MP4, the drain of the NMOS tube MN4, one end of the capacitor C1 and the input end of the Schmitt inverter SMT1 are connected together, the source of the NMOS tube MN4 and the other end of the capacitor C1 are connected together and then used for being grounded, and the output end of the Schmitt inverter SMT1 is used as the output end of the first delay unit.

As a specific embodiment of the first voltage-controlled current unit, it includes: a switching tube S1, a first reference current IP1 and a second reference current IP2; the control end of the switching tube S1 is used as the control end of the first voltage control current unit, one end of the switching tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage control current unit, the other end of the switching tube S1 is connected with one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

The short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switching tube in the upper branch is a PMOS tube, a switching tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short-circuit protection circuit comprises a second short-circuit protection unit;

the second short protection unit includes:

a second judging unit, configured to judge whether the lower leg is turned on;

And the second execution unit is used for further executing the following actions when the judgment result of the second judgment unit is that the lower branch circuit is conducted:

the third preset current is greater than the fourth preset current.

Further, the second judging unit judges whether the lower branch is conducted or not according to the high or low of the switch tube gate driving signal in the lower branch.

the positive phase input end of the second comparator is used for inputting a second short-circuit threshold voltage, and the negative phase input end of the second comparator is used for inputting the output voltage of the output port of the bus driver; the setting end of the second comparator is used for inputting a gate driving signal of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted or not; when the grid driving signal of the switching tube in the lower branch circuit is in a low level, the output end of the second comparator is set to be in a high level; when the grid driving signal of the switching tube in the upper branch circuit is at a high level, the output end of the second comparator outputs the second short circuit comparison result;

The input end of the second delay unit is used for receiving the output end level of the second comparator, and when the output end level of the second comparator is a high level, the second delay unit is used for shaping and transmitting the high level, and the output end of the second delay unit outputs a corresponding high level; when the output end level of the second comparator is low level, the second delay unit is used for outputting the low level through the output end after the second delay time;

the control end of the second voltage control current unit is connected with the output end of the second delay unit, and when the control end of the second voltage control current unit receives a high level, the output end of the second voltage control current unit outputs a third constant current; when the control end of the second voltage control current unit receives a low level, the output end of the second voltage control current unit outputs a fourth constant current, and the third constant current is larger than the fourth constant current;

the second current proportion unit comprises an NMOS tube MN2 and an NMOS tube MN3, wherein the source electrode of the NMOS tube MN2 and the source electrode of the NMOS tube MN3 are connected together and then are grounded, the drain electrode of the NMOS tube MN2, the grid electrode of the NMOS tube MN2 and the grid electrode of the NMOS tube MN3 are connected together and then are connected with the output end of the second voltage control current unit, and the drain electrode of the NMOS tube MN3 is used for being connected with the source electrode of the NMOS tube of the lower branch.

As a specific embodiment of the second delay unit, it includes: PMOS tube MP5, NMOS tube MN5, capacitor C2 and Schmidt inverter SMT2; the grid electrode of the PMOS tube MP5 and the grid electrode of the NMOS tube MN5 are connected together and then serve as the input end of the second delay unit, the source electrode of the PMOS tube MP5 is used for being connected with a power rail, the drain electrode of the PMOS tube MP5, the drain electrode of the NMOS tube MN5, one end of the capacitor C2 and the input end of the Schmitt inverter SMT2 are connected together, the source electrode of the NMOS tube MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output end of the Schmitt inverter SMT2 serves as the output end of the second delay unit.

As a specific embodiment of the second voltage-controlled current unit, it includes: a switching tube S2, a third reference current IN1 and a fourth reference current IN2; the control end of the switching tube S2 is used as the control end of the second voltage control current unit, one end of the switching tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage control current unit, the other end of the switching tube S2 is connected with one end of the third reference current IN1, the other end of the third reference current IN1 is used for inputting a third reference current signal, and the other end of the fourth reference current IN2 is used for inputting a fourth reference current signal.

The short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switching tube in the upper branch is a PMOS tube, a switching tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short-circuit protection circuit comprises a first short-circuit protection unit and a second short-circuit protection unit;

the first short-circuit protection unit includes:

a first judging unit, configured to judge whether the upper leg is turned on;

the first preset current is less than the second preset current;

the second short protection unit includes:

a second judging unit, configured to judge whether the lower leg is turned on;

the third preset current is greater than the fourth preset current.

Further, the first judging unit judges whether the upper branch is conducted or not according to the high or low of a switch tube grid driving signal in the upper branch; the second judging unit judges whether the lower branch circuit is conducted or not according to the high or low of a switch tube grid driving signal in the lower branch circuit.

the first current proportion unit comprises a PMOS tube MP2 and a PMOS tube MP3, wherein the source electrode of the PMOS tube MP2 and the source electrode of the PMOS tube MP3 are connected together and then are used for being connected with a power rail, the drain electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP2 and the grid electrode of the PMOS tube MP3 are connected together and then are connected with the output end of the first voltage control current unit, and the drain electrode of the PMOS tube MP3 is used for being connected with the anode of the backflow prevention diode of the upper branch;

The positive phase input end of the second comparator is used for inputting a second short-circuit threshold voltage, and the negative phase input end of the second comparator is used for inputting the output voltage; the setting end of the second comparator is used for inputting a gate driving signal of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted or not; when the grid driving signal of the switching tube in the lower branch circuit is in a low level, the output end of the second comparator is set to be in a high level; when the grid driving signal of the switching tube in the upper branch circuit is at a high level, the output end of the second comparator outputs the second short circuit comparison result;

As a specific embodiment of the second delay unit, it includes: PMOS tube MP5, NMOS tube MN5, capacitor C2 and Schmidt inverter SMT2; the grid electrode of the PMOS tube MP5 and the grid electrode of the NMOS tube MN5 are connected together and then serve as the input end of the second delay unit, the source electrode of the PMOS tube MP5 is used for being connected with the power rail, the drain electrode of the PMOS tube MP5, the drain electrode of the NMOS tube MN5, one end of the capacitor C2 and the input end of the Schmitt inverter SMT2 are connected together, the source electrode of the NMOS tube MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output end of the Schmitt inverter SMT2 serves as the output end of the second delay unit.

As a third aspect of the present invention, bus driver embodiments are provided as follows:

a bus driver comprising a short circuit protection circuit as in any one of the above embodiments.

Meaning of terms:

current sinking: current is input from one end of the device, flows out from the other end of the device and flows to the power ground, and is similar to current sinking;

current source: current flows from one end of the power rail input device and from the other end of the device, and the current can be used as an input source signal of other circuits, so the current source is commonly called;

the embodiment of the invention at least comprises the following beneficial effects: when the bus driver is overloaded or shorted, the current flowing in the upper branch or the lower branch of the bus driver is reasonably limited by the reference currents with different magnitudes generated inside, so that the temperature rise of the bus driver can be controlled, the reliability of the bus driver is improved, and compared with the control strategy of reducing the number of the upper switch tubes or the lower switch tubes connected in parallel in the prior art, the decoupling between the differential output voltage and the short-circuit current of the bus driver is realized, so that the differential output voltage and the short-circuit current are not mutually limited, the defect that the current value of the corresponding branch is very low when the short-circuit recovery is required during electrification is avoided, and the load capacity of the bus driver is improved within a wide positive and negative common mode output voltage range.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

FIG. 1 is a schematic diagram of a conventional circuit of a prior art bus driver;

FIG. 2 is a schematic diagram of an application of the bus driver of FIG. 1 to a bus;

FIG. 3 is a flow chart of a short-circuit protection method according to a first embodiment of the present invention;

FIG. 4 is a flow chart of a short-circuit protection method according to a second embodiment of the present invention;

FIG. 5 is a flow chart of a short-circuit protection method according to a third embodiment of the present invention;

FIG. 6 is a schematic block diagram of a short-circuit protection circuit according to a fourth embodiment of the present invention;

FIG. 7 is a schematic diagram of a short-circuit protection circuit applied in a bus driver according to a fifth embodiment of the present invention;

FIG. 8 is a schematic diagram of a short-circuit protection circuit for use in a bus driver according to a fifth embodiment of the present invention, the schematic diagram providing specific circuitry for all of the cells of FIG. 7;

fig. 9 is a schematic block diagram of a short-circuit protection circuit according to a sixth embodiment of the present invention;

FIG. 10 is a schematic diagram of a short-circuit protection circuit applied in a bus driver according to a seventh embodiment of the present invention;

FIG. 11 is a schematic diagram of a short-circuit protection circuit for use in a bus driver according to a seventh embodiment of the present invention, the schematic diagram providing specific circuitry for all of the cells of FIG. 10;

FIG. 12 is a schematic block diagram of a short-circuit protection circuit according to an eighth embodiment of the present invention;

FIG. 13 is a schematic diagram of a short-circuit protection circuit applied in a bus driver according to a ninth embodiment of the present invention;

FIG. 14 is a schematic diagram of a short-circuit protection circuit for use in a bus driver according to a ninth embodiment of the present invention, the schematic diagram providing specific circuitry for all of the cells of FIG. 10;

fig. 15 is a waveform diagram of the short-circuit protection delay time design of the present invention.

Detailed Description

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in the specification, claims and drawings, when a step is described as being continued to another step, the step may be directly continued to the other step, or may be continued to the other step through a third step; when an element/unit is described as being "connected" to another element/unit, the element/unit may be "directly connected" to the other element/unit or "connected" to the other element/unit through a third element/unit.

Moreover, the drawings of the present disclosure are schematic representations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. The functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or micro-control devices.

First embodiment

Fig. 3 is a flowchart of a short-circuit protection method according to a first embodiment of the present invention, please refer to fig. 3, the short-circuit protection method of the present embodiment is applied to the bus driver in fig. 1 and 2, the bus driver includes an upper branch and a lower branch, a switch tube in the upper branch is a PMOS tube, a switch tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is turned on, the short-circuit protection method includes the following steps:

s101: judging whether the upper branch is conducted or not;

when the judgment result is that the upper branch circuit is conducted, the following steps are further executed:

S1021: comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result;

s1022: comparing the output voltage with a first loading threshold voltage to obtain a first loading comparison result;

s103: and controlling the current flowing in the upper branch circuit according to the first short circuit comparison result and the first load comparison result, wherein the control logic is as follows:

s1041: when the output voltage is less than or equal to the first short-circuit threshold voltage, the current flowing in the upper branch is determined by the first preset current injected into the upper branch;

s1042: when the first short-circuit threshold voltage is less than the output voltage and less than or equal to the first load threshold voltage, the current flowing in the upper branch is determined by the second preset current injected into the upper branch;

s1043: when the first load threshold voltage is less than the output voltage and less than or equal to the power rail voltage, the current flowing in the upper branch circuit is determined by the driving load of the bus driver;

the first preset current is less than the second preset current.

Wherein steps S1021 and S1022 are performed synchronously, steps S1041, S1042 and S1043 are one of the specific cases of step S103, that is, when step 103 is specifically performed, only one of steps S1041, S1042 and S1043 is performed.

The short-circuit protection method of the embodiment aims to improve the temperature rise problem and the carrying capacity problem of the upper branch, and is divided into the following three modes:

(1) Light load mode: at this time, corresponding to step S1043, that is, when the first load threshold voltage is less than the output voltage and less than the power rail voltage, the current flowing in the upper arm is determined by the driving load of the bus driver, in this mode, the load is smaller, the output voltage of the output port of the bus driver is larger, and nodes a and B can provide enough differential driving voltages, so that the current flowing in the upper arm is determined by the driving load of the bus driver;

(2) Heavy load mode: in step S1042, the first short-circuit threshold voltage is smaller than the output voltage and smaller than the first load threshold voltage, and the current flowing in the upper arm is determined by the second preset current injected into the upper arm, in this mode, the load is larger, the output voltage of the output port of the bus driver is reduced, the nodes a and B are not capable of providing enough differential driving voltages, and in this embodiment, the second preset current is injected into the upper arm, so that the current flowing in the upper arm is determined by the second preset current injected, which not only ensures that the driving stage of the bus driver has enough capability of driving resistive load and capacitive load, but also limits the current of the upper arm of the driving stage within a controllable range;

(3) Short circuit mode: at this time, corresponding to step S1041, that is, the output voltage is less than or equal to the first short-circuit threshold voltage, at this time, the current flowing in the upper arm is determined by the first preset current injected into the upper arm, in this mode, the load is further increased, or the output port of the bus driver is abnormally shorted, so that the output voltage of the output port of the bus driver is lower.

From the above analysis, in this embodiment, when the upper branch circuit has heavy load or short circuit, the current flowing in the upper branch circuit is reasonably limited by the reference currents with different magnitudes generated in the upper branch circuit, so that not only can the temperature rise of the bus driver be controlled and the reliability of the bus driver be improved, but also the decoupling between the differential output voltage and the short circuit current of the bus driver is realized by reducing the control strategy of the number of the parallel upper switching tubes compared with the prior art, so that the two are not restricted, the defect that the current value of the upper branch circuit is required to be very low during the electrified short circuit recovery is avoided, and the load capacity of the bus driver is improved within the wide positive and negative common mode output voltage range.

Further, when step S101 is performed, it is determined whether the upper arm is turned on according to the level of the switching transistor gate driving signal in the upper arm.

Because the switching tube of the upper branch needs to be controlled to be turned on and off by the driving signal, when judging whether the upper branch is turned on or not, the embodiment judges whether the upper branch is turned on or not according to the height of the gate driving signal of the switching tube in the upper branch, thereby avoiding the need of adding additional detection steps.

Second embodiment

Fig. 4 is a flowchart of a short-circuit protection method according to a second embodiment of the present invention, please refer to fig. 4, the short-circuit protection method of the present embodiment is applied to the bus driver in fig. 1 and 2, the bus driver includes an upper branch and a lower branch, a switch tube in the upper branch is a PMOS tube, a switch tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is turned on, the short-circuit protection method includes the following steps:

s201: judging whether the lower branch is conducted or not;

s2021: comparing the output voltage of the output port of the bus driver with a second short-circuit threshold voltage to obtain a second short-circuit comparison result;

S2022: comparing the output voltage with a second load threshold voltage to obtain a second load comparison result;

s203: and controlling the current flowing in the lower branch circuit according to the second short circuit comparison result and the second load comparison result, wherein the control logic is as follows:

s2041: when the output voltage is more than or equal to 0 and less than or equal to the second load threshold voltage, the current flowing in the lower branch circuit is determined by the driving load of the bus driver;

s2042: when the second load threshold voltage is smaller than the output voltage and smaller than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by the third preset current injected into the lower branch;

s2043: when the second short-circuit threshold voltage is less than the output voltage, determining the current flowing in the lower branch by the fourth preset current injected into the lower branch;

the third preset current is greater than the fourth preset current.

Wherein steps S2021 and S2022 are performed synchronously, steps S2041, S2042 and S2043 are one of the specific cases of step S203, that is, when step 203 is specifically performed, only one of steps S2041, S2042 and S2043 is performed.

The short-circuit protection method of the embodiment aims to improve the temperature rise problem and the carrying capacity problem of the lower branch circuit, and is divided into the following three modes:

(1) Light load mode: at this time, corresponding to step S2041, that is, when the output voltage is equal to or less than 0 and equal to or less than the second load threshold voltage, the current flowing in the lower leg is determined by the driving load of the bus driver, in this mode, the load is smaller, the output voltage of the output port of the bus driver is smaller, and the nodes CAN-H and CAN-L CAN provide sufficient differential driving voltages, so that the current flowing in the lower leg is determined by the driving load of the bus driver;

(2) Heavy load mode: at this time, corresponding to step S2042, that is, when the second load threshold voltage is less than the output voltage and less than or equal to the second short circuit threshold voltage, the current flowing in the lower leg is determined by the third preset current injected into the lower leg, in this mode, the load is larger, the output voltage of the output port of the bus driver is increased, the nodes CAN-H and CAN-L are not capable of providing enough differential driving voltages, and in this embodiment, the third preset current is injected into the lower leg, so that the current flowing in the lower leg is determined by the third preset current injected, which not only ensures that the driving stage of the bus driver has enough capability of driving resistive load and capacitive load, but also limits the current of the lower leg of the driving stage within a controllable range;

(3) Short circuit mode: at this time, corresponding to step S2043, that is, when the second short-circuit threshold voltage is less than the output voltage, the current flowing in the lower leg is determined by the fourth preset current injected into the lower leg, in this mode, the load is further increased, or the output port of the bus driver is abnormally shorted, so that the output voltage of the output port of the bus driver is higher.

From the above analysis, in this embodiment, when the down leg is overloaded or shorted, the current flowing in the down leg is reasonably limited by the reference currents with different magnitudes generated in the down leg, so that not only can the temperature rise of the bus driver be controlled and the reliability of the bus driver be improved, but also the decoupling between the differential output voltage of the bus driver and the shorted current is realized by reducing the control strategy of the number of the switches connected in parallel compared with the prior art, so that the two are not restricted any more, thereby eliminating the defect that the current value of the down leg is very low when the short circuit is recovered during electrification, and improving the load carrying capacity of the bus driver in the wide positive and negative common mode output voltage range.

Further, in executing step S201, it is determined whether the lower arm is turned on according to the level of the switching transistor gate driving signal in the lower arm.

Because the switching tube of the lower branch needs to be controlled to be turned on and off by the driving signal, when judging whether the lower branch is turned on or not, the embodiment judges whether the lower branch is turned on or not according to the height of the gate driving signal of the switching tube in the lower branch, thereby avoiding the need of adding additional detection steps.

Third embodiment

Fig. 5 is a flowchart of a short-circuit protection method according to a third embodiment of the present invention, please refer to fig. 5, in which the method of the first embodiment and the method of the second embodiment are combined.

It is to be readily understood that the short-circuit protection method of the present embodiment aims to improve both the problem of the temperature rise and the problem of the carrying capacity of the upper arm and the lower arm, and in this embodiment, step S101 and step S201 are performed simultaneously, and since only one of the upper arm and the lower arm is turned on when the bus driver is operating normally, at the same time, only one of the step S101 and the step S201 has a "yes" judgment result, and the step having a "yes" judgment result is performed continuously. When the judgment result of the step S101 is yes, three working modes are included, and the three working modes are the same as those of the first embodiment, so that description is omitted; when the judgment result of step S201 is yes, three working modes are included, and the three working modes are the same as those of the second embodiment and are not described in detail.

In this embodiment, whether the upper branch circuit is overloaded or shorted, or the lower branch circuit is overloaded or shorted, the current flowing in the corresponding branch circuit is reasonably limited by the reference currents with different magnitudes generated inside, so that not only the temperature rise of the bus driver can be controlled and the reliability of the bus driver is improved, but also the decoupling between the differential output voltage and the shorted current of the bus driver is realized by reducing the control strategy of the number of the upper switch tubes or the lower switch tubes connected in parallel compared with the prior art, so that the two are not restricted by each other, the defect that the current value of the corresponding branch circuit is very low when the short circuit recovery is required during electrification is avoided, and the load capacity of the bus driver is improved within the wide positive and negative common mode output voltage range.

Fourth embodiment

Fig. 6 is a schematic block diagram of a short-circuit protection circuit according to a fourth embodiment of the present invention, referring to fig. 6, the short-circuit protection circuit of the present embodiment is applied to the bus driver in fig. 1 and 2, and the bus driver includes an upper leg and a lower leg; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first backflow preventing unit 105 is a diode DP; the grid driving signal of the PMOS tube MP1 is gate; the switch tube 206 in the lower branch is an NMOS tube MN1, the second anti-backflow unit 205 is a diode DN, and the gate driving signal of the NMOS tube MN1 is GateN; when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises a first short-circuit protection unit;

The first short-circuit protection unit includes:

a first judging unit for judging whether the upper branch is conducted;

when the output voltage is less than or equal to the first short-circuit threshold voltage, the current flowing in the upper branch is determined by the first preset current injected into the upper branch;

when the first short-circuit threshold voltage is less than the output voltage and less than or equal to the first load threshold voltage, the current flowing in the upper branch is determined by the second preset current injected into the upper branch;

the first preset current is less than the second preset current.

It is easy to understand that the short-circuit protection circuit of the present embodiment aims to improve the temperature rise problem and the load capacity problem of the upper arm, and when the judgment result of the first judgment unit is yes, the first execution unit includes three working modes, and the three working modes are the same as those of the first embodiment, so that the beneficial effects brought by the three working modes are the same, and are not repeated.

Further, the first judging unit judges whether the upper branch circuit is conducted or not according to the high or low of the switch tube gate driving signal in the upper branch circuit, so that the need of adding an additional detecting unit is avoided.

Fifth embodiment

Fig. 7 is a schematic diagram of a short-circuit protection circuit applied in a bus driver according to a fifth embodiment of the present invention, referring to fig. 7, the short-circuit protection circuit of the present embodiment is applied to the bus driver in fig. 1 and 2, and the bus driver includes an upper leg and a lower leg; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first backflow preventing unit 105 is a diode DP; the grid driving signal of the PMOS tube MP1 is gate; the switch tube 206 in the lower branch is an NMOS tube MN1, the second anti-backflow unit 205 is a diode DN, and the gate driving signal of the NMOS tube MN1 is GateN; when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises:

The first comparator 101, the positive phase input end of the first comparator 101 is used for connecting the output port OUT of the bus driver, the negative phase input end is used for inputting the first short-circuit threshold voltage Vthp; the set end of the first comparator 101 is used for inputting a gate driving signal gate of a switching tube in the upper branch circuit to judge whether the upper branch circuit is conducted or not; when the gate driving signal GateP of the switching transistor in the upper arm is at a high level, the output terminal of the first comparator 101 is set at a high level; when the gate driving signal gate of the switching tube in the upper branch is at a low level, the output end of the first comparator 101 outputs a first short circuit comparison result;

the input end of the first delay unit 102 is used for receiving the output end level of the first comparator 101, when the output end level of the first comparator 101 is high level, the first delay unit 102 is used for shaping and transmitting the high level, and the output end of the first delay unit 102 outputs corresponding high level; when the output terminal level of the first comparator 101 is a low level, the first delay unit 102 is configured to output the low level from the output terminal thereof after a first delay time;

the control end of the first voltage control current unit 103 is connected with the output end of the first delay unit 102, and when the control end of the first voltage control current unit 103 receives a high level, the output end of the first voltage control current unit 103 outputs a first constant current; when the control end of the first voltage control current unit 103 receives a low level, the output end of the first voltage control current unit 103 outputs a second constant current, and the first constant current is greater than the second constant current;

The first current proportion unit 104, the first current proportion unit 104 includes a PMOS transistor MP2 and a PMOS transistor MP3, the source of the PMOS transistor MP2 and the source of the PMOS transistor MP3 are connected together and then are used for connecting a power rail, the drain of the PMOS transistor MP2, the gate of the PMOS transistor MP2 and the gate of the PMOS transistor MP3 are connected together and then are connected with the output end of the first voltage control current unit 103, and the drain of the PMOS transistor MP3 is used for connecting the anode of the backflow preventing diode DP of the upper branch.

It should be noted that, the PMOS transistors MP2 and MP3 are low-voltage PMOS transistors, and the PMOS transistors MP2 and MP3 are 1: the aspect ratio of m (m is a proper natural number) forms the connection mode of the current mirror. In the case of an upper branch circuit conducting: when the PMOS tube MP3 works in the linear region, the current flowing through the PMOS tube MP3 is determined by the driving load; when the PMOS tube MP3 is in the saturation region, the current flowing through the PMOS tube MP3 is determined by the current value obtained by mirroring the PMOS tube MP3 from the PMOS tube MP 2.

Fig. 8 is a schematic diagram of a short-circuit protection circuit applied in a bus driver according to a fifth embodiment of the present invention, where the schematic diagram provides specific circuits for all the units in fig. 7, please refer to fig. 8:

wherein the first delay unit 102 includes: PMOS tube MP4, NMOS tube MN4, capacitor C1 and Schmidt inverter SMT1; the grid of the PMOS tube MP4 and the grid of the NMOS tube MN4 are connected together and then serve as the input end of the first delay unit 102, the source electrode of the PMOS tube MP4 is used for being connected with a power rail, the drain electrode of the PMOS tube MP4, the drain electrode of the NMOS tube MN4, one end of the capacitor C1 and the input end of the Schmitt inverter SMT1 are connected together, the source electrode of the NMOS tube MN4 and the other end of the capacitor C1 are connected together and then used for being grounded, and the output end of the Schmitt inverter SMT1 serves as the output end of the first delay unit 102.

Wherein the first voltage control current unit 103 includes: a switching tube S1, a first reference current IP1 and a second reference current IP2; the control end of the switching tube S1 is used as the control end of the first voltage control current unit 103, one end of the switching tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage control current unit 103, the other end of the switching tube S1 is connected with one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

It should be noted that, the current magnitudes of the first reference current IP1 and the second reference current IP2 may be selected according to the requirement of the bus driver driving capability during normal operation and the magnitude of the current limit value setting in the short circuit state, and the currents of the first reference current IP1 and the second reference current IP2 are provided by the reference current sink.

In this embodiment, the gate voltage of the PMOS transistor MP2 and the gate voltage VGP of the PMOS transistor MP3 are determined by the output current of the first voltage control current unit 103, the power rail voltage VCC is a fixed value, and the output voltage VOUT of the output port of the bus driver is a variable value.

The conditions of the PMOS tube MP2 and the PMOS tube MP3 working in the saturation region are |Vds| > |Vgs| -Vth|, wherein Vgs is the gate-source voltage of the MOS tube, vds is the drain-source voltage of the MOS tube, vth is the threshold voltage of the MOS tube, and all three are negative values.

The gate and drain of the PMOS tube MP2 are shorted as the input tube of the current mirror, and at this time |vds|= |vgs|, so that |vds| > |vgs| -vth| can be satisfied all the time, and the PMOS tube MP2 works in the saturation region all the time.

The PMOS tube MP2 is used as an output tube of the current mirror, the PMOS tube MP3 also works in a saturation region as a necessary condition for mirror current from the PMOS tube MP2, at the moment, (VCC-VDMP 3) > (VCC-VGP- |VthMP 3|) and VGP > VDMP3- |VthMP3| are obtained after simplifying the formula, wherein VDMP3 is the drain voltage of the PMOS tube MP3, vthMP3 is the threshold voltage thereof, VDSMP1|+VOUT because VDMP 3=VDP+| is the forward conduction voltage drop of the diode DP, VDSMP1 is the drain-source voltage drop of the PMOS tube MP1, and the formula VGP > issubstituted into the formula

From the above analysis, the inventive concept of the present embodiment is the same as that of the first embodiment and the fourth embodiment, and since the condition that VOUT is smaller than the threshold VGP-vdp— vdsmp1+|vthmp3| is required to be satisfied when the operating state of the PMOS transistor MP3 in the present embodiment is saturated from the linear region, the threshold may be regarded as the first load threshold voltage in the first embodiment and the fourth embodiment, so that the present embodiment utilizes the natural operating characteristic of the PMOS transistor MP3 to realize the function of comparing the output voltage VOUT with the first load threshold voltage, obtain the first load comparison result, and execute the function of the related action according to the first load comparison result.

The short-circuit protection circuit of the present embodiment aims to improve the temperature rise problem and the carrying capacity problem of the upper arm, and the working principle of the present embodiment will be analyzed with reference to the circuit of fig. 8. For convenience of explanation and understanding, the following analysis directly considers the threshold VGP-VDP- |vdsmp1|+|vthmp3| as VGP, and when the actual circuit design is performed, the effect that VGP-VDP- |vdsmp 1|+|vthmp3|=vgp can be achieved by designing the value of |vthmp3| -VDP- |vdsmp 1|. It is easy to understand that when no short-circuit protection measures are taken, as the load gradually increases, that is, the current flowing in the upper arm gradually increases, the bus driver in this embodiment will sequentially operate in the light load mode, the heavy load mode and the short-circuit mode, and the output voltage VOUT of the output port of the bus driver will gradually decrease.

Based on the design conditions of the above threshold values, the present embodiment includes the following three modes:

(1) Light load mode: the load is smaller, the output voltage VOUT of the output port of the bus driver is larger, when VGP is smaller than VOUT and smaller than VCC, the positive phase input end of the first comparator 101 is larger than the negative phase input end, the high level output by the first comparator 101 controls the switch tube S1 of the first voltage control current unit 103 to be closed through the first delay unit 102, so that the sum of the first reference current IP1 and the second reference current IP2 is selected to be provided for the input end of the first current proportion unit 104, but at this time, because VOUT is larger than VGP, the low-voltage PMOS tube MP3 in the first current proportion unit 103 is in a linear region and does not have the function of mirroring current from the PMOS tube MP2, at this time, the internal resistance of the PMOS tube MP3 is lower, the voltage drop of the loss between the source and the drain is smaller, and the current flowing through the driving upper branch is completely determined by the load of the driving output;

(2) Heavy load mode: as the driving output load increases, the output voltage of the output port of the bus driver decreases, when Vthp < VOUT less than or equal to VGP, the positive phase input end of the first comparator 101 is still greater than the negative phase input end, the first comparator 101 still outputs a high level, the high level controls the switch tube S1 of the first voltage control current unit 103 to be closed through the first delay unit 102, thereby still selecting the sum of the first reference current IP1 and the second reference current IP2 to be provided to the input end of the first current proportion unit 104, but at this time, because VOUT less than or equal to VGP, the low-voltage PMOS tube MP3 in the first current proportion unit 103 starts to enter a saturation region, and can mirror the reference current on the PMOS tube MP2, so the first current proportion unit 103 can limit the current value flowing through the driving upper branch circuit, and multiply the ratio value m between the low-voltage PMOS designed by the first current proportion unit 103, namely (IP 1+ip 2), thereby ensuring the capability of driving resistive load and capacitive load of the driving stage in the bus driver, and simultaneously limiting the current of the upper branch circuit within a controllable range;

(3) Short circuit mode: with further increase of the driving output load or abnormal short circuit of the port, VOUT is caused to be lower, when VOUT is less than or equal to Vthp, the first comparator 101 will output a low level to the first delay unit 102, the PMOS tube MP4 in the first delay unit 102 is turned on, the power rail charges the capacitor C1 through the PMOS tube MP4 until the voltage drop on the capacitor C1 reaches the inversion point of the schmitt inverter SMT1, that is, after a set delay time, the switching tube S1 in the first voltage control current unit 103 is controlled to be turned off by the output low level, only the second reference current IP2 is selected to be provided to the first current proportion unit 104, at this time VOUT is very low, the low voltage PMOS tube MP3 in the first current proportion unit 104 is in a saturation region and keeps a mirror image effect with the PMOS tube MP2, at this time, the first current proportion unit 104 limits the current value flowing through the upper branch to be the second reference current IP2 multiplied by the proportion value m between the low voltage PMOS designed by the first current proportion unit 104, that is IP2×m, so that the bus driver is caused to be limited in the low level under the short circuit state, and reliability of the bus driver is improved.

The inventive concept of this embodiment is the same as that of the first embodiment and the fourth embodiment, and when the upper branch is overloaded or shorted, the current flowing in the upper branch is reasonably limited by the reference currents (corresponding to the currents injected from the outside in the first embodiment and the fourth embodiment) with different magnitudes generated by the first voltage control current unit 103, so that the temperature rise of the bus driver can be controlled, the reliability of the bus driver is improved, and compared with the prior art, the decoupling between the differential output voltage and the shorted current of the bus driver is realized by reducing the control strategy of the number of the parallel upper switching tubes, so that the two are not mutually restricted, thereby eliminating the defect that the current value of the upper branch is very low when the electrified short circuit recovery is required, and improving the load carrying capacity of the bus driver in a wide positive and negative common mode output voltage range.

Sixth embodiment

Fig. 9 is a schematic diagram of a short-circuit protection circuit applied in a bus driver according to a sixth embodiment of the present invention, referring to fig. 9, the short-circuit protection circuit of the present embodiment is applied to the bus driver in fig. 1 and 2, and the bus driver includes an upper leg and a lower leg; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first backflow preventing unit 105 is a diode DP; the grid driving signal of the PMOS tube MP1 is gate; the switch tube 206 in the lower branch is an NMOS tube MN1, the second anti-backflow unit 205 is a diode DN, and the gate driving signal of the NMOS tube MN1 is GateN; when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short-circuit protection circuit is a second short-circuit protection unit;

the second short-circuit protection unit includes:

a second judging unit, configured to judge whether the lower leg is turned on;

And controlling the current flowing in the lower branch circuit according to the second short circuit comparison result and the second load comparison result, wherein the control logic is as follows:

when the output voltage is more than or equal to 0 and less than or equal to the second load threshold voltage, the current flowing in the lower branch circuit is determined by the driving load of the bus driver;

when the second load threshold voltage is smaller than the output voltage and smaller than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by the third preset current injected into the lower branch;

when the second short-circuit threshold voltage is less than the output voltage, determining the current flowing in the lower branch by the fourth preset current injected into the lower branch;

the third preset current is greater than the fourth preset current.

It is easy to understand that the short-circuit protection circuit of the present embodiment aims to improve the temperature rise problem and the load capacity problem of the lower arm, and when the judgment result of the second judgment unit is yes, the second execution unit includes three working modes, and the three working modes are the same as those of the second embodiment, so that the beneficial effects brought by the three working modes are the same, and are not repeated.

Further, the second judging unit judges whether the lower branch circuit is conducted or not according to the high or low of the switch tube gate driving signal in the lower branch circuit, so that the need of adding an additional detecting unit is avoided.

Seventh embodiment

Fig. 10 is a schematic diagram of a short-circuit protection circuit applied in a bus driver according to a seventh embodiment of the present invention, referring to fig. 7, the short-circuit protection circuit of the present embodiment is applied to the bus driver in fig. 1 and 2, and the bus driver includes an upper leg and a lower leg; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first backflow preventing unit 105 is a diode DP; the grid driving signal of the PMOS tube MP1 is gate; the switch tube 206 in the lower branch is an NMOS tube MN1, the second anti-backflow unit 205 is a diode DN, and the gate driving signal of the NMOS tube MN1 is GateN; when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises:

the second comparator 201, the positive phase input end of the second comparator 201 is used for inputting the second short-circuit threshold voltage Vthn, the negative phase input end is used for inputting the output voltage of the output port of the bus driver; the set end of the second comparator 201 is used for inputting a gate driving signal GateN of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted or not; when the gate driving signal GateN of the switching transistor in the lower arm is at a low level, the output terminal of the second comparator 201 is set at a high level; when the gate driving signal GateN of the switching tube in the upper branch is at a high level, the output end of the second comparator 201 outputs the second short circuit comparison result;

The second delay unit 202, the input end of the second delay unit 202 is used for receiving the output end level of the second comparator 201, when the output end level of the second comparator 201 is high level, the second delay unit 202 is used for shaping and transmitting the high level, and the output end outputs corresponding high level; when the output terminal level of the second comparator 201 is a low level, the second delay unit 202 is configured to output the low level from the output terminal thereof after the second delay time elapses;

the control end of the second voltage control current unit 203 is connected to the output end of the second delay unit 202, and when the control end of the second voltage control current unit 203 receives a high level, the output end of the second voltage control current unit 203 outputs a third constant current; when the control end of the second voltage control current unit 203 receives a low level, the output end of the second voltage control current unit 203 outputs a fourth constant current, and the third constant current is greater than the fourth constant current;

the second current proportion unit 204, the second current proportion unit 204 includes an NMOS tube MN2 and an NMOS tube MN3, the source of the NMOS tube MN2 and the source of the NMOS tube MN3 are connected together and then used for grounding, the drain of the NMOS tube MN2, the gate of the NMOS tube MN2 and the gate of the NMOS tube MN3 are connected together and then connected to the output end of the second voltage control current unit 203, and the drain of the NMOS tube MN3 is used for connecting the source of the NMOS tube of the lower branch.

It should be noted that, the NMOS transistor MN2 and the NMOS transistor are low-voltage NMOS transistors, and the NMOS transistor MN2 and the NMOS transistor are 1: the aspect ratio of n (n is a suitable natural number) constitutes the connection mode of the current mirror. In the case of the down leg being conductive: when the NMOS tube MN3 is in a linear region for operation, the current flowing through the NMOS tube MN3 is determined by a driving load; when the NMOS transistor MN3 is in the saturation region, the current flowing through the NMOS transistor MN3 is determined by the current value mirrored by the NMOS transistor MN3 from the NMOS transistor MN 2.

Fig. 11 is a schematic diagram of a short-circuit protection circuit applied in a bus driver according to a fifth embodiment of the present invention, where the schematic diagram provides specific circuits for all the units in fig. 10, please refer to fig. 11:

wherein the second delay unit 202 comprises: PMOS tube MP5, NMOS tube MN5, capacitor C2 and Schmidt inverter SMT2; the grid electrode of the PMOS tube MP5 and the grid electrode of the NMOS tube MN5 are connected together and then serve as the input end of the second delay unit, the source electrode of the PMOS tube MP5 is used for being connected with a power rail, the drain electrode of the PMOS tube MP5, the drain electrode of the NMOS tube MN5, one end of a capacitor C2 and the input end of a Schmitt inverter SMT2 are connected together, the source electrode of the NMOS tube MN5 and the other end of the capacitor C2 are connected together and then used for being grounded, and the output end of the Schmitt inverter SMT2 serves as the output end of the second delay unit 202.

Wherein the second voltage control current unit includes: a switching tube S2, a third reference current IN1 and a fourth reference current IN2; the control end of the switching tube S2 is used as the control end of the second voltage control current unit 203, one end of the switching tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage control current unit 203, the other end of the switching tube S2 is connected with one end of the third reference current IN1, the other end of the third reference current IN1 is used for inputting a third reference current signal, and the other end of the fourth reference current IN2 is used for inputting a fourth reference current signal.

It should be noted that, the current magnitudes of the third reference current IN1 and the fourth reference current IN2 may be selected according to the requirement of the bus driver driving capability during normal operation and the magnitude of the current limit value setting IN the short circuit state, and the currents of the third reference current IN1 and the fourth reference current IN2 are provided downward by the reference current sources.

In this embodiment, the gate voltage of the NMOS transistor MN2 and the gate voltage VGN of the NMOS transistor MN3 are determined by the output current of the second voltage control current unit 203, the power rail voltage VCC is a fixed value, and the output voltage VOUT of the output port of the bus driver is a variable value.

The conditions of the NMOS tube MN2 and the NMOS tube MN3 working in the saturation region are Vds & gtVgs-Vth, wherein Vgs is the gate-source voltage of the MOS tube, vds is the drain-source voltage of the MOS tube, vth is the threshold voltage of the MOS tube, and the Vds, the Vth and the Vth are positive values.

The gate and drain of the NMOS MN2 are shorted, and vds=vgs at this time, so Vds > Vgs-Vth can be always satisfied, and the NMOS MN2 always operates in the saturation region.

The NMOS transistor MN2 is used as an output tube of the current mirror, the NMOS transistor MN3 also works in the saturation region as a necessary condition for mirroring current from the NMOS transistor MN2, and at this time, VDMN3 > VGN-VthMN3, wherein VDMP3 is the drain voltage of the NMOS transistor MN3, vthMN3 is the threshold voltage of the NMOS transistor MN3, since vdmn3=vout-VDN-VDSMN 1, wherein VDN is the forward conduction voltage drop of the diode DN, VDSMN1 is the drain-source voltage drop of the NMOS transistor MN1, and the substitution formula VDMN3 > VGN-VthMN3 has: VOUT >

The VGN+VDP+VDSMN1-VthMN3, namely when VOUT > VGN+VDP+VDSMN1-VthMN3, the NMOS tube MN3 works in the saturation region, VGN, VDP, VDSMN1 and VthMN3 are fixed values, so that the threshold value that the working state of the NMOS tube MN3 enters the saturation region from the linear region can be designed by designing the values of VGN, VDP, VDSMN and VthMN3, and the threshold value is VGN+VDP+VDSMN1-VthMN3.

As can be seen from the above analysis, the inventive concept of the present embodiment is the same as that of the second embodiment and the fifth embodiment, and since the condition that VOUT is greater than the above threshold vgn+vdp+vdsmn1-vthmn3 is required to be satisfied when the operating state of the NMOS transistor MN3 in the present embodiment is saturated from the linear region, the threshold can be regarded as the second load threshold voltage in the second embodiment and the fifth embodiment, so that the present embodiment utilizes the natural operating characteristics of the NMOS transistor MN3 to realize the function of comparing the output voltage VOUT with the second load threshold voltage, obtain the second load comparison result, and execute the function of the related action according to the second load comparison result.

The short-circuit protection circuit of the present embodiment aims to improve the temperature rise problem and the carrying capacity problem of the lower arm, and the working principle of the present embodiment will be analyzed with reference to the circuit of fig. 11. For ease of explanation, the following analysis regards threshold vgn+vdp+vdsmn1-vthmn3 as VGN directly, and designing vdp+vdsmn1-vthmn3 to zero can also achieve the effect of vgn+vdp+vdsmn1-vthmn3=vgn when the actual circuit design is in progress. It is easy to understand that when no short-circuit protection measures are taken, as the load gradually increases, that is, the current flowing in the lower branch gradually increases, the bus driver in this embodiment will sequentially operate in the light load mode, the heavy load mode and the short-circuit mode, and the output voltage VOUT of the output port of the bus driver will gradually increase.

The short-circuit protection circuit of this embodiment aims to improve the temperature rise problem and the carrying capacity problem of the lower arm, and is analyzed in combination with the circuit of fig. 11, and includes the following three modes:

(1) Light load mode: the load is smaller, the output voltage VOUT of the output port of the bus driver is smaller, when VOUT is not less than 0 and not more than VGN, the negative phase input end of the second comparator 201 is smaller than Yu Zhengxiang input end, the high level output by the second comparator 201 controls the switch tube S2 of the second voltage control current unit 203 to be closed through the second delay unit 202, so that the sum of the third reference current IP3 and the fourth reference current IN2 is selected to be provided for the input end of the second current proportion unit 203, but at the moment, because VOUT is not more than VGN, the low-voltage NMOS tube MN3 IN the second current proportion unit 203 is IN a linear region, the function of mirroring current from the NMOS tube MN2 is not provided, at the moment, the internal resistance of the NMOS tube MN3 is lower, the voltage drop of the loss between the source and the drain is smaller, and the current flowing through the lower branch is completely determined by the load of the driving output;

(2) Heavy load mode: as the driving output load increases, the output voltage of the output port of the bus driver increases, when VGN < VOUT < Vthn, the negative phase input end of the second comparator 201 is still smaller than the positive phase input end, the second comparator 201 still outputs a high level, and the high level controls the switch tube S2 of the second voltage control current unit 203 to be closed through the second delay unit 202, so that the sum of the third reference current IP3 and the fourth reference current IN2 is still selected and provided to the input end of the second current proportion unit 203, but at this time, because VOUT > VGN, the low-voltage NMOS MN3 IN the second current proportion unit enters a saturation region, and can mirror the reference current on the NMOS MN2, so that the second current proportion unit 203 can limit the current value flowing through the lower branch circuit, and multiply the ratio value n between the low-voltage PMOS designed by the second current proportion unit 203, namely (in1+in2), so as to ensure that the driving stage IN the bus driver has the capability of driving resistive load and capacitive load, and at the same time, the current of the lower branch circuit of the driving stage is limited IN a controllable range;

(3) Short circuit mode: with further increase of the driving output load or abnormal short circuit of the port, VOUT is higher, VOUT > Vthn, the second comparator 201 outputs a low level to the second delay unit 202, the PMOS tube MP5 IN the second delay unit 202 is turned on, the power rail charges the capacitor C2 through the PMOS tube MP5 until the voltage drop on the capacitor C2 reaches the inversion point of the schmitt inverter SMT2, that is, after a set delay time, the switching tube S2 IN the second voltage control current unit 203 is turned off, only the fourth reference current IN2 is selected to be provided to the second current proportion unit 204, VOUT is very high, VOUT is kept larger than VGN, the low-voltage NMOS tube MN3 IN the second current proportion unit 203 is IN a saturation region, and the current mirror formed by the NMOS tube MN2 is kept IN mirror image, at this moment, the second current proportion unit 203 limits the current value flowing through the lower branch, that is the fourth reference current IN2 is multiplied by the proportion value n between the low-voltage NMOS designed by the second current proportion unit, that is 2×n, so that the chip is promoted to be limited by the low-level driver under the short circuit state.

The inventive concept of this embodiment is the same as that of the second embodiment and the sixth embodiment, and when the down leg is overloaded or shorted, the current flowing in the down leg is reasonably limited by the reference currents (corresponding to the currents injected from the outside in the second embodiment and the sixth embodiment) with different magnitudes generated by the second voltage control current unit 203, so that the temperature rise of the bus driver can be controlled, the reliability of the bus driver is improved, and compared with the prior art, the decoupling between the differential output voltage and the shorted current of the bus driver is realized by reducing the control strategy of the number of the switches connected in parallel, so that the two are not restricted by each other, thereby eliminating the defect that the current value of the down leg is very low when the short circuit recovery requires the electrification, and improving the load carrying capacity of the bus driver in a wide positive and negative common mode output voltage range.

Eighth embodiment

Fig. 12 is a schematic block diagram of a short-circuit protection circuit according to a fourth embodiment of the present invention, and referring to fig. 12, the short-circuit protection circuit according to the present embodiment combines the circuit according to the fourth embodiment and the circuit according to the sixth embodiment.

It is easy to understand that the short-circuit protection circuit of the present embodiment aims to improve the temperature rise problem and the carrying capacity problem of the upper arm at the same time, and when the judgment result of the first judgment unit is yes, the first execution unit includes three working modes, and the three working modes are the same as those of the first embodiment and the fourth embodiment, so that the beneficial effects brought by the three working modes are the same, and are not repeated; when the judgment result of the second judgment unit is yes, the second execution unit comprises three working modes, and the three working modes are the same as those of the second embodiment and the sixth embodiment, so that the beneficial effects are the same and are not repeated.

In this embodiment, whether the upper branch circuit has heavy load or short circuit, or the lower branch circuit has heavy load or short circuit, the current flowing in the corresponding branch circuit is reasonably limited by the reference currents with different magnitudes generated by the corresponding voltage control current units, so that not only the temperature rise of the bus driver can be controlled and the reliability of the bus driver is improved, but also the decoupling between the differential output voltage and the short circuit current of the bus driver is realized by reducing the control strategy of the number of the upper switch tubes or the lower switch tubes connected in parallel compared with the prior art, so that the two are not restricted each other, the defect that the current value of the corresponding branch circuit is very low when the short circuit recovery is required during electrification is avoided, and the load capacity of the bus driver is improved within a wide positive and negative common mode output voltage range.

Ninth embodiment

Fig. 13 is a schematic block diagram of a short-circuit protection circuit according to a ninth embodiment of the present invention, and fig. 14 is a schematic diagram of a short-circuit protection circuit according to a ninth embodiment of the present invention applied in a bus driver, where specific circuits are provided for all the units in fig. 10, please refer to fig. 13 and 14, and the short-circuit protection circuit according to the present embodiment combines the circuits of the fifth embodiment and the seventh embodiment.

It is easy to understand that the short-circuit protection circuit of the present embodiment aims to improve the temperature rise problem and the carrying capacity problem of the upper branch circuit at the same time, and the present embodiment includes three working modes when the upper branch circuit is turned on, and the three working modes are the same as those of the fifth embodiment, so that the beneficial effects brought by the three working modes are the same, and are not repeated; when the lower branch circuit is conducted, three working modes are included, and the three working modes are the same as those of the seventh embodiment, so that the beneficial effects are the same, and are not repeated.

According to the embodiment, corresponding voltage control current units and current proportion units are added for the upper branch and the lower branch of the main power of the driving stage IN the bus driver, wherein the voltage control current units can output reference currents with different sizes, the current proportion units are designed into current mirrors, the low-voltage PMOS tube MP3 and the low-voltage NMOS tube MN3 IN the current mirrors are connected IN series IN the upper branch and the lower branch of the main power of the driving stage IN the bus driver, so that the conduction internal resistances of the low-voltage PMOS tube MP3 and the low-voltage NMOS tube MN3 can be reduced to enhance the load capacity of the driving stage when the driving stage is designed, differential voltages output by bus nodes (A and B) can be improved, and the driving stage of the bus driver can be reasonably controlled to be limited by reasonably distributing the currents IN the voltage control current units (namely, the first reference current IP1 and the second reference current IP2 and the third reference current IN1 and the fourth reference current IN 2) and setting proper mirror proportion (namely, selecting m and n values) to the current proportion units.

In this embodiment, whether the upper branch circuit has heavy load or short circuit, or the lower branch circuit has heavy load or short circuit, the current flowing in the corresponding branch circuit is reasonably limited by the reference currents with different magnitudes generated by the corresponding voltage control current units, so that not only can the temperature rise of the bus driver be controlled and the reliability of the bus driver be improved, but also the decoupling between the differential output voltage and the short circuit current of the bus driver is realized by reducing the control strategy of the number of the upper switch tubes or the lower switch tubes connected in parallel compared with the prior art, so that the two are not restricted each other, and the defect that the current value of the corresponding branch circuit is very low when the short circuit recovery is required during electrification is avoided, so that the output disconnection of the bus driver improves the load capacity in the wide positive and negative common mode output voltage range.

Tenth embodiment

The present embodiment provides a bus driver, including the short-circuit protection circuit according to any one of the fourth to ninth embodiments, wherein the connection relationship between the short-circuit protection circuit and the bus driver is shown in the drawings corresponding to the embodiments.

The switching tube 106 in the upper branch circuit of the embodiment is a high-voltage P-power MOS tube, and the switching tube 206 in the lower branch circuit is a high-voltage N-power MOS tube; the first anti-backflow unit 105 and the second anti-backflow unit 205 may be respectively selected from a conventional diode, a schottky diode, or one of MOS transistors connected in a diode connection manner.

In this embodiment, when the short-circuit protection circuit includes the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 in the related drawings, since the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 are also connected in series on the main power branch of the driving stage of the bus driver, the maximum current flowing through the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 is generally in a class of 100mA, and in a normal load state, in order to pursue low voltage drop loss, the resistances of the linear regions of the PMOS transistor MP3 and the NMOS transistor MN3 cannot be too large, i.e., the size cannot be too small. Meanwhile, in order to ensure the matching precision of the PMOS tube MP3 and the PMOS tube MP2 and the NMOS tube MN3 and the NMOS tube MN2 in the saturation region in the short circuit state, when the size of the PMOS tube MP3 is m times of that of the PMOS tube MP2, the size of the NMOS tube MN3 is n times of that of the NMOS tube MN2, and the sizes of the PMOS tube MP2 and the NMOS tube MN2 cannot be too small, otherwise, the current matching precision is poor due to the boundary effect of the device parameters caused by undersize, so the multiples m and n cannot be too large, and are recommended to be about 100 times (such as 200uA:200 mA).

As shown IN fig. 15, which is a schematic diagram of waveforms of control voltages and output ports for driving the upper branch switching tube and the lower branch switching tube IN the bus driver of the present embodiment, when the upper branch switching tube and the lower branch switching tube are IN a normal working state, and each pulse is tapped, an initial value of a level VOUT of the driving port OUT always satisfies VOUT > Vthn or VOUT < Vthp, and the first comparator or the second comparator determines that a short circuit occurs, and considering that a transmission rate is a key indicator of the driving circuit, the fifth embodiment, the seventh embodiment and the ninth embodiment design corresponding delay units for avoiding erroneous entering the short circuit state, and the corresponding voltage control current units immediately select to provide a small reference current to the current proportioning unit, and the current proportioning unit multiplies the reference current with a small reference current which defines a current value flowing through the driving branch by the current proportioning unit, that is IP2×m or IN2×n, so as to slow down the first half portions of rising and falling times tr and tf of the power tube, that is tp and tn IN the figure.

It should be noted that the delay time of the delay unit should be designed to ensure that the switching parameter indexes tr and tf at the required highest transmission rate are not affected, i.e. the transmission delay tdp > tr of the first delay unit and the transmission delay tdn > tf of the second delay unit are designed.

The bus driver of this embodiment adds any one of the short-circuit protection circuits of the fourth embodiment to the ninth embodiment, so that whether the upper branch circuit has heavy load or short circuit, or the lower branch circuit has heavy load or short circuit, the current flowing in the corresponding branch circuit can be reasonably limited, so that not only the temperature rise of the bus driver can be controlled and the reliability of the bus driver can be improved, but also the decoupling between the differential output voltage and the short-circuit current of the bus driver is realized by reducing the control strategy of the number of the upper switch tubes or the lower switch tubes connected in parallel in comparison with the prior art, so that the two are not restricted by each other, and the defect that the current value of the corresponding branch circuit is very low when the short-circuit recovery is required during electrification is avoided, and the output disconnection of the bus driver improves the load capacity in a wide positive and negative common mode output voltage range.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Claims

1. The short circuit protection method is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switching tube in the upper branch is a PMOS tube, a switching tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short circuit protection method is characterized by comprising the following steps:

judging whether the upper branch circuit is conducted or not;

the first preset current is less than the second preset current.

2. The short-circuit protection method according to claim 1, characterized in that: and judging whether the upper branch is conducted or not according to the high or low of a switch tube grid driving signal in the upper branch.

3. The short circuit protection method is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switching tube in the upper branch is a PMOS tube, a switching tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short circuit protection method is characterized by comprising the following steps:

judging whether the lower branch circuit is conducted or not;

the third preset current is greater than the fourth preset current.

4. A short-circuit protection method according to claim 3, characterized in that: and judging whether the lower branch circuit is conducted or not according to the high or low of the switch tube grid driving signal in the lower branch circuit.

5. The short circuit protection method is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switching tube in the upper branch is a PMOS tube, a switching tube in the lower branch is an NMOS tube, and when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short circuit protection method is characterized by comprising the following steps:

Judging whether the upper branch circuit is conducted or not;

judging whether the lower branch circuit is conducted or not;

6. The short-circuit protection method according to claim 5, wherein: judging whether the upper branch is conducted or not according to the height of a switch tube grid driving signal in the upper branch; and judging whether the lower branch circuit is conducted or not according to the high or low of the switch tube grid driving signal in the lower branch circuit.

7. The utility model provides a short-circuit protection circuit, is applied to bus driver, bus driver includes upper arm and lower arm, the switching tube in the upper arm is the PMOS tube, the switching tube in the lower arm is the NMOS tube, when bus driver normally works, only one of upper arm with the lower arm switches on, its characterized in that: the short-circuit protection circuit comprises a first short-circuit protection unit;

the first short-circuit protection unit includes:

a first judging unit, configured to judge whether the upper leg is turned on;

the first preset current is less than the second preset current.

8. The short-circuit protection circuit of claim 7, wherein: the first judging unit judges whether the upper branch is conducted or not according to the high or low of a switch tube grid driving signal in the upper branch.

9. The utility model provides a short-circuit protection circuit, is applied to bus driver, bus driver includes upper arm and lower arm, the switching tube in the upper arm is the PMOS tube, the switching tube in the lower arm is the NMOS tube, when bus driver normally works, upper arm with only one of lower arm switches on, its characterized in that, short-circuit protection circuit includes:

10. The short-circuit protection circuit of claim 9, wherein the first delay unit comprises: PMOS tube MP4, NMOS tube MN4, capacitor C1 and Schmidt inverter SMT1; the grid of the PMOS tube MP4 is connected with the grid of the NMOS tube MN4 and then used as the input end of the first delay unit, the source of the PMOS tube MP4 is used for being connected with the power rail, the drain of the PMOS tube MP4, the drain of the NMOS tube MN4, one end of the capacitor C1 and the input end of the Schmitt inverter SMT1 are connected together, the source of the NMOS tube MN4 and the other end of the capacitor C1 are connected together and then used for being grounded, and the output end of the Schmitt inverter SMT1 is used as the output end of the first delay unit.

11. The short-circuit protection circuit of claim 9, wherein the first voltage-controlled current unit comprises: a switching tube S1, a first reference current IP1 and a second reference current IP2; the control end of the switching tube S1 is used as the control end of the first voltage control current unit, one end of the switching tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage control current unit, the other end of the switching tube S1 is connected with one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

12. The utility model provides a short-circuit protection circuit, is applied to bus driver, bus driver includes upper arm and lower arm, the switching tube in the upper arm is the PMOS tube, the switching tube in the lower arm is the NMOS tube, when bus driver normally works, only one of upper arm with the lower arm switches on, its characterized in that: the short-circuit protection circuit comprises a second short-circuit protection unit;

the second short protection unit includes:

a second judging unit, configured to judge whether the lower leg is turned on;

the third preset current is greater than the fourth preset current.

13. The short-circuit protection circuit of claim 12, wherein: the second judging unit judges whether the lower branch circuit is conducted or not according to the high or low of a switch tube grid driving signal in the lower branch circuit.

14. The utility model provides a short-circuit protection circuit, is applied to bus driver, bus driver includes upper arm and lower arm, the switching tube in the upper arm is the PMOS tube, the switching tube in the lower arm is the NMOS tube, when bus driver normally works, upper arm with only one of lower arm switches on, its characterized in that, short-circuit protection circuit includes:

15. The short-circuit protection circuit of claim 14, wherein the second delay unit comprises: PMOS tube MP5, NMOS tube MN5, capacitor C2 and Schmidt inverter SMT2; the grid electrode of the PMOS tube MP5 and the grid electrode of the NMOS tube MN5 are connected together and then serve as the input end of the second delay unit, the source electrode of the PMOS tube MP5 is used for being connected with a power rail, the drain electrode of the PMOS tube MP5, the drain electrode of the NMOS tube MN5, one end of the capacitor C2 and the input end of the Schmitt inverter SMT2 are connected together, the source electrode of the NMOS tube MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output end of the Schmitt inverter SMT2 serves as the output end of the second delay unit.

16. The short-circuit protection circuit of claim 14, wherein the second voltage-controlled current unit comprises: a switching tube S2, a third reference current IN1 and a fourth reference current IN2; the control end of the switching tube S2 is used as the control end of the second voltage control current unit, one end of the switching tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage control current unit, the other end of the switching tube S2 is connected with one end of the third reference current IN1, the other end of the third reference current IN1 is used for inputting a third reference current signal, and the other end of the fourth reference current IN2 is used for inputting a fourth reference current signal.

17. The utility model provides a short-circuit protection circuit, is applied to bus driver, bus driver includes upper arm and lower arm, the switching tube in the upper arm is the PMOS tube, the switching tube in the lower arm is the NMOS tube, when bus driver normally works, only one of upper arm with the lower arm switches on, its characterized in that: the short-circuit protection circuit comprises a first short-circuit protection unit and a second short-circuit protection unit;

the first short-circuit protection unit includes:

a first judging unit, configured to judge whether the upper leg is turned on;

the first preset current is less than the second preset current;

the second short protection unit includes:

a second judging unit, configured to judge whether the lower leg is turned on;

the third preset current is greater than the fourth preset current.

18. The short-circuit protection circuit of claim 17, wherein: the first judging unit judges whether the upper branch is conducted or not according to the height of a switch tube grid driving signal in the upper branch; the second judging unit judges whether the lower branch circuit is conducted or not according to the high or low of a switch tube grid driving signal in the lower branch circuit.

19. The utility model provides a short-circuit protection circuit, is applied to bus driver, bus driver includes upper arm and lower arm, the switching tube in the upper arm is the PMOS tube, the switching tube in the lower arm is the NMOS tube, when bus driver normally works, upper arm with only one of lower arm switches on, its characterized in that, short-circuit protection circuit includes:

20. The short-circuit protection circuit of claim 19, wherein the first delay unit comprises: PMOS tube MP4, NMOS tube MN4, capacitor C1 and Schmidt inverter SMT1; the grid of the PMOS tube MP4 is connected with the grid of the NMOS tube MN4 and then used as the input end of the first delay unit, the source of the PMOS tube MP4 is used for being connected with the power rail, the drain of the PMOS tube MP4, the drain of the NMOS tube MN4, one end of the capacitor C1 and the input end of the Schmitt inverter SMT1 are connected together, the source of the NMOS tube MN4 and the other end of the capacitor C1 are connected together and then used for being grounded, and the output end of the Schmitt inverter SMT1 is used as the output end of the first delay unit.

21. The short-circuit protection circuit of claim 19, wherein the first voltage-controlled current unit comprises: a switching tube S1, a first reference current IP1 and a second reference current IP2; the control end of the switching tube S1 is used as the control end of the first voltage control current unit, one end of the switching tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage control current unit, the other end of the switching tube S1 is connected with one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

22. The short-circuit protection circuit of claim 19, wherein the second delay unit comprises: PMOS tube MP5, NMOS tube MN5, capacitor C2 and Schmidt inverter SMT2; the grid electrode of the PMOS tube MP5 and the grid electrode of the NMOS tube MN5 are connected together and then serve as the input end of the second delay unit, the source electrode of the PMOS tube MP5 is used for being connected with the power rail, the drain electrode of the PMOS tube MP5, the drain electrode of the NMOS tube MN5, one end of the capacitor C2 and the input end of the Schmitt inverter SMT2 are connected together, the source electrode of the NMOS tube MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output end of the Schmitt inverter SMT2 serves as the output end of the second delay unit.

23. The short-circuit protection circuit of claim 22, wherein the second voltage-controlled current unit comprises: a switching tube S2, a third reference current IN1 and a fourth reference current IN2; the control end of the switching tube S2 is used as the control end of the second voltage control current unit, one end of the switching tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage control current unit, the other end of the switching tube S2 is connected with one end of the third reference current IN1, the other end of the third reference current IN1 is used for inputting a third reference current signal, and the other end of the fourth reference current IN2 is used for inputting a fourth reference current signal.

24. A bus driver, comprising: a short circuit protection circuit according to any one of claims 7 to 23.