CN114975242B - Preparation method of 2.5D packaging structure - Google Patents

Preparation method of 2.5D packaging structure Download PDF

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Publication number
CN114975242B
CN114975242B CN202210441937.7A CN202210441937A CN114975242B CN 114975242 B CN114975242 B CN 114975242B CN 202210441937 A CN202210441937 A CN 202210441937A CN 114975242 B CN114975242 B CN 114975242B
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layer
chip
conductive column
bottom metal
semiconductor substrate
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CN114975242A (en
Inventor
刘翔
尹佳山
周祖源
薛兴涛
林正忠
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a preparation method of a 2.5D packaging structure, which is characterized in that a process for removing a bottom metal layer is placed at the end, so that the bottom metal layer can isolate the influence of laser irradiation on the packaging structure, particularly a chip, when a second supporting substrate is removed, thereby protecting the 2.5D packaging structure from protecting the chip and improving the success rate and the yield of the reliability test of the 2.5D packaging chip; the bottom metal layer is easy to form and remove, the packaging cost is not increased, and the process is simple and effective; the second surface of the semiconductor substrate is subjected to chemical mechanical polishing, so that the flatness of the semiconductor substrate is improved, the bonding strength of a plurality of interfaces in subsequent packaging can be improved, and the contact resistance between the bottom metal layer and the TSV conductive column can be reduced; the TSV conductive column, the connection pad and the metal bump are positioned on the same vertical line, so that the delay of the resistance reduction signal can be effectively reduced.

Description

Preparation method of 2.5D packaging structure
Technical Field
The invention relates to the field of semiconductors, in particular to a preparation method of a 2.5D packaging structure.
Background
With the increasing performance requirements of High Performance Computing (HPC) chips such as CPU, GPU, FPGA, the conventional flip chip packaging (FC), package On Package (POP) and other packaging technologies have failed to meet the requirements, and the requirements for 2.5D/3D packaging technologies have increased. At present, the well-known 2.5D packaging technology has CoWoS with accumulated electricity, and can package a plurality of chips together, so that the effects of small packaging volume, low power consumption and few pins are achieved.
In the 2.5D packaging process, process variations can lead to single or multiple chip failure, which in turn can lead to failure of the reliability test results for the entire package structure. Therefore, we need to continuously optimize and improve the process, and the invention provides a preparation method of a 2.5D package structure to improve the yield.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a 2.5D package structure, which is used for solving the problem that the reliability test failure of the chip in the prior art easily occurs, thereby affecting the yield.
To achieve the above and other related objects, the present invention provides a method for manufacturing a 2.5D package structure, the method for manufacturing a 2.5D package structure comprising the steps of:
s1, providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, a TSV conductive column is formed in the semiconductor substrate, and the TSV conductive column comprises a TSV conductive column first end exposed on the first surface of the semiconductor substrate and a TSV conductive column second end positioned in the semiconductor substrate;
s2, forming a first dielectric layer on the first surface of the semiconductor substrate, and etching the first dielectric layer to expose the first end of the TSV conductive column;
s3, forming a connection pad electrically connected with the first end of the TSV conductive column on the first dielectric layer;
s4, providing a first support substrate, bonding the connection pad downwards to the first support substrate, and thinning the semiconductor substrate to expose the second end of the TSV conductive column;
s5, forming a second dielectric layer on the second surface of the semiconductor substrate, and etching the second dielectric layer to expose the second end of the TSV conductive column;
s6, forming a bottom metal layer on the second dielectric layer, wherein the bottom metal layer completely covers the second dielectric layer and is in electrical contact with the second end of the TSV conductive column;
s7, forming a patterned mask layer on the bottom metal layer, forming a metal bump array electrically connected with the bottom metal layer, and removing the mask layer;
s8, providing a second support substrate, and bonding the metal bump array downwards to the second support substrate by combining a laser separation layer;
s9, removing the first support substrate and exposing the connection pads;
s10, providing a chip, and flip-chip mounting the chip on the connection pad to be electrically connected with the connection pad, wherein the projection of the chip on the bottom metal layer is completely positioned in the bottom metal layer;
s11, forming a plastic packaging material layer on the first dielectric layer, wherein the plastic packaging material layer coats the chip and the first dielectric layer;
s12, removing the second support substrate to expose the metal bump array, and removing the exposed bottom metal layer.
Preferably, the TSV conductive post, the connection pad and the metal bump are formed on the same vertical line.
Preferably, the laser separation layer includes an LTHC layer to thermally lift off the second support substrate based on laser light.
Preferably, the step of forming the TSV conductive post includes a step of preparing a TSV hole using one or a combination of laser drilling, mechanical drilling, deep reactive ion etching, and photo-assisted electrochemical etching.
Preferably, the mask layer includes a dry film or a photoresist.
Preferably, the bottom metal layer comprises a diffusion barrier layer and/or a seed layer, wherein the diffusion barrier layer comprises one or a combination of Ti, tiN, ta, taN.
Preferably, a metal micro-bump is arranged on the active surface of the chip, and is electrically contacted with the connection pad through the metal micro-bump.
Preferably, before forming the plastic package material layer on the first dielectric layer, the method further includes a step of filling the gap between the chip and the first dielectric layer with underfill.
Preferably, the process of planarizing the plastic packaging material layer is further included after the plastic packaging material layer is formed.
Preferably, the chip is one or a combination of a bare chip or a packaged chip, and the number of the chips is N, wherein N is more than or equal to 2.
As described above, the preparation method of the 2.5D packaging structure has the following beneficial effects: the bottom metal layer under the metal bump array can isolate the influence of laser irradiation on the packaging structure under the bottom metal layer, particularly the chip, when the second supporting substrate is removed, so that the 2.5D packaging structure is protected, the chip is protected, the success rate of the reliability test of the 2.5D packaging chip is improved, and the yield of the 2.5D packaging chip is also improved; the bottom metal layer is easy to form and remove, the 2.5D packaging structure can be protected by placing the process for removing the bottom metal layer, the packaging cost is not increased, and the process is simple and effective.
In addition, before the bottom metal layer is formed, the second surface of the semiconductor substrate is treated by methods such as chemical mechanical polishing and the like, so that the flatness of the semiconductor substrate is improved, the bonding strength of a plurality of interfaces in subsequent packaging can be improved, the problems of layering, cracking and the like in the process are prevented, the contact resistance between the subsequent bottom metal layer and the TSV conductive column is also reduced, and the reliability and the yield of the packaging structure are further improved; the TSV conductive column, the connection pad and the metal bump are positioned on the same vertical line, so that the delay of resistance reduction signals can be effectively reduced.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a 2.5D package structure according to an embodiment of the invention.
Fig. 2-7 are schematic structural views showing steps in fig. 1.
Description of element reference numerals
100. Semiconductor substrate
110 TSV conductive column
120. A first dielectric layer
130. Connection pad
200. A first support substrate
210. First separation layer
300. Metal bump array
310. Bottom metal layer
320. A second dielectric layer
400. A second support substrate
410. Laser separation layer
500. Chip
510. Metal micro bump
520. Underfill
530. Plastic packaging material layer
S1 to S12 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
While fig. 1-7 illustrate embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not to scale in general, and the schematic views are merely examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1, the invention provides a method for preparing a 2.5D package structure, which comprises the following steps:
s1, providing a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a first surface and a second surface which are oppositely arranged, a TSV conductive column 110 is formed in the semiconductor substrate 100, and the TSV conductive column 110 comprises a first end of the TSV conductive column 110 exposed on the first surface of the semiconductor substrate 100 and a second end of the TSV conductive column 110 in the semiconductor substrate 100;
s2, forming a first dielectric layer 120 on the first surface of the semiconductor substrate 100, and etching the first dielectric layer 120 to expose the first end of the TSV conductive column 110;
s3, forming a connection pad 130 electrically connected with the first end of the TSV conductive column 110 on the first dielectric layer 120;
s4, providing a first support substrate 200, bonding the connection pad 130 downwards to the first support substrate 200, and thinning the semiconductor substrate 100 to expose the second end of the TSV conductive post 110;
s5, forming a second dielectric layer 320 on the second surface of the semiconductor substrate 100, and etching the second dielectric layer 320 to expose the second end of the TSV conductive column 110;
s6, forming a bottom metal layer 310 on the second dielectric layer 320, wherein the bottom metal layer 310 completely covers the second dielectric layer 320 and is in electrical contact with the second end of the TSV conductive column 110;
s7, forming a patterned mask layer (not shown) on the bottom metal layer 310, forming a metal bump array 300 electrically connected with the bottom metal layer 310, and removing the mask layer;
s8, providing a second support substrate 400, and bonding the metal bump array 300 to the second support substrate 400 in a downward mode by combining a laser separation layer 410;
s9, removing the first support substrate 200 to expose the connection pads 130;
s10, providing a chip 500, and flip-chip the chip 500 onto the connection pad 130 to be electrically connected with the connection pad 130, wherein the projection of the chip 500 on the bottom metal layer 310 is completely located in the bottom metal layer 310;
s11, forming a plastic packaging material layer 530 on the first dielectric layer 120, wherein the plastic packaging material layer 530 covers the chip 500 and the first dielectric layer 120;
and S12, removing the second support substrate 400 to expose the metal bump array 300, and removing the exposed bottom metal layer 310.
As shown in step S1 in fig. 1 and fig. 2, a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a first surface and a second surface disposed opposite to each other, a TSV hole is formed in the semiconductor substrate 100 from the first surface of the semiconductor substrate 100, and a conductive material is filled in the TSV hole to form a TSV conductive column 110; the TSV conductive post 110 includes a TSV conductive post 110 first end and a TSV conductive post 110 second end, the TSV conductive post 110 first end is exposed on the first surface of the semiconductor substrate 100, and the TSV conductive post 110 second end is located in the semiconductor substrate 100.
Specifically, the semiconductor substrate 100 includes, but is not limited to, a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, or a gallium nitride substrate, and the shape thereof is any structure including a circle, an ellipse, a polygon, etc., and is not particularly limited herein, and is specifically selected according to need; forming a TSV hole on the first surface of the semiconductor substrate 100, wherein a method of forming the TSV hole includes one or a combination of laser drilling, mechanical drilling, deep reactive ion etching, and photo-assisted electrochemical etching; and filling the TSV hole with a conductive material to form the TSV conductive column 110, wherein the conductive material is one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum, and the like, and the filling method is any one or a combination of electroplating, electroless plating, silk screen printing and wire bonding, and one or a combination of a layer Ta, taN, ti, tiN is deposited as a diffusion barrier layer or an adhesion layer in order to prevent the conductive material from diffusing into the semiconductor substrate and increase the adhesion strength between the conductive material and the semiconductor substrate.
As shown in step S2 in fig. 1 and in fig. 3, a first dielectric layer 120 is formed on the first surface of the semiconductor substrate 100, and the first dielectric layer 120 is etched to expose the first end of the TSV conductive post 110.
Specifically, the first dielectric layer 120 includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, fluorine-containing glass, and the like, in this embodiment, PI is used for the first dielectric layer 120, and the first dielectric layer 120 is etched to expose the first end of the TSV conductive post 110 at the opening of the first dielectric layer 120.
As shown in step S3 in fig. 1 and in fig. 3, a connection pad 130 electrically connected to the first end of the TSV conductive post 110 is formed on the first dielectric layer 120.
Specifically, a metal layer is deposited on the first dielectric layer 120 by electroplating, physical vapor deposition, chemical vapor deposition, or the like, where the metal layer may be one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum, and the like, and the metal layer is etched to form a connection pad 130, and the connection pad 130 is vertically located above the first end of the TSV conductive column 110 and is electrically connected to the first end of the TSV conductive column 110. The connection pads in this embodiment are fabricated by a copper nickel gold electroplating process.
As shown in step S4 in fig. 1 and fig. 3, a first supporting substrate 200 is provided, and the connection pad 130 is bonded downward onto the first supporting substrate 200, and the semiconductor substrate 100 is thinned to expose the second end of the TSV conductive post 110.
Specifically, the connection pad 130 is bonded to the first support substrate 200 through the first separation layer 210 downward, the first support substrate 200 may be one of a glass substrate, a ceramic substrate, a polymer substrate and a metal substrate, and the first support substrate 200 provides a support plane for a subsequent package structure to prevent the semiconductor chip from cracking, breaking, warping and other problems in the subsequent manufacturing process, and needs to be removed later, so that in this embodiment, a glass substrate with relatively low cost is used, and the separation layer is easily formed and peeled on the glass substrate.
The first separation layer 210 is required to bond and fix the connection pad 130 to the first support substrate 200, and thus the first separation layer 210 must have a certain adhesion with the connection pad 130, and for the convenience of peeling, the adhesion between the first separation layer 210 and the connection pad 130 is generally smaller than the adhesion between the first separation layer 210 and the first support substrate 200. The first separation layer 210 includes a polymer layer or an adhesive layer, which is coated on the surface of the first support substrate 200 using a spin coating process, and then is cured and formed using a curing process to bond the connection pad 130 downward to the first support substrate 200. In this embodiment, the polymer layer is an LTHC light-heat conversion layer, and when the first separation layer 210 is peeled, a laser may be used to heat the LTHC light-heat conversion layer, so that the connection pad 130 and the first support substrate 200 are separated from each other from the LTHC light-heat conversion layer.
The semiconductor substrate 100 is turned over so that the second surface of the semiconductor substrate 100 faces upwards, then the semiconductor substrate 100 is thinned by adopting a chemical mechanical polishing method and the like so as to expose the second end of the TSV conductive post 110, and the second surface is processed by adopting a chemical mechanical polishing method and the like so as to obtain good flatness, so that the bonding strength of a plurality of interfaces in subsequent packaging can be improved, the problems of layering, cracking and the like in the process are prevented, the contact resistance between the subsequent bottom metal layer 310 and the TSV conductive post 110 is reduced, and the reliability and the yield of the packaging structure are improved.
As shown in step S5 in fig. 1 and in fig. 4, a second dielectric layer 320 is formed on the second surface of the semiconductor substrate 100, and the second dielectric layer 320 is etched to expose the second end of the TSV conductive post 110.
Specifically, the second dielectric layer 320 includes one or a combination of epoxy, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass, in this embodiment, PI is used for the second dielectric layer 320, and the second dielectric layer 320 is etched to expose the second end of the TSV conductive post 110 at the opening of the second dielectric layer 320.
As shown in step S6 in fig. 1 and in fig. 4, a bottom metal layer 310 is formed on the second dielectric layer 320, and the bottom metal layer 310 completely covers the second dielectric layer 320 and is in electrical contact with the second end of the TSV conductive post 110.
In detail, the bottom metal layer 310 is located on the surface of the second dielectric layer 320 and the sidewall at the opening, and is in vertical electrical contact with the second end of the TSV conductive post 110 at the bottom of the opening of the second dielectric layer 320, wherein the bottom metal layer 310 forming method includes a physical vapor deposition or sputtering method.
As an example, the bottom metal layer 310 includes a diffusion barrier layer and/or a seed layer, wherein the diffusion barrier layer includes one or a combination of Ti, tiN, ta, taN. In detail, the diffusion barrier layer, also referred to as an adhesion layer, may not only prevent diffusion of the seed layer into the second dielectric layer 320, but may also increase adhesion therebetween, the diffusion barrier layer comprising one or a combination of Ti, tiN, ta, taN; the seed layer is formed over the diffusion barrier layer, typically a Cu seed layer, and may also be formed of a Cu alloy, wherein the Cu alloy includes one or a combination of gold, silver, nickel, tin, and chromium. In this embodiment, the diffusion barrier layer is a Ti layer and the seed layer is a Cu seed layer.
As shown in step S7 of fig. 1 and fig. 5, a patterned mask layer (not shown) is formed on the bottom metal layer 310, and a metal bump array 300 electrically connected to the bottom metal layer 310 is formed, and the mask layer is removed.
As an example, the mask layer includes a dry film or a photoresist; forming a patterned mask layer on the bottom metal layer 310 after the dry film or the photoresist is coated, exposed and developed, wherein an opening of the mask layer is correspondingly arranged vertically above the second end of the TSV conductive post 110, and a metallization layer and a welding layer are deposited in the opening of the mask layer by electroplating, electroless plating and other methods and are vertically and electrically contacted with the bottom metal layer 310; the mask layer is removed by etching such as wet etching, dry etching or the like, and an array of bumps is formed on the bonding layer by using a C4 bonding method, and the metallization layer, the bonding layer and the array of bumps together form an array of metal bumps 300, the array of metal bumps 300 being spread over the entire surface of the semiconductor substrate 100, while the array of metal bumps 300 is vertically and electrically connected to the second ends of the TSV conductive pillars 110 through the bottom metal layer 310.
As an example, the TSV conductive post 110, the connection pad 130, and the metal bump are formed on the same vertical line.
Specifically, the connection pad 130 is vertically located above the first end of the TSV conductive column 110 and is electrically connected to the first end of the TSV conductive column 110, and the metal bump array is vertically and electrically connected to the second end of the TSV conductive column 110 through the bottom metal layer 310, so that the TSV conductive column 110, the connection pad 130 and the metal bump are formed on the same vertical line, which reduces the resistance among the TSV conductive column 110, the connection pad 130 and the metal bump and also reduces the signal delay among the TSV conductive column 110, the connection pad 130 and the metal bump.
As shown in step S8 of fig. 1 and fig. 6, a second support substrate 400 is provided, and the metal bump array 300 is bonded to the second support substrate 400 with the laser separation layer 410 facing downward. The second supporting substrate 400 also provides a supporting plane for the subsequent packaging structure to prevent the semiconductor chip from cracking, breaking, warping, etc. during the subsequent manufacturing process, and needs to be removed later, so the second supporting substrate 400 can refer to the first supporting substrate, which is not described in detail herein.
As an example, the laser separation layer 410 includes an LTHC layer to thermally lift off the second support substrate 400 based on laser light. The LTHC layer is also called a photo-thermal conversion layer, and the LTHC layer is irradiated with laser, so that the LTHC layer absorbs light to generate heat to reduce viscosity, and the metal bump array 300 and the second support substrate 400 are separated from the laser separation layer 410, so that the second support substrate 400 is conveniently peeled.
As shown in step S9 in fig. 1 and in fig. 6, the first supporting substrate 200 is removed, and the connection pads 130 are exposed; the first substrate 200 and the first separation layer 210 may be removed by one or a combination of mechanical grinding, chemical polishing, etching, heating, and mechanical stripping, in this embodiment, the first separation layer 210 is an LTHC light-heat conversion layer, and the LTHC light-heat conversion layer is heated by laser to reduce the viscosity of the LTHC light-heat conversion layer, so that the connection pad 130 and the first support substrate 200 are separated from the first separation layer 210, and the connection pad 130 is exposed.
As shown in step S10 in fig. 1 and fig. 6, a chip 500 is provided, and the chip 500 is flip-chip mounted on the connection pad 130 to be electrically connected with the connection pad 130, and the projection of the chip 500 on the bottom metal layer 310 is completely located in the bottom metal layer 310.
Specifically, the chip 500 includes one or a combination of a bare chip and a packaged chip, and is specifically configured according to actual needs, which is not particularly limited herein. The number of the chips 500 is shown as 3 in the present embodiment, but the number of the chips 500 is not limited thereto, and the number of the chips 500 may be 2 or more, such as 2, 4, 5, etc., or more according to the need.
As an example, a metal micro bump is disposed on the active surface of the chip 500, and is electrically contacted with the connection pad 130 through the solder micro bump.
Specifically, the active surface of the chip 500 is provided with a solder micro-bump, the solder micro-bump is electrically connected with the internal circuit of the chip 500, and the chip 500 is flip-chip mounted on the first surface of the semiconductor substrate 100 through the solder micro-bump and the connection pad 130, and the chip 500 may be arranged in parallel or in staggered intervals on the first surface of the semiconductor substrate 100, which is specifically set according to the requirement, but in order to protect the chip 500 from the laser radiation when the second support substrate 400 is peeled, the projection of the chip 500 on the bottom metal layer 310 is completely located in the bottom metal layer 310, so that the bottom metal layer 310 can effectively isolate the laser radiation from affecting the chip 500, thereby protecting the chip by a protection 2.5D package structure, improving the success rate of the reliability test of the 2.5D package chip, and improving the yield of the 2.5D package chip.
As shown in step S11 in fig. 1 and in fig. 6, a molding material layer 530 is formed on the first dielectric layer 120, and the molding material layer 530 encapsulates the chip 500 and the first dielectric layer 120.
As an example, the step of filling the gap between the chip 500 and the first dielectric layer 120 with the underfill 520 is further included before forming the molding compound layer 530 on the first dielectric layer 120.
Specifically, in order to strengthen the connection between the chip 500 and the semiconductor substrate 100 and enhance the anti-dropping performance of the package structure, in this embodiment, a capillary underfill method is used to fill the gap between the chip 500 and the semiconductor substrate 100 with the underfill 520. The capillary underfill method uses capillary action to allow glue to quickly flow through the bottom of the bottom chip 600, with a minimum of 10 μm for capillary flow. The solder ball meets the minimum electrical property requirement between the bonding pad and the solder ball in the welding process, and the glue cannot flow through a gap smaller than 4 mu m, so that the electrical safety property of the welding process is guaranteed, and the bottom gap is filled in a large area by utilizing a heated solidification form, so that the anti-dropping performance of the packaging structure is enhanced.
Wherein the molding material layer 530 formed on the first dielectric layer 120 includes, but is not limited to, a polyimide layer, a silica gel layer, and an epoxy resin layer, and a method of forming the molding material layer 530 includes one of compression molding, transfer molding, liquid sealing molding, molding underfill, capillary underfill, vacuum lamination, and spin coating. In order to simplify the process, the molding material layer 530 in this embodiment also adopts a capillary underfill method, and the molding material layer 530 encapsulates the chip 500 and the first dielectric layer 120.
As an example, the process of planarizing the molding material layer 530 is further included after forming the molding material layer 530.
Specifically, in order to improve the flatness of the surface of the plastic package material layer 530, the thickness of the 2.5D package structure is controlled, so that the plastic package material layer 530 is subjected to planarization treatment, the plastic package material layer 530 is thinned, and meanwhile, the flatness of the surface of the plastic package material layer 530 is improved, so that the subsequent 2.5D package structure is convenient to further process. Methods of planarization include mechanical polishing, chemical mechanical polishing, and the like.
As shown in step S12 in fig. 1 and fig. 7, the second support substrate 400 is removed to expose the metal bump array 300, and the exposed bottom metal layer 310 is removed.
Specifically, the second support substrate 400 may be removed by the same or similar method as that for removing the first support substrate 200, and will not be described in detail herein. The exposed bottom metal layer is removed by dry etching or wet etching, but wet etching is widely used because it is low in cost and does not require cleaning etching residues. In the embodiment, ti/Cu of the bottom metal layer is removed by wet etching; for etching the Cu crystal layer, the etching liquid is formed by H 2 O 2 、H 3 PO4 is mixed in a certain proportion and uniformly sprayed on the surface of the bottom metal layer 310 through etching equipment to complete the etching of the Cu crystal layer; after the etching of the Cu crystal layer is finished, the 2.5D packaging structure is sent to the Ti etching layer, and the etching liquid of Ti is formed by H 2 O 2 Mixing KOH and Ti, uniformly spraying on the surface of the bottom metal layer 310 by etching equipment to finish etching Ti, and washing with DI water and pure N 2 Drying is carried out, so that the whole etching process is completed. Since the etching process of the bottom metal layer 310 is located after the second support substrate 400 is removed, the bottom metal layer 310 can be isolatedExcept for the influence of the laser irradiation on the packaging structure under the bottom metal layer 310, particularly the chip 500, when the second support substrate 400 is used, the 2.5D packaging structure is protected to protect the chip, the success rate of the reliability test of the 2.5D packaged chip is improved, and the yield of the 2.5D packaged chip is also improved; the bottom metal layer 310 is easy to form and remove, and the process of removing the bottom metal layer 310 is placed to be final, so that the 2.5D package structure can be protected, the package cost is not increased, and the process is simple and effective.
In summary, the preparation method of the 2.5D packaging structure has the following beneficial effects: the bottom metal layer under the metal bump array can isolate the influence of laser irradiation on the packaging structure under the bottom metal layer, particularly the chip, when the second supporting substrate is removed, so that the 2.5D packaging structure is protected, the chip is protected, the success rate of the reliability test of the 2.5D packaging chip is improved, and the yield of the 2.5D packaging chip is also improved; the bottom metal layer is easy to form and remove, the 2.5D packaging structure can be protected by placing the process for removing the bottom metal layer, the packaging cost is not increased, and the process is simple and effective.
In addition, before the bottom metal layer is formed, the second surface of the semiconductor substrate is treated by methods such as chemical mechanical polishing and the like, so that the flatness of the semiconductor substrate is improved, the bonding strength of a plurality of interfaces in subsequent packaging can be improved, the problems of layering, cracking and the like in the process are prevented, the contact resistance between the subsequent bottom metal layer and the TSV conductive column is also reduced, and the reliability and the yield of the packaging structure are further improved; the TSV conductive column, the connection pad and the metal bump are positioned on the same vertical line, so that the delay of resistance reduction signals can be effectively reduced.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The preparation method of the 2.5D packaging structure is characterized by comprising the following steps of:
s1, providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface which are oppositely arranged, a TSV conductive column is formed in the semiconductor substrate, and the TSV conductive column comprises a TSV conductive column first end exposed on the first surface of the semiconductor substrate and a TSV conductive column second end positioned in the semiconductor substrate;
s2, forming a first dielectric layer on the first surface of the semiconductor substrate, and etching the first dielectric layer to expose the first end of the TSV conductive column;
s3, forming a connection pad electrically connected with the first end of the TSV conductive column on the first dielectric layer;
s4, providing a first support substrate, bonding the connection pad downwards to the first support substrate, and thinning the semiconductor substrate to expose the second end of the TSV conductive column;
s5, forming a second dielectric layer on the second surface of the semiconductor substrate, and etching the second dielectric layer to expose the second end of the TSV conductive column;
s6, forming a bottom metal layer on the second dielectric layer, wherein the bottom metal layer completely covers the second dielectric layer and is in electrical contact with the second end of the TSV conductive column;
s7, forming a patterned mask layer on the bottom metal layer, forming a metal bump array electrically connected with the bottom metal layer, and removing the mask layer;
s8, providing a second support substrate, and bonding the metal bump array downwards to the second support substrate by combining a laser separation layer;
s9, removing the first support substrate and exposing the connection pads;
s10, providing a chip, and flip-chip mounting the chip on the connection pad to be electrically connected with the connection pad, wherein the projection of the chip on the bottom metal layer is completely positioned in the bottom metal layer;
s11, forming a plastic packaging material layer on the first dielectric layer, wherein the plastic packaging material layer coats the chip and the first dielectric layer;
s12, removing the second support substrate to expose the metal bump array, and removing the exposed bottom metal layer.
2. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the TSV conductive column, the connection pad and the metal bump are formed on the same vertical line.
3. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the laser separation layer includes an LTHC layer to thermally lift off the second support substrate based on a laser.
4. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the step of forming the TSV conductive column comprises the step of preparing a TSV hole by one or a combination of laser drilling, mechanical drilling, deep reactive ion etching and photo-assisted electrochemical etching.
5. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the mask layer includes photoresist.
6. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the bottom metal layer includes a diffusion barrier layer and/or a seed layer, wherein the diffusion barrier layer includes one or a combination of Ti, tiN, ta, taN.
7. The method for manufacturing a 2.5D package structure according to claim 1, wherein: and the active surface of the chip is provided with a metal micro-bump, and the metal micro-bump is electrically contacted with the connecting bonding pad.
8. The method for manufacturing a 2.5D package structure according to claim 1, wherein: and the step of filling the gap between the chip and the first dielectric layer with underfill before forming the plastic package material layer on the first dielectric layer is further included.
9. The method for manufacturing a 2.5D package structure according to claim 1, wherein: and the process of planarizing the plastic packaging material layer is further included after the plastic packaging material layer is formed.
10. The method for manufacturing a 2.5D package structure according to claim 1, wherein: the chip is one or a combination of a bare chip and a packaged chip, and the number of the chips is N, wherein N is more than or equal to 2.
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