CN114946042A - Fan-out structure of Light Emitting Diode (LED) device and lighting system - Google Patents

Fan-out structure of Light Emitting Diode (LED) device and lighting system Download PDF

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Publication number
CN114946042A
CN114946042A CN202080093666.XA CN202080093666A CN114946042A CN 114946042 A CN114946042 A CN 114946042A CN 202080093666 A CN202080093666 A CN 202080093666A CN 114946042 A CN114946042 A CN 114946042A
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substrate
silicon
array
top surface
metal layer
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CN202080093666.XA
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T·Y·轩
A·维亚纳坦
S·巴纳
R·J·邦内
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Lumileds LLC
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Lumileds LLC
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Priority claimed from US16/750,839 external-priority patent/US11621173B2/en
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    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Lighting Device Outwards From Vehicle And Optical Signal (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

A system is described. A system includes a silicon backplate having a top surface, a bottom surface, and side surfaces, and a substrate surrounding the side surfaces of the silicon backplate. The substrate has a top surface, a bottom surface, and side surfaces. At least one bond pad is disposed on the bottom surface of the substrate. A metal layer is disposed on the bottom surface of the substrate and the bottom surface of the silicon backplate and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplate in a central region and a second portion extending between the peripheral region of the silicon backplate and the at least one bond pad. An array of metal connectors is disposed on the top surface of the silicon backplane.

Description

Fan-out structure of Light Emitting Diode (LED) device and lighting system
Cross Reference to Related Applications
This application claims the benefit of 16/750839 U.S. non-provisional application filed on 23/1/2020, 20158481.0 european patent application filed on 20/2/2020, 62/951601 provisional application filed on 20/12/2019, and 62/937629 U.S. provisional application filed on 19/11/2019, the contents of which are incorporated herein by reference.
Background
Closely controlled lighting applications may require the production and manufacture of small addressable Light Emitting Diode (LED) lighting systems. The smaller size of such systems may require unconventional components and manufacturing processes.
Disclosure of Invention
LED lighting systems, vehicle headlamp systems, and methods of manufacture are described. The LED lighting system includes a silicon backplane having a top surface, a bottom surface, and side surfaces, and a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface, and side surfaces. A first redistribution layer is disposed on a top surface of the silicon backplane and a top surface of the substrate. The second redistribution layer is disposed on a bottom surface of the silicon backplane and a bottom surface of the substrate. At least one via extends through the substrate between the first and second redistribution layers and is filled with a metal material.
Drawings
A more particular understanding can be obtained by reference to the following description, given by way of example in conjunction with the accompanying drawings, in which:
FIG. 1A is a top view of an example LED array;
FIG. 1B is a cross-sectional view of an example LED lighting system;
FIG. 1C is a top view of the example LED lighting system of FIG. 1B;
FIG. 1D is a bottom view of the example LED lighting system of FIG. 1B;
FIG. 2 is a cross-sectional view of an example application incorporating the LED lighting system of FIG. 1B;
FIG. 3 is a diagram of an example vehicle headlamp system incorporating the LED lighting system of FIG. 1B;
FIG. 4 is a diagram of another example vehicle headlamp system;
FIG. 5 is a flow chart of an example method of manufacturing an LED lighting system (such as the LED lighting system of FIG. 1B);
fig. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I and 6J are cross-sectional views of an LED lighting system at various stages of a manufacturing process; and
fig. 7 is a bottom view showing the bottom surface of the LED illumination system of fig. 6E.
Detailed Description
Examples of different light illumination system and/or light emitting diode ("LED") embodiments are described more fully below with reference to the accompanying drawings. These examples are not mutually exclusive and features found in one example may be combined with features found in one or more other examples to achieve additional embodiments. Accordingly, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only, and they are not intended to limit the present disclosure in any way. Like numbers refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. For example, a first element could be termed a second element, and a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" can include any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" onto "another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending" onto another element, there may be no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element and/or connected or coupled to the other element via one or more intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present between the element and the other element. It will be understood that these terms are intended to encompass different orientations of the element in addition to any orientation depicted in the figures.
Relative terms, such as "below," "above," "over," "below," "horizontal," or "vertical," may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
Additionally, whether the LEDs, LED arrays, electrical components, and/or electronic components are housed on one, two, or more electronic boards may also depend on design constraints and/or applications.
Semiconductor Light Emitting Devices (LEDs) or optical power emitting devices, such as devices that emit Ultraviolet (UV) or Infrared (IR) optical power, are among the most efficient light sources currently available. These devices (hereinafter "LEDs") may include light emitting diodes, resonant cavity light emitting diodes, vertical cavity laser diodes, edge emitting lasers, and the like. For example, LEDs may be attractive candidates for many different applications due to their compact size and lower power requirements. For example, they may be used as light sources (e.g., flash and camera flash) for handheld battery-powered devices such as cameras and cell phones. They may also be used for e.g. automotive lighting, head-up display (HUD) lighting, horticulture lighting, street lighting, video flashlights (torch for video), general lighting (e.g. home, shop, office and studio lighting, theater/stage lighting and architectural lighting), Augmented Reality (AR) lighting, Virtual Reality (VR) lighting, backlighting as a display, and IR spectrometers. A single LED may provide light that is less bright than an incandescent light source, and thus, a multi-junction device or an LED array (such as a monolithic LED array, a micro LED array, etc.) may be used in applications where higher brightness is desired or needed.
Fig. 1A is a top view of an example LED array 102. In the example illustrated in fig. 1A, the LED array 102 is an array of emitters 120. The LED array may be used in any application, such as applications requiring precise control of the LED array emitters. The emitters 120 in the LED array 102 may be individually addressable or may be group/subset addressable.
Also shown in fig. 1A is an exploded view of a 3 x 3 portion of the LED array 102. As shown in the 3 x 3 partially exploded view, the LED array 102 may include emitters 120, each having a width w 1 . In an embodiment, the width w 1 And may be about 100 μm or less (e.g., 40 μm). The width of the channels 122 between the emitters 120 may be w 2 . In an embodiment, the width w 2 And may be about 20 μm or less (e.g., 5 μm). The channels 122 may provide an air gap between adjacent emitters, or may comprise other materials. Distance d from the center of one emitter 120 to the center of an adjacent emitter 120 1 And may be about 120 μm or less (e.g., 45 μm). It will be understood that the widths and distances provided herein are merely examples and that actual widths and/or dimensions may vary.
It will be appreciated that although rectangular emitters arranged in a symmetric matrix are shown in fig. 1A, emitters of any shape and arrangement may be applied to the embodiments described herein. For example, the LED array 102 of fig. 1A may include more than 20000 emitters in any suitable arrangement, such as a 200 x 100 matrix, a symmetric matrix, an asymmetric matrix, etc. It will also be appreciated that groups of emitters, matrices, and/or boards may be arranged in any suitable form to implement embodiments described herein.
As described above, an LED array (such as LED array 102) may comprise up to 20000 or more emitters. Such an array may have a 90 mm dimension 2 Or larger surface area and may require significant power to power them, such as 60 watts or more. An LED array like this may be referred to as a micro-LED array or simply micro-LED. The micro LEDs may comprise an array of individual emitters disposed on a substrate, or may be a single silicon wafer or die divided into segments (forming the emitters). The latter type of micro-LEDs may be referred to as monolithic LEDs.
In order to individually drive or control the individual LEDs in the array, a silicon backplane may be provided in the vicinity of the LED array and may become very hot during operation. Thus, heat dissipation can be challenging for such devices. While some solutions for heat dissipation of semiconductor devices are known, these solutions typically include a structure for dissipating heat through the top of the device. However, due to light emission, an LED array (such as LED array 102 of fig. 1A) may not be able to dissipate heat through the top of the device.
Additionally, LED arrays, such as LED array 102, may be used in applications such as vehicle headlamp systems, which may include passive elements (such as resistors and capacitors) that may form drivers, controllers, and other circuits. It may be desirable to package at least some of the passive components with the LED array.
Embodiments described herein may provide a low profile (profile) LED array package that may house one or more passive components and enable dissipation of heat generated by a silicon backplane and an LED array.
Fig. 1B is a cross-sectional view of an example LED lighting system 100. In the example illustrated in fig. 1B, the LED lighting system 100 includes a silicon backplane 104. The silicon backplate 104 has a top surface 101, a bottom surface 103, and side surfaces 105. The side surfaces 105 of the silicon backplate 104 are surrounded by a substrate 106 (formed of a molding material). The substrate 106 has a top surface 107, a bottom surface 109, and side surfaces 190. One or more metal layers 110 or redistribution layers (RDLs) (shown in the alternative embodiment of fig. 6E) are provided on the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106. RDL 117 may be formed on top surface 101 of silicon backplate 104 and at least a portion of top surface 107 of substrate 106. In the example illustrated in fig. 1B, RDL 117 includes two layers 116a and 116B of dielectric material 116 and a single metal layer 112. One or more vias 108 may extend through the substrate 106 and may be filled with a metallic material. The vias may thus form a continuous electrical connection between the silicon backplane 104, the RDL 117, and the metallization/RDL 110. An array of LEDs, such as the array of LEDs 102 of fig. 1A, may be disposed on the top surface 101 of the silicon backplane 104 and electrically coupled thereto via an array of metal connectors (not shown in fig. 1B). In an embodiment, the electronic components 114 may be disposed on the RDL 117 and electrically coupled to the LED lighting system 100 via the metal layer 112.
The LED array 102 may be a micro LED, such as described above with reference to fig. 1A. The LED array 102 may have a depth d 1. In an embodiment, the depth d1 may be, for example, between 5 μm and 250 μm.
The silicon backplane 104 may include circuitry and connectors for individually addressable connection to the emitters in the LED array 102. In an embodiment, the silicon backplane may be a Complementary Metal Oxide Semiconductor (CMOS) integrated circuit, which in an embodiment may be an Application Specific Integrated Circuit (ASIC). The silicon backplate 104 may have a depth d 3. In an embodiment, the depth d3 may be, for example, between 100 μm and 1 mm.
The structure consisting of silicon backplane 104, substrate 106, metallization/RDL 110, RDL 117, and vias 108 may have a depth d 2. In an embodiment, the depth d2 may be, for example, between 100 μm and 1 mm. Since the silicon backplane 104 is integrated into the substrate and the LED array 102 is disposed on top of the silicon backplane 104, the LED lighting system 100 may have a lower profile relative to a system in which one or more of these elements are vertically stacked.
In the example illustrated in fig. 1B, RDL 117 includes two layers 116a and 116B of dielectric material 116 and a single metal layer 112. A first layer 116a of the two layers of dielectric material 116 may be on the top surface 107 of the substrate 106 and at least a portion of the top surface 101 of the silicon backplate 104. The metal layer 112 may be patterned on the first layer 116a of dielectric material 116, such as by copper plating and copper etching. The second layer 116b of dielectric material 116 may be on top of the patterned metal layer 112 and on exposed portions of the first layer 116a of dielectric material 116. Although an RDL composed of two layers of dielectric material and a single layer of metal is shown in fig. 1B, one of ordinary skill in the art will recognize that RDL 117 may include more or fewer layers of dielectric material and/or more layers of metal, depending on design constraints. The dielectric material 116 may be any suitable dielectric material. In an embodiment, the dielectric material may be a polymer dielectric material (such as polyimide).
The RDL 117 may extend from a peripheral region of the silicon backplate 104 toward the side surface 190 of the substrate 106. This can both accommodate the LED array 102 (attached to the top surface 101 of the silicon backplane 104) in the central region, and can help dissipate heat by including a dielectric material that can further isolate the LED lighting system 100 from regions of highest heat area away from the center of the LED lighting system 100. Metal layer 112 may have portions exposed from dielectric material 116 to form bond pads. The metal layer 112 may include a portion that extends between the perimeter region of the silicon backplate 104 and the bond pads to create a continuous electrical connection therebetween. The bond pads may be electrically coupled to the vias 108 to create a continuous electrical connection between the top and bottom surfaces of the LED lighting system 100. The bond pads may be placed in a peripheral region of the substrate or spaced apart from but closer to the array (e.g., as shown in fig. 1C).
The metallization/RDL 110 may be formed in a number of different ways. In the example illustrated in fig. 1B, metallization/RDL 110 is a metal layer that includes a first portion electrically and thermally coupled to bottom surface 103 of silicon backplane 104 in a central region and a second portion fanning out from a peripheral region of silicon backplane 104 toward side surface 190 of substrate 106. In an embodiment, the first portion and the second portion may be electrically insulated from each other. Although not visible in fig. 1B, the second portion may extend from the silicon backplane 104 and join with a separate via 108 at a bond pad, thereby electrically coupling the silicon backplane 104 to the metal layer 112 on the top surface. Both the first and second portions of the metal layer 110 may be coupled to an external circuit board (not shown), such as by soldering. This may enable a direct connection between the LED lighting system 100 and an external circuit board, which provides improved heat dissipation through the bottom of the LED lighting system. Additionally, the structure may enable communication between the silicon backplane 104, the LED array 102, the passive components 114 on the substrate 106, and any electronic components on an external circuit board.
In another example (which will be described in more detail later with reference to fig. 6E and 7), the metallization/RDL 110 may be a combination of a metal layer and an RDL. As with the embodiment illustrated in fig. 1B, the metal layer may be electrically and thermally coupled to the bottom surface 103 of the silicon backplate 104 in the central region. However, the fanout may be implemented using RDLs rather than metal layers. In such an embodiment, LED lighting device 100 may have RDLs on both the top and bottom surfaces.
In both cases, the metallization/RDL 110 may be a thin structure compared to conventional silicon device packages, and may include much less dielectric material than conventional silicon device packages. For example, metal layer 100 in the embodiment shown in fig. 1B may be a single metal layer, and the RDL may include as few dielectric layers as possible. This may improve heat dissipation efficiency in such a package and enable packaging of micro LEDs and CMOS backplanes that may emit significant heat.
In the LED illumination system 100 illustrated in fig. 1B, the top surface 101 of the silicon back-plate 104 and the top surface 107 of the substrate 106 are coplanar. Similarly, the bottom surface 103 of the silicon backplate 104 and the bottom surface 109 of the substrate 106 are coplanar. This arrangement may allow for a package that is as thin as possible and easy to manufacture. However, one of ordinary skill in the art will recognize that because the substrate 106 is molded, the substrate 106 may take any shape, such as, for example, where the substrate has a top surface 107 that is higher than the top surface 101 of the silicon backplate 104, to further space the electronic components 114 from the high heat regions of the LED lighting system 100. Thus, in embodiments, the surfaces may not be coplanar.
Fig. 1C is a top view illustrating the top surface 130 of the example LED lighting system 100 of fig. 1B. In the example illustrated in fig. 1C, the top surface 130 of the LED lighting system includes the topmost layer 116b of dielectric material 116 in the RDL 117. An electronic component 114 is electrically coupled to the metal 112 in the RDL and is exposed from the dielectric material 116. In an embodiment, the electronic component 114 may not be electrically coupled to all areas of the metal 112, and thus, in an embodiment, the top surface 130 may also include some areas of the metal 112 exposed from the dielectric material 116. The top surface of at least a portion of the silicon backplate 104 is shown in fig. 1C and includes the portion of the top surface of the silicon backplate 104 not covered by the LED array 102 or the dielectric material 116. The top surface of the LED array 102 is also shown mounted on the top surface of the silicon backplane 104.
As shown in FIG. 1C, LED lighting system 100 has a length l 1 And width w 1 . In an embodiment, the length l 1 May be about 20 mm and has a width w 1 May be about 15 mm. The silicon backplate 104 may have a length l 2 And width w 2 . In an embodiment, the length l 2 May be about 15.5 mm and a width w 2 May be about 6.5 mm. The LED array 102 may have a length l 3 And width w 3 . In an embodiment, the length l 3 May be about 11 mm and has a width w 3 May be about 4.4 mm.
Given these example dimensions, a relatively large surface area (300 mm in the above example) may be provided 2 ) In which a relatively large amount of surface area is not occupied by the LED array (in the above example, the LED array has about 100 mm) 2 Surface area of). Thus, the design is of electronic components on the LED array packageThe attachment provides ample space.
FIG. 1D is a bottom view illustrating the bottom surface 140 of the example LED lighting system 100 of FIG. 1B. In the example illustrated in fig. 1D, the bottom surface 140 includes a region of the substrate 106 exposed from the molding material 106 and a region of the metal 110 or a pad coupled thereto. In an embodiment, some areas of the substrate may be covered by metallization and/or portions of the RDL interconnecting the silicon backplane and the bond pads (although these are not shown in fig. 1D). In some embodiments, the interconnect metal regions and/or RDLs may be covered by a dielectric material or other encapsulation or protection material (not shown in fig. 1D).
Fig. 2 is a cross-sectional view of an application system 200 incorporating the LED lighting system 100 of fig. 1B. The application system 200 may include a circuit board 150, the circuit board 150 having a plurality of bond pads 152. In the example illustrated in fig. 2, the exposed metal areas/bond pads of the RDL/metallization 110 of the LED lighting system 100 are directly bonded to the bond pads 152 of the circuit board 150. As described above, the direct bond between the metal layer 110 on the bottom surface of the silicon backplane 104 and the circuit board 150 enables efficient heat transfer from the LED lighting system 100 to the circuit board 150 for heat dissipation purposes without the need for additional heat dissipation structures above the top (or elsewhere) of the LED lighting system 100 (which might otherwise, for example, block light emission from the LED array 102). The circuit board 150 may be part of a larger system used in a particular application, such as a vehicle lighting or flash application (example vehicle lighting systems are described below with reference to fig. 3 and 4). In such a system, some of the passive components used in the application may be components 114 and may be disposed directly on LED lighting system 100 prior to attachment to circuit board 150. In addition to the heat sink, the circuit board 150 may include other circuit elements as needed for larger systems. RDL 117, RDL/metallization 110, and vias 108 may provide a continuous electrical connection between components 114, silicon backplane 104, and circuit board 150.
Fig. 3 is a diagram of an example vehicle headlamp system 300 that may incorporate the LED lighting system 100 of fig. 1B. The example vehicle headlamp system 300 illustrated in fig. 3 includes a power line 302, a data bus 304, an input filter and protection module 306, a bus transceiver 308, a sensor module 310, an LED direct current to direct current (DC/DC) module 312, a logic Low Dropout (LDO) module 314, a microcontroller 316, and an active headlamp 318. In an embodiment, active headlamp 318 may include an LED lighting system (such as LED lighting system 100 of fig. 1B). As described above, the LED lighting system 100 provides sufficient space and bond pads on the top surface of the substrate so that one, more, or all of the modules illustrated in fig. 3 can be housed on the top surface of the LED lighting system 100. Modules that are not disposed on the top surface of the LED lighting system 100 may be disposed on a circuit board 150 (as shown in fig. 2). In some embodiments, some electronic components of some or all of the modules in the vehicle lighting system 300 may be housed on the top surface of the LED lighting system 100, and some may be disposed on the circuit board 150 (as shown in fig. 2).
The power line 302 may have inputs to receive power from the vehicle and the data bus 304 may have inputs/outputs through which data may be exchanged between the vehicle and the vehicle headlamp system 300. For example, the vehicle headlamp system 300 may receive instructions from other locations in the vehicle, such as instructions to turn on a turn signal or turn on headlamps, and may send feedback to other locations in the vehicle, if desired. The sensor module 310 may be communicatively coupled to the data bus 304 and may provide additional data to the vehicle headlamp system 300 or other locations in the vehicle, such as relating to environmental conditions (e.g., time of day, rain, fog, or ambient light levels), vehicle status (e.g., parked, in motion, speed of motion, or direction of motion), and the presence/location of other objects (e.g., vehicles or pedestrians). A headlamp controller separate from any vehicle controller (communicatively coupled to the vehicle data bus) may also be included in the vehicle headlamp system 300. In fig. 3, the headlamp controller may be a microcontroller, such as microcontroller (μ c) 316. The microcontroller 316 may be communicatively coupled to the data bus 304.
The input filter and protection module 306 may be electrically coupled to the power line 302 and may, for example, support various filters to reduce conducted emissions and provide power immunity. In addition, the input filter and protection module 306 may provide electrostatic discharge (ESD) protection, load dump protection, alternator field decay protection, and/or reverse polarity protection.
The LED DC/DC module 312 may be coupled between the filter and protection module 306 and the active headlamp 318 to receive the filtered power and provide a drive current to power the LEDs in the LED array in the active headlamp 318. The LED DC/DC module 312 may have an input voltage between 7 and 18 volts, with a nominal voltage of approximately 13.2 volts, and an output voltage that may be slightly higher (e.g., 0.3 volts) than the maximum voltage of the LED array (e.g., determined by factory or local calibration and operating condition adjustments due to load, temperature, or other factors).
The logic LDO module 314 may be coupled to the input filter and protection module 306 to receive the filtered power. Logic LDO module 314 may also be coupled to microcontroller 314 and active headlamp 318 to provide power to a silicon backplane (e.g., CMOS logic) in microcontroller 314 and/or active headlamp 318.
The bus transceiver 308 may have, for example, a Universal Asynchronous Receiver Transmitter (UART) or a Serial Peripheral Interface (SPI) interface, and may be coupled to the microcontroller 316. Microcontroller 316 can convert vehicle inputs based on or including data from sensor module 310. The converted vehicle input may include a video signal that may be communicated to an image buffer in active headlamp module 318. In addition, the microcontroller 316 may load default image frames and tests for open/shorted pixels during startup. In an embodiment, the SPI interface may load the image buffer in CMOS. The image frames may be full frames, differential or partial frames. Other features of microcontroller 316 may include control interface monitoring of CMOS states, including die temperature, as well as logic LDO outputs. In an embodiment, the LED DC/DC output can be dynamically controlled to minimize headroom (headroom). In addition to providing image frame data, other headlamp functions, such as complementary use in conjunction with a side light (side marker) or turn signal light and/or activation of daytime running lights, may also be controlled.
Fig. 4 is a diagram of another example vehicle headlamp system 400. The example vehicle headlamp system 400 illustrated in fig. 4 includes an application platform 402, two LED illumination systems 406 and 408, and optics 410 and 412. The two LED lighting systems 406 and 408 may be LED lighting systems (such as the LED lighting system 100 of fig. 1B), or may include all or some of the LED lighting system 100 plus other modules in the vehicle headlamp system 300 of fig. 3. In the latter embodiment, the LED lighting systems 406 and 408 may be vehicle headlamp subsystems.
The LED illumination system 408 may emit a light beam 414 (shown between arrows 414a and 414b in fig. 4). The LED lighting system 406 may emit a light beam 416 (shown between arrows 416a and 416b in fig. 4). In the embodiment shown in fig. 4, the secondary optic 410 is adjacent to the LED illumination system 408, and light emitted from the LED illumination system 408 passes through the secondary optic 410. Similarly, secondary optic 412 is adjacent to LED illumination system 406, and light emitted from LED illumination system 412 passes through secondary optic 406. In an alternative embodiment, the secondary optic 410/412 is not provided in the vehicle headlamp system.
Where secondary optic 410/412 is included, secondary optic 410/412 may be or include one or more light guides. The one or more light guides may be edge-lit or may have an interior opening defining an interior edge of the light guide. The LED illumination systems 408 and 406 (or the active headlights of the vehicle headlight subsystem) may be embedded in the inner opening of the one or more light guides such that they inject light into the inner edge (inner opening light guide) or the outer edge (edge-lit light guide) of the one or more light guides. In embodiments, the one or more light guides may shape the light emitted by the LED illumination systems 408 and 406 in a desired manner, such as, for example, in a gradient, a chamfered distribution, a narrow distribution, a wide distribution, or an angular distribution.
The application platform 402 may provide power and/or data to the LED lighting systems 406 and/or 408 via lines 404, which lines 404 may include one or more or a portion of the power line 302 and the data bus 304 of fig. 3. One or more sensors (which may be sensors in system 300 or other additional sensors) may be internal or external to the housing of application platform 402. Alternatively or additionally, as shown in the example LED lighting system 300 of fig. 3, each LED lighting system 408 and 406 may include its own sensor module, connection and control module, power supply module, and/or LED array.
In an embodiment, the vehicle headlamp system 400 may represent an automobile with a steerable light beam, where the LEDs may be selectively activated to provide steerable light. For example, an array of LEDs (e.g., LED array 102) may be used to define or project a shape or pattern, or to illuminate only a selected portion of a roadway. In an example embodiment, the infrared camera or detector pixels within the LED systems 406 and 408 may be sensors (e.g., similar to the sensors in the sensor module 310 of fig. 3) that identify portions of the scene that require illumination (e.g., roads or crosswalks).
Fig. 5 is a flow chart of an example method 500 of manufacturing an LED lighting system, such as the LED lighting system 100 of fig. 1B. Fig. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I and 6J are cross-sectional views of an LED lighting system at various stages of a manufacturing method. In an embodiment, the method 500 may produce a panel-level packaged high-density LED lighting system.
In the example method 500 of fig. 5, a silicon backplane may be attached to a first carrier (502) to form a first structure. In an embodiment, the silicon backplane may be attached to a temporary (e.g., plastic) carrier via an adhesive material, such as tape or a temporary adhesive. An example 600A of a first structure is illustrated in fig. 6A and includes a silicon backplate 104, a first carrier 602, and an optional adhesive material 604.
A silicon backplate attached to the first carrier may be molded (504) to form a second structure. An example of a second structure 600B is illustrated in fig. 6B and includes the first structure 600A of fig. 6A, where the molding material surrounds the sides of the silicon backplate 104. The molding material forms a substrate 106 with an embedded silicon backplate 104. In an embodiment, a mold may be placed over the structure 600A, which is filled with a molding material and cured. Any excess molding material may be removed from the top surface of the silicon backplane if desired. In an embodiment, the molding may be a panel-level molding, the molding material may be a polymer material, and the second structure 600B may be a plastic substrate with an embedded silicon backplane on a temporary substrate.
One or more vias (506) may be formed through the substrate to form a third structure. In embodiments, the one or more vias may be formed using a laser or drilling. An example 600C of a third structure is illustrated in fig. 6C and includes a silicon backplate 104 embedded in a substrate 106, with two vias 108 formed through the substrate 106. At this stage, the silicon backplate 104 and the substrate 106 with the through holes 108 may remain attached to the first temporary carrier 602. The vias 108 may be filled with a metallic material.
At least one metal layer (508) may be formed on one surface of the silicon backplane and the substrate. This can be done in a number of different ways.
In some embodiments, a metal layer may be patterned or plated on one surface of the silicon backplane and the substrate to form the fourth structure. Fig. 6D illustrates an example 600D of a fourth structure, which includes a third structure having a metal layer 110. As can be seen in fig. 6D, the metal layer 110 forms a bond pad over a via and region extending from the perimeter region of the silicon backplane 104. A metal layer is also disposed on a central region of one surface of the silicon backplate 104. The bottom view of the LED lighting system 100 illustrated in fig. 1D shows such an example.
In other embodiments, a metal layer may be formed on one surface of the silicon backplane in the central region, and a redistribution layer may be formed on the one surface of the silicon backplane and the substrate adjacent the single metal layer to form the fifth structure. Fig. 6E illustrates an example of a fifth structure 600E, which includes a third structure having a single metal layer 618 and a redistribution layer 616. In the example illustrated in fig. 6E, redistribution layer 616 includes a layer of dielectric material 614 and metal layer 612. Although three metal layers are shown in fig. 6E, one, two, or more than three metal layers may be used if desired due to design limitations. For example, the redistribution layer may be formed by alternating deposition of layers of dielectric material, selective removal of portions of the dielectric material (if desired), and patterning of a metal layer on top. As can be seen in fig. 6E, the metal layer 612 begins at a peripheral region of one surface of the silicon backplane and extends toward a side surface of the substrate. Metal layer 612 is electrically coupled between silicon backplane 104 and the vias. A portion of the metal layer 612 is exposed from the dielectric material 614 to form a pad, or a separate pad may be formed on the outermost surface of the outermost dielectric layer.
Fig. 7 is a bottom view illustrating the bottom surface 700 of the LED lighting system of fig. 6E. Line 702 represents the outermost periphery of the substrate. Line 104 represents the outermost periphery of the area occupied by the silicon backplate 104 relative to the outermost periphery of the substrate. Dashed line 704 represents the boundary of the area between line 704 and the outermost perimeter of silicon backplate 104, which may be referred to herein as the perimeter area of silicon backplate 104. The metal layer 612 of the redistribution layer 616 may begin at the peripheral region and extend toward the side surface of the substrate (depicted by line 702). There is a gap between the boundary 704 of the perimeter region of the silicon backplane and a single metal layer 618 formed on one surface of the silicon backplane. The gap may be filled with a dielectric material, for example, as reflected in fig. 6E.
The structure formed as a result of 508 (e.g., the fourth or fifth structure) may be flipped over and attached to a second carrier (510) to form a sixth structure. In embodiments, the structure (e.g., the fourth or fifth structure) may be attached to a temporary (e.g., plastic) carrier via an adhesive material, such as tape or a temporary adhesive. The structure may be placed with at least one metal layer adjacent to the second carrier. An example 600G of a sixth structure is illustrated in fig. 6G and includes a second carrier 608 and an optional adhesive material 606. Once the structure is attached to the second carrier, the first carrier may be removed (512) to form a seventh structure. An example 600G of a seventh structure is shown in fig. 6G.
A redistribution layer and an array of metal connectors (514) may be formed on the surface exposed by removing the second carrier to form an eighth structure. In an embodiment, the array of metal connectors may be formed by plating or otherwise patterning or forming an array of copper pillar bumps on the surface. An example of an eighth structure 600H is illustrated in fig. 6H and includes a metal connector 640 and a redistribution layer 117, the redistribution layer 117 including at least one metal layer 112 and a dielectric material 116. As described above with reference to fig. 6E, the redistribution layer may be formed by alternating deposition of layers of dielectric material, selective removal of portions of the dielectric material (if desired), and patterning of the metal layer on top. In an embodiment, more than 20000 (e.g., about 28000) metal connectors may be formed on the surface.
The LED array may be attached to a silicon backplane (516) via electrical connectors to form a ninth structure. In an embodiment, this may be performed by aligning the silicon backplane with the electrical connector and applying heat to reflow the solder copper material in the copper pillar bumps. The backflow creates underfill (underfil) under the LED array. In an embodiment, the LED array may be a monolithic LED array. An example 600I of a ninth structure is illustrated in fig. 6I and includes LED array 102 and an underfill.
The LED array may undergo a laser lift-off (LLO) process and phosphor integration (518). Any passive components may be mounted on the exposed metal regions in the redistribution layer 117 to form the tenth structure. An example 600J of a tenth structure is illustrated in diagram 600J and includes LED array 102 with phosphor material 610 and passive components 114.
Optionally, a tenth structure (which may be an LED lighting system, such as LED lighting system 100 of fig. 1B) may be mounted on an external circuit board (520), for example, to incorporate LED lighting system 100 into a vehicle headlamp or other application system.
Having described embodiments in detail, those skilled in the art will appreciate that given the present description, modifications may be made to the embodiments described herein without departing from the spirit of the inventive concept. Therefore, it is intended that the scope of the invention not be limited to the particular embodiments illustrated and described.

Claims (20)

1. A system, comprising:
a silicon backplane having a top surface, a bottom surface, and side surfaces;
a substrate surrounding a side surface of the silicon backplate, the substrate having a top surface, a bottom surface, and a side surface;
at least one bond pad on a bottom surface of the substrate;
a metal layer on a bottom surface of the substrate and a bottom surface of the silicon backplate, the metal layer having a first portion electrically and thermally coupled to the bottom surface of the silicon backplate in a central region and a second portion extending between a peripheral region of the silicon backplate and the at least one bond pad; and
an array of metal connectors on a top surface of the silicon backplane.
2. The system of claim 1, further comprising at least one via through the substrate, the at least one via filled with a metallic material and electrically coupled to the at least one bond pad.
3. The system of claim 2, further comprising a redistribution layer on a top surface of the silicon backplane and a top surface of the substrate, the redistribution layer comprising:
at least one first dielectric layer, and
at least one first metal layer is provided on the substrate,
the at least one first metal layer extends from a peripheral region of the silicon backplane toward a side surface of the substrate and has at least a portion exposed from at least one dielectric layer to form at least one additional bond pad.
4. The system of claim 3, wherein the at least one additional bond pad is electrically coupled to the at least one via.
5. The system of claim 4, further comprising at least one passive component electrically coupled to the at least one bond pad.
6. The system of claim 1, further comprising an array of Light Emitting Diodes (LEDs) electrically coupled to the array of metal connectors on the top surface of the silicon backplane.
7. The system of claim 6, wherein the LED array is a monolithic LED array comprising a plurality of rows and columns of emitters, each emitter having a width of 100 μm or less, and channels between adjacent rows and columns having a width of 20 μm or less.
8. The system of claim 1, wherein the array of metal connectors is an array of copper pillar bumps.
9. The system of claim 1, wherein the substrate comprises a molding material.
10. The system of claim 1, wherein the silicon backplane is a Complementary Metal Oxide Semiconductor (CMOS) integrated circuit.
11. A system, comprising:
a silicon backplate having a top surface, a bottom surface, and side surfaces;
a substrate surrounding a side surface of the silicon backplate, the substrate having a top surface, a bottom surface, and a side surface;
a first metal layer electrically and thermally coupled to a bottom surface of the silicon backplate in a central region;
a redistribution layer on a bottom surface of the silicon backplane and a bottom surface of the substrate, the redistribution layer comprising at least one dielectric layer and at least one second metal layer extending from a perimeter region of the silicon backplane towards a side surface of the substrate and having at least a portion exposed from the at least one dielectric layer to form at least one bond pad; and
an array of metal connectors on a top surface of the silicon backplane.
12. The system of claim 11, further comprising at least one via through the substrate, the at least one via filled with a metallic material and electrically coupled to the at least one bond pad.
13. The system of claim 12, further comprising an additional redistribution layer on a top surface of the silicon backplane and a top surface of the substrate, the additional redistribution layer comprising:
at least one further dielectric layer, and
at least one third metal layer is formed on the first metal layer,
the at least one third metal layer extends from a peripheral region of the silicon backplane toward a side surface of the substrate and has at least a portion exposed from the at least one additional dielectric layer to form at least one additional bond pad.
14. The system of claim 13, wherein the at least one third metal layer is electrically coupled to the at least one via.
15. The system of claim 14, further comprising at least one passive component electrically coupled to the at least one additional bond pad.
16. The system of claim 11, further comprising an array of Light Emitting Diodes (LEDs) electrically coupled to the array of metal connectors on the top surface of the silicon backplane.
17. The system of claim 16, wherein the LED array is a monolithic LED array comprising a plurality of rows and columns of emitters, each emitter having a width of 100 μ ι η or less, and channels between adjacent rows and columns having a width of 20 μ ι η or less.
18. The system of claim 11, wherein the array of metal connectors is an array of copper pillar bumps.
19. The system of claim 11, wherein the substrate comprises a molding material.
20. The system of claim 11, wherein the silicon backplane is a Complementary Metal Oxide Semiconductor (CMOS) integrated circuit.
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