CN114944139B

CN114944139B - Multi-level output grid transfer circuit and display device

Info

Publication number: CN114944139B
Application number: CN202210753686.6A
Authority: CN
Inventors: 黄丽玉; 许雅琴; 顾小祥
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2023-07-25
Anticipated expiration: 2042-06-29
Also published as: CN114944139A

Abstract

The invention provides a multi-level output grid transfer circuit and a display device, wherein the multi-level output grid transfer circuit comprises multi-level grid transfer units, each level of grid transfer unit comprises a pre-charging module, a first output module, a second output module, a third output module, a pull-down module and a stabilizing module, the pre-charging module charges a first node according to a transfer signal output by an n-1 level grid transfer unit and a second grid signal output by the n-1 level grid transfer unit, the first output module outputs a first grid signal according to a first clock signal, the second output module outputs a second grid signal according to a second clock signal, the third output module outputs a transfer signal according to a transfer clock signal, the pull-down module pulls down the first node according to the transfer signal output by the n+1 level grid transfer unit and the first grid signal output by the n+1 level grid transfer unit, and the stabilizing module is used for maintaining a low level. The invention reduces the number of devices used for gate driving and improves the stability of the circuit.

Description

Multi-level output grid transfer circuit and display device

Technical Field

The present invention relates to the field of display driving technologies, and in particular, to a multi-level output gate transfer circuit and a display device.

Background

Display devices, such as liquid crystal display devices (Liquid Crystal Display, LCDs), have been widely used in electronic devices such as high-definition digital televisions, desktop computers, personal digital assistants, notebook computers, mobile phones, and digital cameras, as they are increasingly replacing conventional cathode ray tube displays due to their advantages of being light and thin, energy-saving, and non-radiative.

Today, the narrow frame display technology is rapid and starts to become the mainstream flat panel display technology. If the conventional a-Si-H TFT-LCD panel is adopted, the mobility of a-Si is low, the TFT characteristic floats greatly along with the variation of the manufacturing process, meanwhile, due to the threshold voltage drift characteristic of amorphous silicon, the characteristic degradation of a pull-down stable transistor can occur after the pull-down stable transistor is subjected to long-time bias, the stability of a circuit is poor due to the decrease of on-state current, and finally the circuit is invalid. Therefore, with the increase of resolution and panel load and the requirement of ultra-narrow frame, how to reduce layout occupation of the gate driving circuit and improve stability becomes a problem to be solved. Therefore, it is necessary to design a novel high-stability gate driving circuit, so as to improve the output capability and stability of the circuit and enable the circuit to exert stable output capability in a limited layout space.

Disclosure of Invention

In view of the above, the present invention provides a multi-level output gate transfer circuit and a display device, which can reduce the number of devices used for gate driving and improve the stability of the circuit.

The embodiment of the invention provides a multi-level output grid transfer circuit which comprises multi-level grid transfer units, wherein each level of grid transfer unit comprises a pre-charging module, a first output module, a second output module, a third output module, a pull-down module and a stabilizing module. The pre-charging module is connected with the first node and charges the first node according to the transmission signal output by the n-1 level grid transmission unit and the second grid signal output by the n-1 level grid transmission unit. The first output module is connected with the pre-charging module and is connected with the first node, and outputs a first grid signal at a first output end according to a first clock signal. The second output module is connected with the precharge module and is connected with the first node, a second grid signal is output at a second output end according to a second clock signal, the period and the duty ratio of the first clock signal and the second clock signal are the same, and the first grid signal and the second grid signal are sent to two adjacent grid lines of the display panel. The third output module is connected with the precharge module and is connected with the first node, a transmission signal is output at a third output end according to the transmission clock signal, and the high-level time period of the transmission clock signal comprises the high-level time period of the first clock signal and the high-level time period of the second clock signal. The pull-down module is connected with the pre-charging module and is connected with the first node, and the first node is pulled down to a low level according to the transmission signal output by the n+1th level grid transmission unit and the first grid signal output by the n+1th level grid transmission unit. The stabilizing module is connected with the first node, the first output end, the second output end and the third output end, and is used for simultaneously maintaining the first node, the first output end, the second output end and the third output end at a low level when the first node is pulled down to the low level.

Specifically, the precharge module includes a first switching element including a first control terminal receiving a transfer signal output from the n-1 st stage gate transfer unit, a first pass terminal receiving a second gate signal output from the n-1 st stage gate transfer unit, and a second pass terminal connected to the first node.

Specifically, the first output module includes a second switching element, the second switching element includes a second control end, a third path end, and a fourth path end, the second control end of the second switching element is connected to the first node, the third path end of the second switching element receives the first clock signal, and the fourth path end of the second switching element is connected to the first output end.

Specifically, the second output module includes a third switching element including a third control terminal, a fifth path terminal, and a sixth path terminal, the third control terminal of the third switching element being connected to the first node, the fifth path terminal of the third switching element receiving the second clock signal, the sixth path terminal of the third switching element being connected to the second output terminal.

Specifically, the third output module includes a fourth switching element, where the fourth switching element includes a fourth control end, a seventh path end, and an eighth path end, the fourth control end of the fourth switching element is connected to the first node, the seventh path end of the fourth switching element receives the transfer clock signal, and the eighth path end of the fourth switching element is connected to the third output end.

Specifically, the pull-down module includes a fifth switching element, where the fifth switching element includes a fifth control end, a ninth pass end, and a tenth pass end, the fifth control end of the fifth switching element receives the transfer signal output by the n+1th stage gate transfer unit, the ninth pass end of the fifth switching element is connected to the first node, and the tenth pass end of the fifth switching element receives the first gate signal output by the n+1th stage gate transfer unit.

Specifically, the stabilization module includes sixth to nineteenth switching elements. The sixth switching element includes a sixth control terminal, an eleventh pass terminal, and a twelfth pass terminal, the sixth control terminal of the sixth switching element receiving the first control signal, the eleventh pass terminal of the sixth switching element being coupled to the sixth control terminal of the sixth switching element, the twelfth pass terminal of the sixth switching element being coupled to the second node. The seventh switching element includes a seventh control terminal, a tenth pass terminal, and a fourteenth pass terminal, the seventh control terminal of the seventh switching element receiving the first control signal, the thirteenth pass terminal of the seventh switching element receiving a first low level signal, the fourteenth pass terminal of the seventh switching element being connected to a third node. The eighth switching element includes an eighth control terminal, a fifteenth pass terminal, and a sixteenth pass terminal, the eighth control terminal of the eighth switching element receiving the second control signal, the fifteenth pass terminal of the eighth switching element being connected to the third node, the sixteenth pass terminal of the eighth switching element being connected to the eighth control terminal of the eighth switching element. The ninth switching element includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal, the ninth control terminal of the ninth switching element receiving the second control signal, the seventeenth path terminal of the ninth switching element being connected to the second node, the eighteenth path terminal of the ninth switching element receiving the first low-level signal. The tenth switching element includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal, the tenth control terminal of the tenth switching element being connected to the first node, the nineteenth path terminal of the tenth switching element receiving the first low level signal, the twentieth path terminal of the tenth switching element being connected to the second node. The eleventh switching element includes an eleventh control terminal, a twenty-first path terminal, and a twenty-first path terminal, the eleventh control terminal of the eleventh switching element being connected to the first node, the twenty-first path terminal of the eleventh switching element receiving the first low level signal, the twenty-first path terminal of the eleventh switching element being connected to the third node. The twelfth switching element includes a twelfth control terminal, a twenty-fourth channel terminal, and a twenty-fourth channel terminal, the twelfth control terminal of the twelfth switching element being connected to the second node, the twenty-third channel terminal of the twelfth switching element being connected to the first node, the twenty-fourth channel terminal of the twelfth switching element receiving the first low-level signal. The thirteenth switching element includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal, the thirteenth control terminal of the thirteenth switching element being connected to the third node, the twenty-fifth path terminal of the thirteenth switching element receiving the first low level signal, the twenty-sixth path terminal of the thirteenth switching element being connected to the first node. The fourteenth switching element includes a fourteenth control terminal, a twenty-seventh path terminal, and a twenty-eighth path terminal, the fourteenth control terminal of the fourteenth switching element being connected to the second node, the twenty-seventh path terminal of the fourteenth switching element being connected to the first output terminal, the twenty-eighth path terminal of the fourteenth switching element receiving a second low-level signal. The fifteenth switching element includes a fifteenth control terminal, a twenty-ninth pass terminal, and a thirty-first pass terminal, the fifteenth control terminal of the fifteenth switching element being connected to the third node, the twenty-ninth pass terminal of the fifteenth switching element receiving the second low level signal, the thirty-first pass terminal of the fifteenth switching element being connected to the first output terminal. The sixteenth switching element includes a sixteenth control terminal, a thirty-first path terminal, and a thirty-first path terminal, the sixteenth control terminal of the sixteenth switching element being connected to the second node, the thirty-first path terminal of the sixteenth switching element being connected to the second output terminal, the thirty-first path terminal of the sixteenth switching element receiving the second low-level signal. The seventeenth switching element includes a seventeenth control terminal, a thirty-third channel terminal, and a thirty-fourth channel terminal, the seventeenth control terminal of the seventeenth switching element being connected to the third node, the thirty-third channel terminal of the seventeenth switching element receiving the second low-level signal, the thirty-fourth channel terminal of the seventeenth switching element being connected to the second output terminal. The eighteenth switching element includes an eighteenth control terminal, a thirty-fifth path terminal, and a thirty-sixth path terminal, the eighteenth control terminal of the eighteenth switching element being connected to the second node, the thirty-fifth path terminal of the eighteenth switching element being connected to the third output terminal, the thirty-sixth path terminal of the eighteenth switching element receiving the second low-level signal. The nineteenth switching element includes a nineteenth control terminal connected to the third node, a thirty-seventh pass terminal that receives the second low level signal, and a thirty-eighth pass terminal connected to the third output terminal.

Specifically, the first control signal and the second control signal are opposite in polarity and are inverted in polarity once per frame.

Specifically, the gate transfer unit further includes a first capacitor and a second capacitor, a first end of the first capacitor is connected to the first node, a second end of the first capacitor is connected to the first output end, a first end of the second capacitor is connected to the first node, and a second end of the second capacitor is connected to the second output end.

Specifically, the duty cycle of the first clock signal and the second clock signal is 25%.

The embodiment of the invention also provides a display device which comprises the multi-stage output grid transfer circuit.

The multistage output grid transfer circuit and the display device provided by the invention have the advantages that the number of devices used for grid driving is reduced, the layout area is further reduced, and the stability of the circuit is improved.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.

Drawings

Fig. 1 is a circuit diagram of a gate transfer unit according to an embodiment of the invention.

FIG. 2 is a timing diagram of a multi-level output gate pass unit of the embodiment of FIG. 1.

FIG. 3 is a block diagram of a cascade of multi-stage output gate pass circuits according to an embodiment of the invention.

FIG. 4 is a timing diagram of the clock signal and the gate signal of an embodiment of FIG. 3.

Fig. 5 is a block diagram of an 8-stage output connection of a multi-stage output gate pass circuit according to an embodiment of the present invention.

FIG. 6 is a full-level connection block diagram of the multi-level output gate pass circuit of one embodiment of the invention.

Detailed Description

In order to further describe the technical means and effects adopted by the present invention for achieving the intended purpose, the following detailed description refers to the specific implementation, method, steps, structure, characteristics and effects of the multi-level output gate transfer circuit and the display device according to the present invention with reference to the accompanying drawings and preferred embodiments.

The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments, which proceeds with reference to the accompanying drawings. While the invention may be susceptible to further details of embodiments and examples of means and effects for achieving the desired purpose, the drawings are provided for the purpose of reference and illustration only and are not intended to be limiting.

Fig. 1 is a circuit diagram of a gate transfer unit according to an embodiment of the invention. Referring to fig. 1, the multi-stage output gate transfer circuit of the present embodiment includes multi-stage gate transfer units, each of which includes: a precharge module 10, a first output module 20, a second output module 40, a third output module 30, a pull-down module 50, and a stabilization module 60.

In the embodiment of the invention, the current gate transfer unit is assumed to be an nth stage gate transfer unit, G2n-1, G2n, zn respectively represent a first gate signal, a second gate signal and a transfer signal output by the nth stage gate transfer unit, g2n+1, g2n+2, zn+1 respectively represent a first gate signal, a second gate signal and a transfer signal output by a next (n+1) th stage gate transfer unit of the present (nth) stage gate transfer unit, and G2n-3, G2n-2, zn-1 respectively represent a first gate signal, a second gate signal and a transfer signal output by a previous (n-1) th stage gate transfer unit of the present (nth) stage gate transfer unit.

The precharge module 10 is connected to the first node Q, and charges the first node Q according to the transfer signal Zn-1 output by the n-1 th stage gate transfer unit and the second gate signal G2n-2 output by the n-1 th stage gate transfer unit.

The first output module 20 is connected to the first node Q with the precharge module 10, and outputs a first gate signal G2n-1 at a first output terminal according to the first clock signal CLK 1.

The second output module 40 is connected to the first node Q with the precharge module 10, and outputs a second gate signal G2n at a second output terminal according to the second clock signal CLK2, wherein the periods and the duty ratios of the first clock signal CLK1 and the second clock signal CLK2 are the same, and the first gate signal G2n-1 and the second gate signal G2n are sent to two adjacent gate lines of the display panel.

The third output module 30 is connected to the first node Q and outputs a transfer signal Zn at a third output terminal according to a transfer clock signal CLKA, wherein the high level period of the transfer clock signal CLKA includes a high level period of the first clock signal CLK1 and a high level period of the second clock signal CLK 2.

The pull-down module 50 is connected to the first node Q with the precharge module 10, and pulls down the first node Q to a low level according to the transfer signal zn+1 output by the n+1th stage gate transfer unit and the first gate signal g2n+1 output by the n+1th stage gate transfer unit.

The stabilizing module 60 is connected to the first node Q, the first output terminal, the second output terminal, and the third output terminal, and the stabilizing module 60 is configured to maintain the first node Q, the first output terminal, the second output terminal, and the third output terminal at a low level when the first node Q is pulled down to a low level.

It should be noted that, since the first-stage gate transfer unit 110 has no previous-stage gate transfer unit, the second gate signal G2n-2 outputted from the n-1-th-stage gate transfer unit and the transfer signal Zn-1 outputted from the n-1-th-stage gate transfer unit required by the precharge module 10 of the first-stage gate transfer unit 110 are required to be provided by external signal circuits, such as the start signal STV1 and the start signal STV2 directly provided by the timing control circuit or provided via the source driving circuit. Since the last-stage gate transfer unit does not have the next-stage gate transfer unit, the first gate signal g2n+1 outputted from the n+1th-stage gate transfer unit and the transfer signal zn+1 outputted from the n+1th-stage gate transfer unit required by the pull-down module 50 of the last-stage gate transfer unit are required to be supplied by external signal circuits, for example, the end signal STV3 and the end signal STV4 directly supplied by a timing control circuit or supplied via a source driving circuit.

In an embodiment of the present invention, the precharge module 10 may include a first switching element T1, the first switching element T1 includes a first control terminal, a first pass terminal and a second pass terminal, the first control terminal of the first switching element T1 receives the transmission signal Zn-1 outputted by the n-1 th stage gate transmission unit, the first pass terminal of the first switching element T1 receives the second gate signal G2n-2 outputted by the n-1 th stage gate transmission unit, and the second pass terminal of the first switching element T1 is connected to the first node Q.

In an embodiment of the present invention, the first output module 20 may include a second switching element T2, where the second switching element T2 includes a second control terminal, a third channel terminal and a fourth channel terminal, the second control terminal of the second switching element T2 is connected to the first node Q, the third channel terminal of the second switching element T2 receives the first clock signal CLK1, and the fourth channel terminal of the second switching element T2 is connected to the first output terminal.

In an embodiment of the present invention, the second output module 40 may include a third switching element T3, where the third switching element T3 includes a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switching element T3 is connected to the first node Q, the fifth path terminal of the third switching element T3 receives the second clock signal CLK2, and the sixth path terminal of the third switching element T3 is connected to the second output terminal.

In an embodiment of the present invention, the third output module 30 may include a fourth switching element T4, where the fourth switching element T4 includes a fourth control terminal, a seventh pass terminal and an eighth pass terminal, the fourth control terminal of the fourth switching element T4 is connected to the first node Q, the seventh pass terminal of the fourth switching element T4 receives the transfer clock signal CLKA, and the eighth pass terminal of the fourth switching element T4 is connected to the third output terminal.

In an embodiment of the present invention, the pull-down module 50 may include a fifth switching element T5, where the fifth switching element T5 includes a fifth control terminal, a ninth pass terminal and a tenth pass terminal, the fifth control terminal of the fifth switching element T5 receives the transmission signal zn+1 output by the n+1th stage gate transmission unit, the ninth pass terminal of the fifth switching element T5 is connected to the first node Q, and the tenth pass terminal of the fifth switching element T5 receives the first gate signal g2n+1 output by the n+1th stage gate transmission unit.

In one embodiment of the present invention, the stabilization module 60 may include: a sixth switching element T6, a seventh switching element T7, an eighth switching element T8, a ninth switching element T9, a tenth switching element T10, an eleventh switching element T11, a twelfth switching element T12, a thirteenth switching element T13, a fourteenth switching element T14, a fifteenth switching element T15, a sixteenth switching element T16, a seventeenth switching element T17, an eighteenth switching element T18, and a nineteenth switching element T19.

The sixth switching element T6 includes a sixth control terminal, an eleventh pass terminal, and a tenth pass terminal, the sixth control terminal of the sixth switching element T6 receiving the first control signal V1, the eleventh pass terminal of the sixth switching element T6 being connected to the sixth control terminal of the sixth switching element T6, the twelfth pass terminal of the sixth switching element T6 being connected to the second node QB1. The seventh switching element T7 includes a seventh control terminal, a tenth pass terminal, and a tenth four-pass terminal, the seventh control terminal of the seventh switching element T7 is connected to the eleventh pass terminal of the sixth switching element T6, receives the first control signal V1, the thirteenth pass terminal of the seventh switching element T7 receives the first low-level signal VSQ, and the fourteenth pass terminal of the seventh switching element T7 is connected to the third node QB2. The eighth switching element T8 includes an eighth control terminal, a fifteenth pass terminal, and a sixteenth pass terminal, the eighth control terminal of the eighth switching element T8 receiving the second control signal V2, the fifteenth pass terminal of the eighth switching element T8 being connected to the third node QB2, the sixteenth pass terminal of the eighth switching element T8 being connected to the eighth control terminal of the eighth switching element T8. The ninth switching element T9 includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal, the ninth control terminal of the ninth switching element T9 being connected to the sixteenth path terminal of the eighth switching element T8, receiving the second control signal V2, the seventeenth path terminal of the ninth switching element T9 being connected to the second node QB1, the eighteenth path terminal of the ninth switching element T9 receiving the first low level signal VSQ. The tenth switching element T10 includes a tenth control terminal, a nineteenth pass terminal, and a twentieth pass terminal, the tenth control terminal of the tenth switching element T10 being connected to the first node Q, the nineteenth pass terminal of the tenth switching element T10 receiving the first low level signal VSQ, the twentieth pass terminal of the tenth switching element T10 being connected to the second node QB1. The eleventh switching element T11 includes an eleventh control terminal, a twenty-first pass terminal, and a twenty-first pass terminal, the eleventh control terminal of the eleventh switching element T11 being connected to the first node Q, the twenty-first pass terminal of the eleventh switching element T11 being connected to the nineteenth pass terminal of the tenth switching element T10, receiving the first low level signal VSQ, the twenty-first pass terminal of the eleventh switching element T11 being connected to the third node QB2.

The twelfth switching element T12 includes a twelfth control terminal, a twenty-third channel terminal, and a twenty-fourth channel terminal, the twelfth control terminal of the twelfth switching element T12 is connected to the second node QB1, the twenty-third channel terminal of the twelfth switching element T12 is connected to the first node Q, and the twenty-fourth channel terminal of the twelfth switching element T12 receives the first low-level signal VSQ. The thirteenth switching element T13 includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal, the thirteenth control terminal of the thirteenth switching element T13 being connected to the third node QB2, the twenty-fifth path terminal of the thirteenth switching element T13 being connected to the twenty-fourth path terminal of the twelfth switching element T12, receiving the first low level signal VSQ, the twenty-sixth path terminal of the thirteenth switching element T13 being connected to the first node Q. The fourteenth switching element T14 includes a fourteenth control terminal, a twenty-seventh path terminal, and a twenty-eighth path terminal, the fourteenth control terminal of the fourteenth switching element T14 is connected to the second node QB1, the twenty-seventh path terminal of the fourteenth switching element T14 is connected to the first output terminal, and the twenty-eighth path terminal of the fourteenth switching element T14 receives the second low level signal VGL. The fifteenth switching element T15 includes a fifteenth control terminal, a twenty-ninth pass terminal, and a thirty-eighth pass terminal, the fifteenth control terminal of the fifteenth switching element T15 is connected to the third node QB2, the twenty-ninth pass terminal of the fifteenth switching element T15 is connected to the twenty-eighth pass terminal of the fourteenth switching element T14, the thirty-eighth pass terminal of the fifteenth switching element T15 is connected to the first output terminal, and receives the second low level signal VGL. The sixteenth switching element T16 includes a sixteenth control terminal, a thirty-first pass terminal, and a thirty-first pass terminal, the sixteenth control terminal of the sixteenth switching element T16 is connected to the second node QB1, the thirty-first pass terminal of the sixteenth switching element T16 is connected to the second output terminal, and the thirty-first pass terminal of the sixteenth switching element T16 receives the second low-level signal VGL. The seventeenth switching element T17 includes a seventeenth control terminal, a thirty-third channel terminal, and a thirty-fourth channel terminal, the seventeenth control terminal of the seventeenth switching element T17 is connected to the third node QB2, the thirty-third channel terminal of the seventeenth switching element T17 is connected to the thirty-third channel terminal of the sixteenth switching element T16, the thirty-fourth channel terminal of the seventeenth switching element T17 is connected to the second output terminal, and receives the second low level signal VGL. The eighteenth switching element T18 includes an eighteenth control terminal, a thirty-fifth path terminal, and a thirty-sixth path terminal, the eighteenth control terminal of the eighteenth switching element T18 is connected to the second node QB1, the thirty-fifth path terminal of the eighteenth switching element T18 is connected to the third output terminal, and the thirty-sixth path terminal of the eighteenth switching element T18 receives the second low-level signal VGL. The nineteenth switching element T19 includes a nineteenth control terminal, a thirty-seventh path terminal, and a thirty-eighth path terminal, the nineteenth control terminal of the nineteenth switching element T19 is connected to the third node QB2, the thirty-seventh path terminal of the nineteenth switching element T19 is connected to the thirty-sixth path terminal of the eighteenth switching element T18, the thirty-eighth path terminal of the nineteenth switching element T19 is connected to the third output terminal, and receives the second low-level signal VGL.

In an embodiment of the present invention, the first control signal V1 and the second control signal V2 are low-frequency clock signals (i.e. the frequency thereof is lower than that of the clock signals), and the first control signal V1 and the second control signal V2 are alternately high-level, so that when the first control signal V1 is high-level, the second control signal V2 is low-level; when the second control signal V2 is at a high level, the first control signal V1 is at a low level. In an embodiment of the present invention, the polarity of the first control signal V1 is opposite to that of the second control signal V2, and the polarities are reversed once every frame. Then, in the stable phase, the first control signal V1 controls the sixth switching element T6 and the seventh switching element T7 to be in a turned-on state and charges the second node QB1 through the turned-on sixth switching element T6 and the turned-on seventh switching element T7 discharges the third node QB2 to the first low level VSQ, or the second control signal V2 controls the eighth switching element T8 and the ninth switching element T9 to be in a turned-on state and charges the third node QB2 through the turned-on eighth switching element T8 and discharges the second node QB1 to the first low level VSQ through the turned-on ninth switching element T9. Accordingly, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be at a high-low level such that the twelfth switching element T12, the fourteenth switching element T14, the sixteenth switching element T16, the eighteenth switching element T18, and the thirteenth switching element T13, the fifteenth switching element T15, the seventeenth switching element T17, the nineteenth switching element T19 connected to the third node QB2 are alternately turned on with each other. Thus, the first node Q alternately receives the first low level signal VSQ through the connected twelfth switching element T12 and thirteenth switching element T13, the first output terminal alternately receives the second low level signal VGL through the connected fourteenth switching element T14 and fifteenth switching element T15, the second output terminal alternately receives the second low level signal VGL through the connected sixteenth switching element T16 and seventeenth switching element T17, and the third output terminal alternately receives the second low level signal VGL through the connected eighteenth switching element T18 and nineteenth switching element T19, thereby achieving a stable low level effect.

In an embodiment of the present invention, the gate transfer unit further includes a first capacitor C1 and a second capacitor C2, wherein a first end of the first capacitor C1 is connected to the first node Q, a second end of the first capacitor C1 is connected to the first output terminal, a first end of the second capacitor C2 is connected to the first node Q, and a second end of the second capacitor C2 is connected to the second output terminal.

In an embodiment of the present invention, the first capacitor C1 may be, but not limited to, an external capacitor between the first node Q and the first output terminal, so that the effect of pulling up the voltage of the first node Q can be improved by using the coupling effect of the capacitor. In an embodiment of the present invention, the second capacitor C2 may be, but not limited to, an external capacitor between the first node Q and the second output terminal, so that the effect of pulling up the voltage of the first node Q can be improved by using the coupling effect of the capacitor.

In one embodiment of the present invention, the duty cycle of the first clock signal CLK1 and the second clock signal CLK2 may be, but are not limited to, 25%. Thus, in the multi-stage gate transfer units of the multi-stage output gate transfer circuit, the gate transfer units of the odd-numbered rows receive the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA of the first group, and the gate transfer units of the even-numbered rows receive the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA of the second group, so that the multi-stage output gate transfer circuit can continuously output the four-stage gate signals within one period of the clock signals through the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA of the two groups. A person skilled in the art may obtain other similar technical solutions according to this embodiment, for example, the duty ratio of the second clock signal CLK2 and the first clock signal CLK1 is set to 33.3%, so that the multi-stage gate transfer unit of the multi-stage output gate transfer circuit corresponds to three groups of the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA, and the gate transfer unit of each stage receives the same group of the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA, and then the multi-stage output gate transfer circuit can continuously output six-stage gate signals in one period of the clock signals through the three groups of the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA.

In an embodiment of the present invention, the first to nineteenth switching elements T1 to T19 may be, but are not limited to, N-type TFTs, NMOS transistors, N-type transistors, or the like. The first to nineteenth control terminals of the first to nineteenth switching elements T1 to T19 are gates. The corresponding pass terminals of the first to nineteenth switching elements T1 to T19 are drain or source.

The embodiments of the present invention and the operation principle thereof will be specifically described below taking the first to nineteenth switching elements T1 to T19 as N-type TFTs, and the duty ratios of the first clock signal CLK1 and the second clock signal CLK2 being 25% as an example.

FIG. 2 is a timing diagram of a multi-level output gate pass unit of the embodiment of FIG. 1. The operation of the gate transfer unit of the present embodiment will be described below with reference to fig. 1 and 2, wherein the operation of the gate transfer unit includes four phases, namely, a precharge phase, an output phase, a pull-down phase, and a stabilization phase:

a precharge phase:

at time t1, when the transfer signal Zn-1 output by the n-1 th stage gate transfer unit jumps from low level to high level, the precharge module 10 controls the first node Q to receive the second gate signal G2n-2 output by the n-1 th stage gate transfer unit. At time t2, the first node Q charges when the second gate signal G2n-2 output from the n-1 th stage gate transfer unit transitions from a low level to a high level. Thus, the first node Q may be stably pulled up to a high level, so that the first, second and third output modules 20, 40 and 30 enter an operating state.

In an embodiment, at time T1, the first control terminal of the first switching element T1 receives the transfer signal Zn-1 output by the n-1 th stage gate transfer unit, and jumps from low level to high level, so that the first switching element T1 becomes in an on state. Thus, the first node Q connected to the second path terminal of the first switching element T1 receives the second gate signal G2n-2 output from the n-1 th stage gate transfer unit on the first path terminal of the first switching element T1 through the turned-on first switching element T1. Then at time t2 the first node Q charges when the second gate signal G2n-2 transitions from a low level to a high level.

In an embodiment, when the first node Q is charged and pulled up to a high level, the second control terminal of the second switching element T2, the third control terminal of the third switching element T3, and the fourth control terminal of the fourth switching element T4 connected to the first node Q become high levels, and then the second switching element T2, the third switching element T3, and the fourth switching element T4 become conductive, thereby enabling the first output module 20, the second output module 40, and the third output module 30 to enter an operating state.

In an embodiment, when the first node Q is charged and pulled up to a high level, the tenth control terminal of the tenth switching element T10 and the eleventh control terminal of the eleventh switching element T11 connected to the first node Q become high levels, and the tenth switching element T10 and the eleventh switching element T11 become conductive, so that the second node QB1 connected to the twentieth pass terminal of the tenth switching element T10 receives the first low level signal VSQ on the nineteenth pass terminal of the tenth switching element T10 through the conductive tenth switching element T10, and the third node QB2 connected to the twenty first pass terminal of the eleventh switching element T11 receives the first low level signal VSQ on the twenty first pass terminal of the eleventh switching element T11 through the conductive eleventh switching element T11. When the second node QB1 and the third node QB2 are at low level, the respective control terminals of the twelfth to nineteenth switching elements T12 to T19 are at low level, and the twelfth to nineteenth switching elements T12 to T19 are in an off state, the stabilizing module 60 enters a non-operating state, and has no influence on the first, second and third output terminals.

Output stage:

at time t3, the first node Q is pulled up to a high level, and transitions from a low level to a high level according to the first clock signal CLK1, and the first output terminal of the first output module 20 receives the first clock signal CLK1 and outputs the first gate signal G2n-1 at the first output terminal. In an embodiment, the fourth channel terminal of the second switching element T2 is connected to the first output terminal, and the first output terminal receives the first clock signal CLK1 on the third channel terminal of the second switching element T2 through the turned-on second switching element T2, so that the first output terminal outputs the first gate signal G2n-1. In an embodiment, the first node Q is further bootstrapped and pulled up (charge pump) by the first capacitor C1, so that the level of the first node Q is further raised, and the second switching element T2 is fully opened.

At time t4, according to the transition of the second clock signal CLK2 from the low level to the high level, the second output terminal of the second output module 40 receives the second clock signal CLK2 and outputs the second gate signal G2n at the second output terminal. In an embodiment, the sixth path terminal of the third switching element T3 is connected to the second output terminal, and the second output terminal receives the second clock signal CLK2 on the fifth path terminal of the third switching element T3 through the turned-on third switching element T3, so that the second output terminal outputs the second gate signal G2n. In an embodiment, the second capacitor C2 is further used to bootstrap-pull up (charge pump) the first node Q, so that the level of the first node Q is further raised, and the third switching element T3 is fully turned on.

Meanwhile, since the high level period of the transfer clock signal CLKA includes the high level period of the first clock signal CLK1 and the high level period of the second clock signal CLK2, it is possible to transition to the high level according to the low level of the first clock, the transfer clock signal CLKA also transitions to the high level from the low level, and when the high level of the second clock transitions to the low level, the transfer clock signal CLKA also transitions to the low level from the high level. The third output terminal of the third output module 30 receives the transfer clock signal CLKA and outputs the transfer signal Zn at the third output terminal. In an embodiment, the eighth path terminal of the fourth switching element T4 is connected to the third output terminal, and the third output terminal receives the transfer clock signal CLKA on the seventh path terminal of the fourth switching element T4 through the turned-on fourth switching element T4, so that the third output terminal outputs the transfer signal Zn.

And (3) a pull-down stage:

at time t5, when the transfer signal zn+1 output by the n+1th stage gate transfer unit jumps from low level to high level, the pull-down module 50 controls the first node Q to receive the first gate signal g2n+1 output by the n+1th stage gate transfer unit, and at time t6, when the first gate signal g2n+1 output by the n+1th stage gate transfer unit jumps from high level to low level, the first node Q pulls down. Thus, the first node Q may be stably pulled down to a low level, so that the first, second and third output modules 20, 40 and 30 enter a non-operating state.

In an embodiment, at time T5, the fifth control terminal of the fifth switching element T5 receives the transfer signal zn+1 output by the n+1th stage gate transfer unit, and jumps from low level to high level, so that the fifth switching element T5 becomes in an on state. Thus, the first node Q connected to the ninth pass terminal of the fifth switching element T5 receives the first gate signal g2n+1 output from the n+1th stage gate transfer unit on the tenth pass terminal of the fifth switching element T5 through the turned-on fifth switching element T5. Then at time t6, the first node Q is pulled down when the first gate signal g2n+1 transitions from a high level to a low level.

In an embodiment, when the first node Q is pulled down to a low level, the second control terminal of the second switching element T2, the third control terminal of the third switching element T3, and the fourth control terminal of the fourth switching element T4 connected to the first node Q become low levels, and then the second switching element T2, the third switching element T3, and the fourth switching element T4 become off states, thereby causing the first output module 20, the second output module 40, and the third output module 30 to enter the inactive states.

In an embodiment, when the first node Q is pulled down to a low level, the tenth control terminal of the tenth switching element T10 and the eleventh control terminal of the eleventh switching element T11 connected to the first node Q become low levels, and the tenth switching element T10 and the eleventh switching element T11 become off states. Meanwhile, since the first control signal V1 and the second control signal V2 are opposite in polarity, the first control signal V1 controls the sixth switching element T6 and the seventh switching element T7 to be in a turned-on state and charges the second node QB1 through the turned-on sixth switching element T6 and discharges the third node QB2 to the first low level VSQ through the turned-on seventh switching element T7, or the second control signal V2 controls the eighth switching element T8 and the ninth switching element T9 to be in a turned-on state and charges the third node QB2 through the turned-on eighth switching element T8 and discharges the second node QB1 to the first low level VSQ through the turned-on and ninth switching element T9 to be turned-on. Accordingly, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be at a high-low level such that the twelfth switching element T12, the fourteenth switching element T14, the sixteenth switching element T16, the eighteenth switching element T18, and the thirteenth switching element T13, the fifteenth switching element T15, the seventeenth switching element T17, the nineteenth switching element T19 connected to the third node QB2 are alternately turned on with each other. Thus, the first node Q alternately receives the first low level signal VSQ through the connected twelfth switching element T12 and thirteenth switching element T13, the first output terminal alternately receives the second low level signal VGL through the connected fourteenth switching element T14 and fifteenth switching element T15, the second output terminal alternately receives the second low level signal VGL through the connected sixteenth switching element T16 and seventeenth switching element T17, and the third output terminal alternately receives the second low level signal VGL through the connected eighteenth switching element T18 and nineteenth switching element T19, thereby achieving a stable low level effect.

Stabilization phase:

in the two time periods before the time t1 and after the time t7, the precharge module 10 enters the non-working state when the transfer signal Zn-1 output by the n-1 gate transfer unit received by the precharge module 10 is at a low level, and similarly, the transfer signal zn+1 output by the n+1 gate transfer unit received by the pull-down module 50 enters the non-working state when the pull-down module 50 is at a low level. Thus, the precharge module 10 and the pull-down module 50 have no influence on the first node Q, and the stabilization module 60 may be used to maintain the first node Q, the first output terminal, the second output terminal, and the third output terminal at low levels.

In an embodiment, in two periods before the time T1 and after the time T7, the first node Q is pulled down to a low level, and then the second control terminal of the second switching element T2, the third control terminal of the third switching element T3, and the fourth control terminal of the fourth switching element T4 connected to the first node Q are at a low level, and then the second switching element T2, the third switching element T3, and the fourth switching element T4 are in an off state, so that the first output module 20, the second output module 40, and the third output module 30 enter a non-operating state.

In an embodiment, in two periods before the time T1 and after the time T7, the first node Q has been pulled down to a low level, the tenth control terminal of the tenth switching element T10 and the eleventh control terminal of the eleventh switching element T11 connected to the first node Q are at a low level, and the tenth switching element T10 and the eleventh switching element T11 are in an off state. Meanwhile, since the first control signal V1 and the second control signal V2 are opposite in polarity, the first control signal V1 controls the sixth switching element T6 and the seventh switching element T7 to be in a turned-on state and charges the second node QB1 through the turned-on sixth switching element T6 and discharges the third node QB2 to the first low level VSQ through the turned-on seventh switching element T7, or the second control signal V2 controls the eighth switching element T8 and the ninth switching element T9 to be in a turned-on state and charges the third node QB2 through the turned-on eighth switching element T8 and discharges the second node QB1 to the first low level VSQ through the turned-on and ninth switching element T9 to be turned-on. Accordingly, the first control signal V1 and the second control signal V2 alternately control the second node QB1 and the third node QB2 to be at a high-low level, so that the twelfth switching element T12, the fourteenth switching element T14, the sixteenth switching element T16, the eighteenth switching element T18, and the thirteenth switching element T13, the fifteenth switching element T15, the seventeenth switching element T17, and the nineteenth switching element T19 connected to the second node QB1 are alternately turned on with each other. Thus, the first node Q alternately receives the first low level signal VSQ through the connected twelfth switching element T12 and thirteenth switching element T13, the first output terminal alternately receives the second low level signal VGL through the connected fourteenth switching element T14 and fifteenth switching element T15, the second output terminal alternately receives the second low level signal VGL through the connected sixteenth switching element T16 and seventeenth switching element T17, and the third output terminal alternately receives the second low level signal VGL through the connected eighteenth switching element T18 and nineteenth switching element T19, thereby achieving a stable low level effect.

Thus, in the stabilization phase, regardless of how the transfer signal Zn-1 outputted from the n-1 th stage gate transfer unit and the second gate signal G2n-2 outputted from the n-1 st stage gate transfer unit received by the precharge module 10 change, the transfer signal zn+1 outputted from the n+1 th stage gate transfer unit and the first gate signal g2n+1 outputted from the n+1 th stage gate transfer unit received by the pull-down module 50 change, and how the first clock signal CLK1, the second clock signal CLK2 and the transfer clock signal CLKA change, the stabilization module 60 can maintain the first node Q, the first output terminal, the second output terminal and the third output terminal at low levels, and can release charges such as parasitic capacitances of the second switching element T2 coupled due to clock feedthrough, thereby ensuring stability of the first node Q and the outputted first gate signal G2n-1 and the second gate signal G2 n. In addition, in the precharge stage, each voltage pull-up on the first node Q is performed on the first low level signal VSQ, so that the pull-up voltage is relatively stable, and a drift phenomenon of the voltage of the first node Q is prevented, so that the voltage of the first node Q is more stable, the stability of the circuit is improved, and the reliability of display is improved. In an embodiment, the voltages of the second node QB1 and the third node QB2 are more stable, so that the working states of the connected switching elements are more stable, the influence of the ambient temperature on the circuit is reduced, namely, the voltage drift exceeds a certain threshold value when the temperature is too high or too low, and the working of the connected switching elements is abnormal; in addition, the voltages of the second node QB1 and the third node QB2 are more stable, and the related timing designs of the second node QB1 and the third node QB2 are widened.

FIG. 3 is a block diagram of a cascade of multi-stage output gate pass circuits according to an embodiment of the invention. FIG. 4 is a timing diagram of the clock signal and the gate signal of an embodiment of FIG. 3. As shown in fig. 3, the gate transfer circuit includes a plurality of gate transfer units in the embodiment of fig. 1, and the gate transfer circuit includes four gate transfer units as an example. The transfer signal Zn-1 outputted from the n-1 th stage gate transfer unit and the second gate signal G2n-2 outputted from the n-1 st stage gate transfer unit required by the precharge module 10 in the first stage gate transfer unit 110 may be replaced by the start signal STV1 and the start signal STV2, respectively, and the first stage gate transfer unit 110 receives the transfer clock signal CLKA, the first clock signal CLK1, the second clock signal CLK2, the first control signal V1, the second control signal V2, the first low level signal VSQ, the second low level signal VGL, the start signal STV1, the start signal STV2, and the first gate signal G3 and the transfer signal Z2 outputted from the second stage gate transfer unit 120 and outputs the first gate signal G1, the second gate signal G2, and the transfer signal Z1 of the present stage. The second stage gate transfer unit 120 receives the transfer clock signal CLKA, the first clock signal CLK1, the second clock signal CLK2, the first control signal V1, the second control signal V2, the first low level signal VSQ, the second low level signal VGL, the second gate signal G2 and the transfer signal Z1 output by the first stage gate transfer unit 110, and the first gate signal G5 and the transfer signal Z3 output by the third stage gate transfer unit 130, and outputs the first gate signal G3, the second gate signal G4, and the transfer signal Z2 of the present stage. The third stage gate transfer unit 130 receives the transfer clock signal CLKA, the first clock signal CLK1, the second clock signal CLK2, the first control signal V1, the second control signal V2, the first low level signal VSQ, the second low level signal VGL, the second gate signal G4 and the transfer signal Z2 output by the second stage gate transfer unit 120, and the first gate signal G7 and the transfer signal Z4 output by the fourth stage gate transfer unit 140, and outputs the first gate signal G5, the second gate signal G6 and the transfer signal Z3 of the present stage. The transfer signal zn+1 outputted from the n+1th stage gate transfer unit and the first gate signal g2n+1 outputted from the n+1th stage gate transfer unit required by the pull-down module 50 of the fourth stage gate transfer unit 140 may be replaced by the end signal STV3 and the end signal STV4, respectively, and the fourth stage gate transfer unit 140 receives the transfer clock signal CLKA, the first clock signal CLK1, the second clock signal CLK2, the first control signal V1, the second control signal V2, the first low level signal VSQ, the second low level signal VGL, the second gate signal G6 and the transfer signal Z3 outputted from the third stage gate transfer unit 130, the end signal STV3 and the end signal STV4, and outputs the first gate signal G7, the second gate signal G8 and the transfer signal Z4 of the present stage.

In this embodiment, as shown in fig. 4, the multi-level output gate pass circuit may receive six clock signals VA, VB, VC, VD, VE and VF. The gate transfer units of the odd-numbered rows receive the first clock signal CLK1 of the first group as the clock signal VA, the second clock signal CLK2 of the first group as the clock signal VB and the transferred clock signal CLKA of the first group as the clock signal VE, and the gate transfer units of the even-numbered rows receive the first clock signal CLK1 of the second group as the clock signal VC, the second clock signal CLK2 of the second group as the clock signal VD and the transferred clock signal of the second group as the clock signal VF. As shown in fig. 4, the clock periods of the six clock signals are the same, and the first clock signal CLK1 of the first group, the second clock signal CLK2 of the first group, the first clock signal CLK1 of the second group, and the second clock signal CLK2 of the second group may be clock signals with a duty ratio of 25%, the second clock signal CLK2 of the first group is one phase later than the first clock signal CLK1 of the first group, the second clock signal CLK2 of the second group is one phase later than the first clock signal CLK1 of the second group, the first clock signal CLK1 of the second group is one phase later than the second clock signal CLK2 of the first group, one phase is T/4, and T is the period of the clock signals; the first set of transferred clock signals CLKA and the second set of transferred clock signals CLKA may each be 50% duty cycle clock signals, the second set of transferred clock signals CLKA being two phases later than the first set of transferred clock signals CLKA.

In this embodiment, the operation of the gate transfer unit in the gate transfer circuit may refer to the gate transfer unit in the embodiment of fig. 1, and will not be described herein. As shown in fig. 4, the gate signals output by the gate transfer circuit are separated from each other by the same time and have the same signal shape, and can be quickly pulled up to a high level and then quickly pulled down to a low level, so that the gate signals can be stably provided to the gate lines of the display panel.

In addition, as can be seen from the cascade connection of the multi-stage output gate transfer circuits in fig. 3, in the multi-stage output gate transfer circuit of this embodiment, the gate transfer unit of this stage needs to receive the second gate signal G2n-2 output by the n-1 th stage gate transfer unit and the transfer signal Zn-1 output by the n-1 th stage gate transfer unit, and the first gate signal g2n+1 output by the n+1 th stage gate transfer unit and the transfer signal zn+1 output by the n+1 th stage gate transfer unit. Therefore, the first grid electrode transmission unit above can be used as the first-stage grid electrode transmission unit from top to bottom, and a starting signal STV1 and a starting signal STV2 are provided, so that the multi-stage output grid electrode transmission circuit can output grid electrode signals from top to bottom to perform forward scanning of the display panel; alternatively, the first gate transfer unit below may be used as the first stage gate transfer unit, and the start signal STV1 and the start signal STV2 may be provided, so that the multi-stage output gate transfer circuit may output the gate signal from bottom to top to perform the reverse scan of the display panel. Therefore, the multi-stage output gate transfer circuit of the present embodiment can be used for the forward and backward scanning of the display panel.

Fig. 5 is a block diagram of an 8-stage output connection of a multi-stage output gate pass circuit according to an embodiment of the present invention. As shown in fig. 5, the multi-stage output gate transfer circuit of this embodiment may be provided with a plurality of gate transfer units on the left side of the display panel, may be provided with a plurality of gate transfer units on the right side of the display panel, and may be provided with four gate transfer units on the left side of the display panel, and may be provided with four gate transfer units on the right side of the display panel, and may respectively provide 4 clock signals with a duty ratio of 25% as the corresponding first clock signal CLK1 and the second clock signal CLK2, 2 clock signals with a duty ratio of 50% as the corresponding transfer clock signal CLKA, one first low level signal VSQ, one second low level signal VGL, one first control signal V1, one second control signal V2, two start signals STV1 and STV2, and two end signals STV3 and STV4. The operation of the multi-stage output gate transfer circuit of the present embodiment may refer to the multi-stage output gate transfer circuit of the embodiment of fig. 3, and will not be described herein.

In an embodiment, the gate transfer unit on the left side and the gate transfer unit on the right side can provide gate signals to different gate lines of the display panel, and the gate signals are provided on the opposite side to the single side, so that the occupation of the layout area on one side can be avoided.

In an embodiment, the gate transfer unit on the left side and the gate transfer unit on the right side can provide gate signals to the left side and the right side on the same gate line of the display panel, and the gate signals are provided on the opposite side, so that image anomalies caused by voltage drop of the gate signals on the gate line can be avoided, all the thin film transistors connected on the gate line are opened quickly, and quick image display is facilitated.

FIG. 6 is a full-level connection block diagram of the multi-level output gate pass circuit of one embodiment of the invention. As shown in fig. 6, the multi-stage output gate transfer circuit of the present embodiment may further include a signal providing module 200, where the signal providing module 200 is configured to provide corresponding input signals to the plurality of gate transfer units, and the signal providing module 200 may be composed of a multi-stage substrate gate driving circuit and signal lines. In an embodiment, the signal providing module 200 is disposed at the middle of the plurality of gate transfer units, so that the plurality of gate transfer units may be connected upward and downward, respectively, and/or the plurality of gate transfer units may be connected leftward and rightward, respectively. Taking the multi-level output gate transfer circuit shown in fig. 6 as an example, the signal providing module 200 is provided with four gate transfer units on the upper left side, the lower left side, the upper right side and the lower right side, and the four gate transfer units on each of the four sides are all 8-level output connections, so that the signal providing module 200 may connect the gate transfer units on each side and provide input signals for each side, including 4 clock signals with a duty ratio of 25% as the corresponding first clock signal CLK1 and the second clock signal CLK2, 2 clock signals with a duty ratio of 50% as the corresponding transfer clock signal CLKA, one first low level signal VSQ, one second low level signal VGL, one first control signal V1, one second control signal V2. In an embodiment, the signal providing module 200 may further provide two end signals STV3 and STV4 for each of the fourth gate transfer units located at the upper left and upper right sides, and two start signals STV1 and STV2 for each of the first gate transfer units located at the lower left and lower right sides; accordingly, the first gate transfer units on the upper left and upper right sides each require two start signals STV1 and STV2 to be supplied from other external signal circuits, and the fourth gate transfer units on the lower left and lower right sides each require two end signals STV3 and STV4 to be supplied from other external signal circuits. The operation of the multi-stage output gate transfer circuit of the present embodiment may refer to the multi-stage output gate transfer circuit of the embodiment of fig. 3, and will not be described herein.

Based on the same inventive concept, the embodiment of the present invention also provides a display device including the multi-level output gate transfer circuit provided in the above embodiment for providing gate signals to gate lines of a display panel. The implementation of the display device can be referred to the embodiment of the multi-level output gate transfer circuit, and the repetition is not repeated.

According to the multi-stage output grid transfer circuit and the display device, each stage of grid transfer unit can output two stages of grid signals and transfer signals, the number of devices used for grid driving can be reduced, the stability of the circuit can be improved, and the multi-stage output grid transfer circuit can be used for forward and backward scanning of a display panel.

The present invention is not limited to the preferred embodiments, but is capable of modification and variation in detail, and is intended to cover modifications, equivalents and variations of the above embodiments in accordance with the principles of the present invention, without departing from the scope of the invention.

Claims

1. A multi-level output gate transfer circuit comprising a multi-level gate transfer unit, wherein each level of the gate transfer unit comprises:

the precharge module (10), the said precharge module (10) links with first node (Q), according to the transmission signal (Zn-1) that the n-1 gate transmission unit outputs and second gate signal (G2 n-2) that the n-1 gate transmission unit outputs, charge the said first node (Q);

the first output module (20), the said first output module (20) links to each other with said precharge module (10) to connect to said first node (Q), according to the first clock signal (CLK 1), output the first grid signal (G2 n-1) at the first output end;

a second output module (40), wherein the second output module (40) is connected with the precharge module (10) and is connected with the first node (Q), a second gate signal (G2 n) is output at a second output end according to a second clock signal (CLK 2), the period and the duty ratio of the first clock signal (CLK 1) and the second clock signal (CLK 2) are the same, and the first gate signal (G2 n-1) and the second gate signal (G2 n) are sent to two adjacent gate lines of the display panel;

a third output module (30), the third output module (30) being connected to the precharge module (10) and being connected to the first node (Q), the third output module outputting a transfer signal (Zn) according to a transfer clock signal (CLKA), the high level period of the transfer clock signal (CLKA) comprising the high level period of the first clock signal (CLK 1) and the high level period of the second clock signal (CLK 2);

A pull-down module (50), wherein the pull-down module (50) is connected with the precharge module (10) and is used for pulling down the first node (Q) to a low level according to a transmission signal (Zn+1) output by an n+1th-stage gate transmission unit and a first gate signal (G2n+1) output by the n+1th-stage gate transmission unit;

-a stabilizing module (60), said stabilizing module (60) being connected to said first node (Q), said first output, said second output and said third output, said stabilizing module (60) being adapted to simultaneously maintain said first node (Q), said first output, said second output and said third output at a low level when said first node (Q) is pulled down to a low level;

wherein the stabilization module (60) comprises:

a sixth switching element (T6), the sixth switching element (T6) comprising a sixth control terminal, an eleventh pass terminal and a twelfth pass terminal, the sixth control terminal of the sixth switching element (T6) receiving the first control signal (V1), the eleventh pass terminal of the sixth switching element (T6) being connected to the sixth control terminal of the sixth switching element (T6), the twelfth pass terminal of the sixth switching element (T6) being connected to the second node (QB 1);

A seventh switching element (T7), the seventh switching element (T7) comprising a seventh control terminal, a tenth pass terminal and a fourteenth pass terminal, the seventh control terminal of the seventh switching element (T7) being connected to the eleventh pass terminal of the sixth switching element (T6), receiving the first control signal (V1), the thirteenth pass terminal of the seventh switching element (T7) receiving a first low level signal (VSQ), the fourteenth pass terminal of the seventh switching element (T7) being connected to a third node (QB 2);

-an eighth switching element (T8), the eighth switching element (T8) comprising an eighth control terminal, a fifteenth pass terminal and a sixteenth pass terminal, the eighth control terminal of the eighth switching element (T8) receiving a second control signal (V2), the fifteenth pass terminal of the eighth switching element (T8) being connected to the third node (QB 2), the sixteenth pass terminal of the eighth switching element (T8) being connected to the eighth control terminal of the eighth switching element (T8);

a ninth switching element (T9), the ninth switching element (T9) including a ninth control terminal, a seventeenth pass terminal, and an eighteenth pass terminal, the ninth control terminal of the ninth switching element (T9) being connected to the sixteenth pass terminal of the eighth switching element (T8) and receiving the second control signal (V2), the seventeenth pass terminal of the ninth switching element (T9) being connected to the second node (QB 1), the eighteenth pass terminal of the ninth switching element (T9) receiving the first low level signal (VSQ);

A tenth switching element (T10), the tenth switching element (T10) including a tenth control terminal, a nineteenth pass terminal, and a twentieth pass terminal, the tenth control terminal of the tenth switching element (T10) being connected to the first node (Q), the nineteenth pass terminal of the tenth switching element (T10) receiving the first low level signal (VSQ), the twentieth pass terminal of the tenth switching element (T10) being connected to the second node (QB 1);

an eleventh switching element (T11), the eleventh switching element (T11) including an eleventh control terminal, a twenty-first pass terminal, and a twenty-second pass terminal, the eleventh control terminal of the eleventh switching element (T11) being connected to the first node (Q), the twenty-first pass terminal of the eleventh switching element (T11) being connected to the nineteenth pass terminal of the tenth switching element (T10), receiving the first low level signal (VSQ), the twenty-second pass terminal of the eleventh switching element (T11) being connected to the third node (QB 2);

a twelfth switching element (T12), the twelfth switching element (T12) including a twelfth control terminal, a twenty-third channel terminal, and a twenty-fourth channel terminal, the twelfth control terminal of the twelfth switching element (T12) being connected to the second node (QB 1), the twenty-third channel terminal of the twelfth switching element (T12) being connected to the first node (Q), the twenty-fourth channel terminal of the twelfth switching element (T12) receiving the first low-level signal (VSQ);

A thirteenth switching element (T13), the thirteenth switching element (T13) including a thirteenth control terminal, a twenty-fifth pass terminal, and a twenty-sixth pass terminal, the thirteenth control terminal of the thirteenth switching element (T13) being connected to the third node (QB 2), the twenty-fifth pass terminal of the thirteenth switching element (T13) being connected to the twenty-fourth pass terminal of the twelfth switching element (T12), receiving the first low-level signal (VSQ), the twenty-sixth pass terminal of the thirteenth switching element (T13) being connected to the first node (Q);

a fourteenth switching element (T14), the fourteenth switching element (T14) including a fourteenth control terminal, a twenty-seventh pass terminal, and a twenty-eighth pass terminal, the fourteenth control terminal of the fourteenth switching element (T14) being connected to the second node (QB 1), the twenty-seventh pass terminal of the fourteenth switching element (T14) being connected to the first output terminal, the twenty-eighth pass terminal of the fourteenth switching element (T14) receiving a second low level signal (VGL);

a fifteenth switching element (T15), the fifteenth switching element (T15) including a fifteenth control terminal, a twenty-ninth pass terminal, and a thirty-first pass terminal, the fifteenth control terminal of the fifteenth switching element (T15) being connected to the third node (QB 2), the twenty-ninth pass terminal of the fifteenth switching element (T15) being connected to the twenty-eighth pass terminal of the fourteenth switching element (T14) to receive the second low-level signal (VGL), the thirty-first pass terminal of the fifteenth switching element (T15) being connected to the first output terminal;

A sixteenth switching element (T16), the sixteenth switching element (T16) including a sixteenth control terminal, a thirty-first pass terminal, and a thirty-first pass terminal, the sixteenth control terminal of the sixteenth switching element (T16) being connected to the second node (QB 1), the thirty-first pass terminal of the sixteenth switching element (T16) being connected to the second output terminal, the thirty-first pass terminal of the sixteenth switching element (T16) receiving the second low level signal (VGL);

a seventeenth switching element (T17), the seventeenth switching element (T17) including a seventeenth control terminal, a thirty-third channel terminal, and a thirty-fourth channel terminal, the seventeenth control terminal of the seventeenth switching element (T17) being connected to the third node (QB 2), the thirty-third channel terminal of the seventeenth switching element (T17) being connected to the thirty-third channel terminal of the sixteenth switching element (T16) for receiving the second low level signal (VGL), the thirty-fourth channel terminal of the seventeenth switching element (T17) being connected to the second output terminal;

an eighteenth switching element (T18), the eighteenth switching element (T18) including an eighteenth control terminal, a thirty-fifth pass terminal and a thirty-sixth pass terminal, the eighteenth control terminal of the eighteenth switching element (T18) being connected to the second node (QB 1), the thirty-fifth pass terminal of the eighteenth switching element (T18) being connected to the third output terminal, the thirty-sixth pass terminal of the eighteenth switching element (T18) receiving the second low-level signal (VGL);

A nineteenth switching element (T19), the nineteenth switching element (T19) including a nineteenth control terminal, a thirty-seventh pass terminal, and a thirty-eighth pass terminal, the nineteenth control terminal of the nineteenth switching element (T19) being connected to the third node (QB 2), the thirty-seventh pass terminal of the nineteenth switching element (T19) being connected to the thirty-sixth pass terminal of the eighteenth switching element (T18), receiving the second low level signal (VGL), the thirty-eighth pass terminal of the nineteenth switching element (T19) being connected to the third output terminal.

2. The multi-level output gate transfer circuit of claim 1, wherein the precharge module (10) includes a first switching element (T1), the first switching element (T1) including a first control terminal, a first pass terminal, and a second pass terminal, the first control terminal of the first switching element (T1) receiving a transfer signal (Zn-1) output by an n-1 th level gate transfer unit, the first pass terminal of the first switching element (T1) receiving a second gate signal (G2 n-2) output by an n-1 th level gate transfer unit, the second pass terminal of the first switching element (T1) being connected to the first node (Q).

3. The multi-level output gate transfer circuit of claim 1, wherein the first output module (20) includes a second switching element (T2), the second switching element (T2) including a second control terminal, a third channel terminal, and a fourth channel terminal, the second control terminal of the second switching element (T2) being connected to the first node (Q), the third channel terminal of the second switching element (T2) receiving the first clock signal (CLK 1), the fourth channel terminal of the second switching element (T2) being connected to the first output terminal.

4. The multi-level output gate transfer circuit of claim 1, wherein the second output module (40) includes a third switching element (T3), the third switching element (T3) including a third control terminal, a fifth pass terminal, and a sixth pass terminal, the third control terminal of the third switching element (T3) being connected to the first node (Q), the fifth pass terminal of the third switching element (T3) receiving the second clock signal (CLK 2), the sixth pass terminal of the third switching element (T3) being connected to the second output terminal.

5. The multi-level output gate transfer circuit of claim 1, wherein the third output module (30) comprises a fourth switching element (T4), the fourth switching element (T4) comprising a fourth control terminal, a seventh pass terminal and an eighth pass terminal, the fourth control terminal of the fourth switching element (T4) being connected to the first node (Q), the seventh pass terminal of the fourth switching element (T4) receiving the transfer clock signal (CLKA), the eighth pass terminal of the fourth switching element (T4) being connected to the third output terminal.

6. The multi-level output gate transfer circuit of claim 1, wherein the pull-down module (50) includes a fifth switching element (T5), the fifth switching element (T5) including a fifth control terminal, a ninth pass terminal, and a tenth pass terminal, the fifth control terminal of the fifth switching element (T5) receiving the transfer signal (zn+1) output by the n+1th level gate transfer unit, the ninth pass terminal of the fifth switching element (T5) being connected to the first node (Q), the tenth pass terminal of the fifth switching element (T5) receiving the first gate signal (g2n+1) output by the n+1th level gate transfer unit.

7. The multi-level output gate transfer circuit of claim 1 wherein the first control signal (V1) and the second control signal (V2) are of opposite polarity and are all inverted in polarity once per frame.

8. The multi-level output gate transfer circuit of claim 1, wherein the gate transfer unit further comprises a first capacitor (C1) and a second capacitor (C2), a first end of the first capacitor (C1) is connected to the first node (Q), a second end of the first capacitor (C1) is connected to the first output terminal, a first end of the second capacitor (C2) is connected to the first node (Q), and a second end of the second capacitor (C2) is connected to the second output terminal.

9. A display device comprising a multi-level output gate transfer circuit as claimed in any one of claims 1 to 8.