CN112365851A - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN112365851A CN112365851A CN202011266597.6A CN202011266597A CN112365851A CN 112365851 A CN112365851 A CN 112365851A CN 202011266597 A CN202011266597 A CN 202011266597A CN 112365851 A CN112365851 A CN 112365851A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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Abstract
The application provides a GOA circuit and display panel, the GOA circuit includes the GOA unit of multistage cascade setting, each grade the GOA unit is including pull-up control unit, pull-up unit, drop-down unit, first drop-down maintain unit, second drop-down maintain unit, reverser unit and feedback unit. In the GOA circuit that this application provided, each grade GOA unit all can realize a plurality of signal output that have different chronogenesis to drive the inside pixel compensation circuit of display panel, and then realize the design of narrow frame.
Description
Technical Field
The application relates to the technical field of display, in particular to a GOA circuit and a display panel.
Background
The Gate driver Array (GOA) is a driving method in which a Gate driver circuit is integrated on an Array substrate of a display panel to implement progressive scanning, so that the Gate driver circuit can be omitted, and the Array substrate Gate driver Array has the advantages of reducing production cost and implementing narrow frame design of the panel, and is used for various displays.
In the driving method, an AMOLED (Active Matrix Organic Light Emitting diode) belongs to a current driving type and is sensitive to electrical variation of a transistor, and uniformity and drift of a threshold voltage Vth of the transistor affect accuracy and uniformity of image Display.
In the pixel compensation circuit in the prior art, a plurality of signals with different time sequences are often required to be driven, so that a plurality of sets of GOA circuits are required to be arranged in the display panel, which is not beneficial to realizing a narrow frame.
Disclosure of Invention
The application provides a GOA circuit and display panel to need to set up many sets of GOA circuit in solving prior art display panel, be unfavorable for realizing the technical problem of narrow frame.
The application provides a GOA circuit, it includes multistage cascaded GOA unit, and every grade GOA unit all includes: the device comprises a pull-up control unit, a pull-up unit, a pull-down unit, a first pull-down maintaining unit, a second pull-down maintaining unit, an inverter unit and a feedback unit;
the pull-up control unit is connected to a first scanning signal and a first clock signal of a previous stage, is electrically connected to a first node and a second node, and is used for pulling up the potential of the first node under the control of the first scanning signal and the first clock signal of the previous stage;
the pull-up unit is connected to a second clock signal, a third clock signal and a fourth clock signal, is electrically connected to the first node, the current-stage first scanning signal output end, the current-stage second scanning signal output end and the current-stage enable signal output end, and is used for outputting the current-stage first scanning signal, the current-stage second scanning signal and the current-stage enable signal under the control of the potential of the first node, the second clock signal, the third clock signal and the fourth clock signal;
the pull-down unit is connected to a next-stage first scanning signal and a reference low level signal, is electrically connected to the first node and the second node, and is used for pulling down the potential of the first node under the control of the next-stage first scanning signal and the reference low level signal;
the first pull-down maintaining unit is connected to the reference low level signal, electrically connected to the first node, the second node and the third node, and configured to maintain a potential of the first node after the pull-down unit pulls down the potential of the first node;
the second pull-down maintaining unit is connected to the reference low level signal and the reference high level signal, and is electrically connected to the third node, the current-stage first scanning signal output end, the current-stage second scanning signal output end and the current-stage enable signal output end, and is configured to maintain the potentials of the current-stage first scanning signal, the current-stage second scanning signal and the current-stage enable signal under the control of the potential of the third node, the reference low level signal and the reference high level signal;
the inverter unit is connected to the reference high level signal, electrically connected to the first node and the third node, and configured to keep a potential of the third node opposite to a potential of the first node;
the feedback unit is connected to the reference high level signal, electrically connected to the first node and the second node, and configured to pull up a potential of the second node under control of the potential of the first node and the reference high level signal.
In the GOA circuit provided by the present application, the pull-up control unit includes a first transistor and a second transistor;
the grid electrode of the first transistor and the grid electrode of the second transistor are both connected to the first clock signal; the source electrode of the first transistor is connected with the upper-stage first scanning signal; the drain electrode of the first transistor and the source electrode of the second transistor are both electrically connected to the second node; the drain of the second transistor is electrically connected to the first node.
In the GOA circuit provided in the present application, the pull-up unit includes a bootstrap capacitor, a third transistor, a fourth transistor, and a fifth transistor;
the first end of the bootstrap capacitor, the gate of the third transistor, the gate of the fourth transistor and the gate of the fifth transistor are all electrically connected to the first node; the source electrode of the third transistor is connected to the second clock signal; the drain electrode of the third transistor and the second end of the bootstrap capacitor are both electrically connected to the current-stage first scanning signal output end; the source electrode of the fourth transistor is connected to the third clock signal; the drain electrode of the fourth transistor is electrically connected to the current-stage second scanning signal output end; the source electrode of the fifth transistor is connected with the fourth clock signal; and the drain electrode of the fifth transistor is electrically connected to the current-stage enable signal output end.
In the GOA circuit provided by the present application, the pull-down unit includes a sixth transistor and a seventh transistor;
the grid electrode of the sixth transistor and the grid electrode of the seventh transistor are both connected to the next-stage first scanning signal; the source electrode of the sixth transistor is connected with the reference low-level signal; the drain electrode of the sixth transistor and the source electrode of the seventh transistor are both electrically connected to the second node; the drain of the seventh transistor is electrically connected to the first node.
In the GOA circuit provided in the present application, the first pull-down sustain unit includes an eighth transistor and a ninth transistor;
the gate of the eighth transistor and the gate of the ninth transistor are both electrically connected to the third node; the source electrode of the eighth transistor is connected with the reference low-level signal; the drain of the eighth transistor and the source of the ninth transistor are both electrically connected to the second node; the drain of the ninth transistor is electrically connected to the first node.
In the GOA circuit provided by the present application, the second pull-down sustain unit includes a tenth transistor, an eleventh transistor, and a twelfth transistor;
a gate of the tenth transistor, a gate of the eleventh transistor, and a gate of the twelfth transistor are all electrically connected to the third node; a source electrode of the tenth transistor and a source electrode of the eleventh transistor are both connected to the reference low-level signal; the drain of the tenth transistor is electrically connected to the current-stage first scanning signal output end; the drain electrode of the eleventh transistor is electrically connected to the current-stage second scanning signal output end; the source electrode of the twelfth transistor is connected with the reference high-level signal; and the drain electrode of the twelfth transistor is electrically connected to the current-stage enable signal output end.
In the GOA circuit provided by the present application, the inverter unit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
the grid electrode of the thirteenth transistor, the source electrode of the thirteenth transistor and the source electrode of the fourteenth transistor are all connected with the reference high-level signal; the drain electrode of the thirteenth transistor, the grid electrode of the fourteen transistor and the drain electrode of the fifteenth transistor are connected; a drain of the fourteenth transistor and a drain of the sixteenth transistor are both electrically connected to the third node; a gate of the fifteenth transistor and a source of the sixteenth transistor are both electrically connected to the first node; a source of the fifteenth transistor and a source of the sixteenth transistor are both coupled to the reference low level signal.
In the GOA circuit provided by the present application, the feedback unit includes a seventeenth transistor;
a gate of the seventeenth transistor is electrically connected to the first node; the source electrode of the seventeenth transistor is connected with the reference high-level signal; the drain of the seventeenth transistor is electrically connected to the second node.
In the GOA circuit provided by the application, the transistors in the GOA unit are all indium gallium zinc oxide thin film transistors.
Correspondingly, the application also provides a display panel, which comprises the GOA circuit described in any one of the above.
The application provides a GOA circuit and display panel, the GOA circuit includes the GOA unit of multistage cascade setting, each the GOA unit is including pull-up control unit, pull-up unit, drop-down unit, first drop-down maintain unit, second drop-down maintain unit, reverser unit and feedback unit. And each GOA unit can output a current-stage first scanning signal, a current-stage second scanning signal and a current-stage enable signal with different time sequences so as to drive a pixel compensation circuit in the display panel, thereby realizing narrow-frame design.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a circuit schematic of a pixel compensation circuit provided herein;
FIG. 2 is a signal timing diagram of a pixel compensation circuit provided in the present application;
fig. 3 is a schematic structural diagram of a GOA unit in the GOA circuit provided in the present application;
fig. 4 is a schematic circuit diagram of a GOA unit in the GOA circuit provided in the present application;
fig. 5 is a signal voltage value of the GOA unit provided in the present application;
fig. 6 is a timing diagram of signals of a GOA unit provided in the present application;
fig. 7 is a schematic plan view of a display panel provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. The form in the drawing provides that the middle end of the switching transistor is a grid, the signal input end is a drain, and the output end is a source. In addition, the transistors used in the embodiments of the present application may include a P-type transistor and/or an N-type transistor, where the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
In the following embodiments of the present application, the transistors are all described by taking N-type transistors as examples, but the present application is not limited thereto.
Referring to fig. 1 and fig. 2, fig. 1 is a circuit schematic diagram of a pixel compensation circuit provided in the present application, and fig. 2 is a signal timing diagram of the pixel compensation circuit provided in the present application.
As shown in fig. 1 and 2, the pixel compensation circuit 10 has a structure of 5T 2C. The pixel compensation circuit 10 effectively compensates the threshold voltage of the driving transistor T2 in each pixel under the control of the first Scan signal Scan1, the second Scan signal Scan2, and the enable signal EM.
The first Scan signal Scan1, the second Scan signal Scan2 and the enable signal EM are all provided by the GOA circuit in the display panel.
It should be noted that the operation principle of the pixel compensation circuit 10 is well known to those skilled in the art, and will not be described herein.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a GOA unit in the GOA circuit provided in the present application.
As shown in fig. 3, the GOA circuit includes multiple cascaded levels of GOA cells 20. Each stage of GOA units 20 comprises: a pull-up control unit 101, a pull-up unit 102, a pull-down unit 103, a first pull-down maintaining unit 104, a second pull-down maintaining unit 105, an inverter unit 106, and a feedback unit 107.
The pull-up control unit 101 is connected to the previous stage first Scan signal Scan1(N-1) and the first clock signal CK1, electrically connected to the first node Q and the second node N, and configured to pull up the potential of the first node Q under the control of the previous stage first Scan signal Scan1(N-1) and the first clock signal CK 1.
The pull-up unit 102 is electrically connected to the first node Q, the current stage first Scan signal output terminal a, the current stage second Scan signal output terminal B, and the current stage enable signal output terminal C, and is configured to output the current stage first Scan signal Scan1(n), the current stage second Scan signal Scan2(n), and the current stage enable signal em (n) under the control of the potential of the first node Q, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK 4.
The pull-down unit 103 is connected to the next-stage first Scan signal Scan1(N +1) and the reference low-level signal VGL, electrically connected to the first node Q and the second node N, and configured to pull down the potential of the first node Q under the control of the next-stage first Scan signal Scan1(N +1) and the reference low-level signal VGL.
The first pull-down maintaining unit 104 is coupled to the reference low level signal VGL, and is electrically connected to the first node Q, the second node N, and the third node QB, for maintaining the potential of the first node Q after the pull-down unit 103 pulls down the potential of the first node Q.
The second pull-down maintaining unit 105 is electrically connected to the third node QB, the current-stage first Scan signal output terminal a, the current-stage second Scan signal output terminal B, and the current-stage enable signal output terminal C, and is configured to maintain the potentials of the current-stage first Scan signal Scan1(n), the current-stage second Scan signal Scan2(n), and the current-stage enable signal em (n) under the control of the potential of the third node QB, the reference low-level signal VGL, and the reference high-level signal VGL.
The inverter unit 106 is coupled to the reference high level signal VGH, electrically connected to the first node Q and the third node QB, and configured to keep the voltage level of the third node QB opposite to the voltage level of the first node Q.
The feedback unit 107 is connected to the reference high level signal VGH, electrically connected to the first node Q and the second node N, and configured to pull up the potential of the second node N under the control of the potential of the first node Q and the reference high level signal VGH.
It should be noted that, in the embodiment of the present application, for the first-stage GOA unit 20 in the GOA circuit, an additional trigger signal needs to be introduced from the outside to replace the previous-stage first Scan signal Scan1(n-1) to pull up the potential of the first node Q. Similarly, for the last-stage GOA unit 20 in the GOA circuit, a feedback signal needs to be introduced from the outside to replace the next-stage first Scan signal Scan1(n +1) to pull down the potential of the first node Q.
The embodiment of the present application provides a GOA circuit, which includes multiple stages of GOA units 20 arranged in a cascade manner. Each of the GOA units 20 can output the current-stage first Scan signal Scan1(n), the current-stage second Scan signal Scan2(n), and the current-stage enable signal em (n) with different timings, so that the GOA circuit can drive the pixel compensation circuit 10 shown in fig. 1. Compared with the prior art that a plurality of sets of GOA circuits are arranged in the display panel, the GOA circuit provided by the embodiment of the application is beneficial to realizing narrow frame design.
Referring to fig. 4, fig. 4 is a circuit schematic diagram of a GOA unit in the GOA circuit provided in the present application.
Wherein, the pull-up control unit 101 includes a first transistor T1 and a second transistor T2.
The gate of the first transistor T1 and the gate of the second transistor T2 are both connected to the first clock signal CK 1. The source of the first transistor T1 is connected to the previous stage first Scan signal Scan1 (n-1). The drain of the first transistor T1 and the source of the second transistor T2 are both electrically connected to the second node N. The drain of the second transistor T2 is electrically connected to the first node Q.
The pull-up unit 102 includes a bootstrap capacitor C, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
The first end of the bootstrap capacitor C, the gate of the third transistor T3, the gate of the fourth transistor T4, and the gate of the fifth transistor T5 are all electrically connected to the first node Q. The source of the third transistor T3 is coupled to the second clock signal CK 2. The drain of the third transistor T3 and the second end of the bootstrap capacitor C are both electrically connected to the first scan signal output terminal a of the present stage. The source of the fourth transistor T4 is connected to the third clock signal CK 3. The drain of the fourth transistor T4 is electrically connected to the second scan signal output terminal B of the present stage. The source of the fifth transistor T5 is connected to the fourth clock signal CK 4. The drain of the fifth transistor T5 is electrically connected to the current stage enable signal output terminal C.
The pull-down unit 103 includes a sixth transistor T6 and a seventh transistor T7.
The gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both connected to the next stage first Scan signal Scan1(n + 1). A source of the sixth transistor T6 is connected to the reference low level signal VGL. The drain of the sixth transistor T6 and the source of the seventh transistor T7 are both electrically connected to the second node N. The drain of the seventh transistor T7 is electrically connected to the first node Q.
The first pull-down maintaining unit 104 includes an eighth transistor T8 and a ninth transistor T9.
The gate of the eighth transistor T8 and the gate of the ninth transistor T9 are both electrically connected to the third node QB. A source of the eighth transistor T8 is connected to the reference low level signal VGL. The drain of the eighth transistor T8 and the source of the ninth transistor T9 are both electrically connected to the second node N. The drain of the ninth transistor T9 is electrically connected to the first node Q.
The second pull-down maintaining unit 105 includes a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12.
The gate of the tenth transistor T10, the gate of the eleventh transistor T11, and the gate of the twelfth transistor T12 are electrically connected to the third node QB. The source of the tenth transistor T10 and the source of the eleventh transistor T11 are both connected to the reference low signal VGL. The drain of the tenth transistor T10 is electrically connected to the current stage first scan signal output terminal a. The drain of the eleventh transistor T11 is electrically connected to the current-stage second scan signal output terminal B. A source of the twelfth transistor T12 is connected to the reference high signal VGH. The drain of the twelfth transistor T12 is electrically connected to the current stage enable signal output terminal C.
The inverter unit 106 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16.
The gate of the thirteenth transistor T13, the source of the thirteenth transistor T13, and the source of the fourteenth transistor T14 are all connected to the reference high signal VGH. A drain of the thirteenth transistor T13, a gate of the fourteenth transistor T14, and a drain of the fifteenth transistor T15 are connected. The drain of the fourteenth transistor T14 and the drain of the sixteenth transistor T16 are both electrically connected to the third node QB. The gate of the fifteenth transistor T15 and the source of the sixteenth transistor T16 are both electrically connected to the first node Q. The source of the fifteenth transistor T15 and the source of the sixteenth transistor T16 are both connected to the reference low signal VGL.
Wherein the feedback unit 107 comprises a seventeenth transistor T17.
The gate of the seventeenth transistor T17 is electrically connected to the first node Q. A source of the seventeenth transistor T17 is connected to the reference high signal VGH. The drain of the seventeenth transistor T17 is electrically connected to the second node N.
Specifically, please refer to fig. 5 and 6. Fig. 5 shows signal voltage values of the GOA unit provided in the present application. Fig. 6 is a timing diagram of signals of the GOA unit provided in the present application.
At the stage T1, the first clock signal CK1 is at a high level, and the first transistor T1 and the second transistor T2 are turned on. Since the previous-stage first Scan signal Scan1(n-1) is at a high potential, the potential of the first node Q is pulled to a high potential, so that the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on. At this time, since the second clock signal CK2 is at a low potential, the third clock signal CK3 is at a low potential, and the fourth clock signal CK4 is at a high potential, the current stage first Scan signal Scan1(n) and the current stage second Scan signal Scan2(n) are both outputted at a low potential, and the current stage enable signal em (n) is outputted at a high potential. Meanwhile, the fifteenth transistor T15 and the sixteenth transistor T16 are turned on, and the potential of the third node QB is pulled low to a low potential, so that the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are turned off.
At the stage T2, the first clock signal CK1 goes low, the first transistor T1 and the second transistor T2 are turned off, and the first node Q remains high, so that the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on. At this time, the second clock signal CK2 and the third clock signal CK3 transition from low to high, and thus the current stage first Scan signal Scan1(n) and the current stage second Scan signal Scan2(n) are both output as high.
Meanwhile, since the fourth clock signal CK4 is kept at a high level in the second stage and then changes from the high level to the low level, the stage enable signal em (n) is outputted at a high level and then outputted at a low level. It should be noted that, in the stage t2, the time for the stage enable signal em (n) to be output as the high potential and the low potential is equal.
In addition, at the stage T2, due to the existence of the bootstrap capacitor C, the potential of the first node Q is pulled up to a higher potential due to the bootstrap effect, so that the gate voltage of the third transistor T3 is pulled up to a fully open state quickly, the rising time of the current-stage first Scan signal Scan1(n) is effectively reduced, and further, the Scan line corresponding to the nth-stage GOA unit 20 is effectively charged, thereby improving the charging capability of the display panel.
At the stage T3, the first clock signal CK1 is still at the low level, the first transistor T1 and the second transistor T2 are turned off, and the first node Q is still at the high level, so that the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on. At this time, the second clock signal CK2 is kept at a high level, the third clock signal CK3 changes from a high level to a low level, and the fourth clock signal is kept at a low level, so that the current stage first Scan signal Scan1(n) is output at a high level, and the current stage second Scan signal Scan2(n) and the current stage enable signal em (n) are both output at a low level.
At the stage T4, the first clock signal CK1 changes from low to high, the first transistor T1 and the second transistor T2 are turned on, the next scan signal scan1(n +1) is raised to high, the sixth transistor T6 and the seventh transistor T7 are turned on, the voltage level of the first node Q is pulled down to low, and the fifteenth transistor T15 and the sixteenth transistor T16 are turned off. Meanwhile, the thirteenth transistor T13 is turned on, such that the fourteenth transistor T14 is turned on, the third node QB is pulled high, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the present stage first Scan signal Scan1(n) and the present stage second Scan signal Scan2(n) are output low, and the present stage enable signal em (n) is output high.
In addition, according to the embodiment of the present application, the feedback unit 107 is disposed in the GOA unit 20, so that leakage of the first node Q is effectively reduced.
Specifically, in the GOA unit 20, the drain of the second transistor T2, the source of the ninth transistor T9, and the drain of the seventh transistor T7 are all electrically connected to the second node N. In the above-mentioned period T1-T3, when the potential of the first node Q is pulled high, the seventeenth transistor T17 is turned on, and the potential of the second node N is also pulled high, so that the second transistor T2, the seventh transistor T7 and the ninth transistor T9 can be completely turned off when the first clock signal CK1, the third node QB and the next-stage first Scan signal Scan1(N +1) are at low potential, thereby reducing the leakage of the GOA circuit and improving the stability of the GOA circuit.
The transistors in the GOA circuit provided by the present application may be low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors. Meanwhile, the transistors in the GOA circuit provided by the embodiment of the application are the same type of transistors, so that the influence of difference among different types of transistors on the GOA circuit is avoided.
The embodiment of the present application provides a GOA unit 20 with a 17T2C structure, and a plurality of stages of GOA units 20 are cascaded to form a GOA circuit, wherein each stage of GOA unit 20 can output a current-stage first Scan signal Scan1(n), a current-stage second Scan signal Scan2(n), and a current-stage enable signal em (n) with different timings, so that the GOA circuit can drive the pixel compensation circuit 10 shown in fig. 1. Compared with the prior art that a plurality of sets of GOA circuits are arranged in the display panel, the GOA circuit provided by the embodiment of the application is beneficial to realizing narrow frame design.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a display panel provided in the present application. As shown in fig. 7, the display panel includes a display portion 100 and a GOA circuit 200 integrally disposed on an edge of the display portion 100; the structure and principle of the GOA circuit 200 are similar to those of the GOA circuit described above, and are not described herein again.
The display panel according to the embodiment of the present application is described by taking a one-side driving method in which the GOA circuit 200 is disposed on the display portion 100 side as an example, but the present application is not limited thereto. In some embodiments, other driving methods such as double-side driving may be adopted according to the actual requirements of the display panel.
The foregoing describes in detail the GOA circuit and the display panel provided in the embodiments of the present application, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the foregoing embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A GOA circuit, comprising a plurality of cascaded GOA units, each GOA unit comprising: the device comprises a pull-up control unit, a pull-up unit, a pull-down unit, a first pull-down maintaining unit, a second pull-down maintaining unit, an inverter unit and a feedback unit;
the pull-up control unit is connected to a first scanning signal and a first clock signal of a previous stage, is electrically connected to a first node and a second node, and is used for pulling up the potential of the first node under the control of the first scanning signal and the first clock signal of the previous stage;
the pull-up unit is connected to a second clock signal, a third clock signal and a fourth clock signal, is electrically connected to the first node, the current-stage first scanning signal output end, the current-stage second scanning signal output end and the current-stage enable signal output end, and is used for outputting the current-stage first scanning signal, the current-stage second scanning signal and the current-stage enable signal under the control of the potential of the first node, the second clock signal, the third clock signal and the fourth clock signal;
the pull-down unit is connected to a next-stage first scanning signal and a reference low level signal, is electrically connected to the first node and the second node, and is used for pulling down the potential of the first node under the control of the next-stage first scanning signal and the reference low level signal;
the first pull-down maintaining unit is connected to the reference low level signal, electrically connected to the first node, the second node and the third node, and configured to maintain a potential of the first node after the pull-down unit pulls down the potential of the first node;
the second pull-down maintaining unit is connected to the reference low level signal and the reference high level signal, and is electrically connected to the third node, the current-stage first scanning signal output end, the current-stage second scanning signal output end and the current-stage enable signal output end, and is configured to maintain the potentials of the current-stage first scanning signal, the current-stage second scanning signal and the current-stage enable signal under the control of the potential of the third node, the reference low level signal and the reference high level signal;
the inverter unit is connected to the reference high level signal, electrically connected to the first node and the third node, and configured to keep a potential of the third node opposite to a potential of the first node;
the feedback unit is connected to the reference high level signal, electrically connected to the first node and the second node, and configured to pull up a potential of the second node under control of the potential of the first node and the reference high level signal.
2. The GOA circuit according to claim 1, wherein the pull-up control unit comprises a first transistor and a second transistor;
the grid electrode of the first transistor and the grid electrode of the second transistor are both connected to the first clock signal; the source electrode of the first transistor is connected with the upper-stage first scanning signal; the drain electrode of the first transistor and the source electrode of the second transistor are both electrically connected to the second node; the drain of the second transistor is electrically connected to the first node.
3. The GOA circuit according to claim 1, wherein the pull-up unit comprises a bootstrap capacitor, a third transistor, a fourth transistor and a fifth transistor;
the first end of the bootstrap capacitor, the gate of the third transistor, the gate of the fourth transistor and the gate of the fifth transistor are all electrically connected to the first node; the source electrode of the third transistor is connected to the second clock signal; the drain electrode of the third transistor and the second end of the bootstrap capacitor are both electrically connected to the current-stage first scanning signal output end; the source electrode of the fourth transistor is connected to the third clock signal; the drain electrode of the fourth transistor is electrically connected to the current-stage second scanning signal output end; the source electrode of the fifth transistor is connected with the fourth clock signal; and the drain electrode of the fifth transistor is electrically connected to the current-stage enable signal output end.
4. The GOA circuit of claim 1, wherein the pull-down unit comprises a sixth transistor and a seventh transistor;
the grid electrode of the sixth transistor and the grid electrode of the seventh transistor are both connected to the next-stage first scanning signal; the source electrode of the sixth transistor is connected with the reference low-level signal; the drain electrode of the sixth transistor and the source electrode of the seventh transistor are both electrically connected to the second node; the drain of the seventh transistor is electrically connected to the first node.
5. The GOA circuit of claim 1, wherein the first pull-down sustain unit comprises an eighth transistor and a ninth transistor;
the gate of the eighth transistor and the gate of the ninth transistor are both electrically connected to the third node; the source electrode of the eighth transistor is connected with the reference low-level signal; the drain of the eighth transistor and the source of the ninth transistor are both electrically connected to the second node; the drain of the ninth transistor is electrically connected to the first node.
6. The GOA circuit of claim 1, wherein the second pull-down sustain unit comprises a tenth transistor, an eleventh transistor and a twelfth transistor;
a gate of the tenth transistor, a gate of the eleventh transistor, and a gate of the twelfth transistor are all electrically connected to the third node; a source electrode of the tenth transistor and a source electrode of the eleventh transistor are both connected to the reference low-level signal; the drain of the tenth transistor is electrically connected to the current-stage first scanning signal output end; the drain electrode of the eleventh transistor is electrically connected to the current-stage second scanning signal output end; the source electrode of the twelfth transistor is connected with the reference high-level signal; and the drain electrode of the twelfth transistor is electrically connected to the current-stage enable signal output end.
7. The GOA circuit of claim 1, wherein the inverter unit comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;
the grid electrode of the thirteenth transistor, the source electrode of the thirteenth transistor and the source electrode of the fourteenth transistor are all connected with the reference high-level signal; the drain electrode of the thirteenth transistor, the grid electrode of the fourteen transistor and the drain electrode of the fifteenth transistor are connected; a drain of the fourteenth transistor and a drain of the sixteenth transistor are both electrically connected to the third node; a gate of the fifteenth transistor and a source of the sixteenth transistor are both electrically connected to the first node; a source of the fifteenth transistor and a source of the sixteenth transistor are both coupled to the reference low level signal.
8. The GOA circuit of claim 1, wherein the feedback unit comprises a seventeenth transistor;
a gate of the seventeenth transistor is electrically connected to the first node; the source electrode of the seventeenth transistor is connected with the reference high-level signal; the drain of the seventeenth transistor is electrically connected to the second node.
9. The GOA circuit according to claim 1, wherein the transistors in the GOA unit are indium gallium zinc oxide thin film transistors.
10. A display panel comprising the GOA circuit of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011266597.6A CN112365851A (en) | 2020-11-13 | 2020-11-13 | GOA circuit and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011266597.6A CN112365851A (en) | 2020-11-13 | 2020-11-13 | GOA circuit and display panel |
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| CN112365851A true CN112365851A (en) | 2021-02-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011266597.6A Pending CN112365851A (en) | 2020-11-13 | 2020-11-13 | GOA circuit and display panel |
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| CN (1) | CN112365851A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023010690A (en) * | 2021-07-08 | 2023-01-20 | エルジー ディスプレイ カンパニー リミテッド | Gate driving section and display panel including the same |
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| CN103730089A (en) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | Grid driving circuit and method, array substrate line driving circuit and display device |
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| CN111223433A (en) * | 2020-01-19 | 2020-06-02 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display device |
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| CN103730089A (en) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | Grid driving circuit and method, array substrate line driving circuit and display device |
| CN108230999A (en) * | 2018-02-01 | 2018-06-29 | 武汉华星光电半导体显示技术有限公司 | GOA circuits and OLED display |
| CN109243371A (en) * | 2018-10-29 | 2019-01-18 | 北京大学深圳研究生院 | A kind of drive circuit unit, driving circuit and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2023010690A (en) * | 2021-07-08 | 2023-01-20 | エルジー ディスプレイ カンパニー リミテッド | Gate driving section and display panel including the same |
| JP7383086B2 (en) | 2021-07-08 | 2023-11-17 | エルジー ディスプレイ カンパニー リミテッド | Gate drive unit and display panel including it |
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Application publication date: 20210212 |