CN114914295B - UMOS device with excellent forward and reverse conduction characteristics - Google Patents
UMOS device with excellent forward and reverse conduction characteristics Download PDFInfo
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- CN114914295B CN114914295B CN202210757304.7A CN202210757304A CN114914295B CN 114914295 B CN114914295 B CN 114914295B CN 202210757304 A CN202210757304 A CN 202210757304A CN 114914295 B CN114914295 B CN 114914295B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 105
- 239000004065 semiconductor Substances 0.000 claims abstract description 97
- 229920005591 polysilicon Polymers 0.000 claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 210000000746 body region Anatomy 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract 1
- 229910010271 silicon carbide Inorganic materials 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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Abstract
The invention provides a UMOS device structure with excellent forward and reverse conduction characteristics, and belongs to the technical field of power semiconductor devices. According to the UMOS device with excellent forward and reverse conduction characteristics, the bottom oxide layer of the trench gate is removed, so that the trench bottom shielding layer, the drift region and the substrate form a diode structure. Meanwhile, the grid polysilicon has an upper doping type structure and a lower doping type structure, so that the switching speed under the condition of forward conduction can be improved, and meanwhile, the grid polysilicon can also be used as diode conduction current under the condition of reverse conduction. Therefore, under the condition of reverse conduction, the device not only has strong current driving capability, but also greatly reduces the reverse conduction voltage of the device due to the existence of the polysilicon diode. Therefore, the structure of the invention effectively improves the switching speed of the device under forward conduction on the basis of ensuring the original basic electrical performance of UMOS, optimizes the three-quadrant characteristic of the device, and is suitable for silicon carbide devices.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a UMOS device with excellent forward and reverse conduction characteristics.
Background
With the continuous development of power semiconductors towards the application fields of higher frequency and higher voltage, the switching loss of Si-based power devices is difficult to be further reduced in a high-frequency environment due to the limitation of self material parameters, and the working temperature of the Si-based devices cannot reach more than 150 ℃. SiC is used as a third generation wide bandgap semiconductor material, and is more suitable for high-frequency, high-voltage and high-temperature working conditions due to the characteristics of wide bandgap, high critical breakdown electric field, large heat conductivity coefficient and the like.
When the SiC MOSFET is applied to a bridge circuit, the device not only needs to work in a forward conduction state to play a role of switching, but also needs to work in a reverse conduction state as a freewheeling diode.
Because the SiC device has smaller cell area than the Si-based device with the same quantity, the switching speed is very fast, but the existence of parasitic capacitance of the device can also influence the switching speed of the device, so that the switching loss of the device is increased. Among the parasitic capacitances of the device, the miller capacitance has the most remarkable effect on the switching of the device, and it is an extremely effective measure to further increase the switching speed of the device, reduce the conduction loss, and reduce the miller capacitance.
In addition, because the forbidden bandwidth of the SiC material is wide, the conduction voltage drop of the parasitic body diode is about four times larger than that of the Si-based diode, and the reverse conduction loss of the device is larger. In order to enable the device to have lower conduction loss and stronger current driving capability under the reverse conduction condition, the integrated diode is a common device level improvement method inside the device structure.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a UMOS device having excellent forward and reverse conduction characteristics, which can effectively reduce the miller capacitance of the device, and increase the forward switching speed of the device, thereby reducing the conduction loss of the device. In addition, the reverse conduction voltage of the device can be effectively reduced, the reverse conduction loss of the device is reduced, and the reverse current driving capability of the device is improved.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a UMOS device having excellent forward and reverse conduction characteristics, comprising a metalized drain 1, a heavily doped first conductivity type semiconductor substrate 2 on the metalized drain 1, a lightly doped first conductivity type semiconductor body 3 on the heavily doped first conductivity type semiconductor substrate 2, a first conductivity type semiconductor highly doped region 8 on the lightly doped first conductivity type semiconductor body 3;
a highly doped second conductivity type semiconductor body 9 located over said first conductivity type semiconductor highly doped region 8; a heavily doped first conductivity type semiconductor source region 11 and a heavily doped second conductivity type semiconductor contact region 12 located immediately above the highly doped second conductivity type semiconductor body region 9; the heavily doped first conductivity type semiconductor source region 11 and the heavily doped second conductivity type semiconductor contact region 12 are in direct contact with the metalized source 14 in the form of ohmic contacts;
the upper part of the lightly doped first conductivity type semiconductor body region 3 is also provided with a groove structure, and the upper surface of the groove is electrically isolated from the metalized source 14 through a dielectric layer 13; the side surface of the groove is provided with a gate oxide layer 6, and the gate oxide layer 6 is in direct contact with the side surfaces of the first conductive type semiconductor high doping area 8, the high doping second conductive type semiconductor body area 9 and the heavily doping first conductive type semiconductor source area 11; the part of the high doped second conductivity type semiconductor body 9 close to the trench wall is a channel region; the trench is filled with a heavily doped first-conductivity-type polysilicon gate electrode region 10 and a lightly doped second-conductivity-type polysilicon body region 7, wherein the lightly doped second-conductivity-type polysilicon body region 7 is positioned below the heavily doped first-conductivity-type polysilicon gate electrode region 10 and is in direct contact with the lower surface of the heavily doped first-conductivity-type polysilicon gate electrode region; a heavily doped second conductivity type polysilicon source electrode region 5 is arranged right below the lightly doped second conductivity type polysilicon body region 7; a heavily doped second conductivity type semiconductor shielding layer 4 is arranged right below the heavily doped second conductivity type polycrystalline silicon source electrode region 5;
the heavily doped first conductivity type polysilicon gate electrode region 10 completely covers the side surface of the highly doped second conductivity type semiconductor body region 9; the heavily doped first conductivity type polysilicon gate electrode region 10 is connected to a gate potential; the heavily doped second conductivity type polycrystalline silicon source electrode region 5 is connected with the potential of the metalized source 14 through a through hole by layout design;
the heavily doped first conductive type polysilicon gate electrode region 10 completely covers the channel region, so that the switching performance of the semiconductor device can be realized; the heavily doped first conductivity type polysilicon gate electrode region 10 is connected to a gate potential; the heavily doped second conductivity type polysilicon source electrode region 5 and the metalized source 14 are connected to a source potential; under the reverse operation of the semiconductor device, the gate contact and the drain contact are shorted.
Preferably, lightly doped second conductivity type polysilicon body regions 7 are alternately arranged between heavily doped second conductivity type polysilicon source electrode regions 5 directly below lightly doped second conductivity type polysilicon body regions 7.
Preferably, the first conductivity type is n-type and the second conductivity type is p-type.
Preferably, the first conductivity type is p-type and the second conductivity type is n-type.
Preferably, the semiconductor is SiC.
Preferably, the doping concentration of the heavy doping is more than 1E19cm -3 The doping concentration of the light doping is less than 1E17cm -3 The doping concentration of the high doping is 1E19cm -3 And 1E17cm -3 Between them.
The invention has the beneficial effects that: the UMOS device with excellent forward and reverse characteristics is prepared by using a step-by-step deposition method to make a conventional polysilicon electrode region into N + P - P + When the first conductive type semiconductor is an n-type semiconductor, the reverse bias of the polysilicon PN junction is realized by utilizing the gate-source potential difference in the forward working state, and under the condition that the through breakdown of the polysilicon gate source electrode area is not generated, the electrical isolation between the polysilicon gate source electrode areas is realized, and the gate-drain overlapping area is reduced, so that the Miller capacitance of the device is reduced, and the switching speed of the device in the forward working state is improved. In addition highly doped P + The existence of the shielding layer (when the first conductive type semiconductor is an n-type semiconductor) also effectively protects the oxidation layer at the bottom of the groove and improves the voltage-withstanding capability of the device. When the device works under the condition of reverse conduction, the grid electrode and the drain electrode are connected with zero potential, and the polysilicon diode is conducted preferentially to carry out circuit because the conduction voltage drop of the SiC parasitic body diode is largerAnd when the source potential rises to two and three volts, the SiC body diode is conducted, and the device has strong reverse current driving capability. In the invention, the device has two parasitic body diodes, one is a parasitic body diode formed by a highly doped second conductive type semiconductor body region 9, a first conductive type semiconductor highly doped region 8, a lightly doped first conductive type semiconductor body region 3 and a heavily doped first conductive type semiconductor substrate 2; another is a parasitic body diode formed by heavily doping the second conductivity type semiconductor shield layer 4, lightly doping the first conductivity type semiconductor body region 3, and heavily doping the first conductivity type semiconductor substrate 2. Therefore, under the condition of reverse conduction, the whole cell area can provide a current path, and the problem of rising of junction temperature of the device caused by current concentration is greatly relieved.
Drawings
Fig. 1 is a schematic structural diagram of a UMOS device having excellent forward and reverse conduction characteristics according to embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of a trench portion of a UMOS device with good forward and reverse conduction characteristics according to embodiment 1 after a trench bottom oxide layer is thickened;
fig. 3 is an equivalent circuit diagram of a parasitic capacitance-containing parasitic diode of a UMOS device having excellent forward and reverse conduction characteristics of embodiment 1 of the present invention;
fig. 4 is a schematic structural diagram of a UMOS device having excellent forward and reverse conduction characteristics according to embodiment 2 of the present invention;
fig. 5 is a top view of a polysilicon source electrode region and a corresponding polysilicon local area diagram of a UMOS device having excellent forward and reverse conduction characteristics according to embodiment 2 of the present invention; wherein (a) is a top view of the polysilicon portion of the trench bottom and (b) is an overall cross-sectional view of the device along section line AA'.
Fig. 6 is a top view of another polysilicon source electrode region design and a corresponding polysilicon local area diagram of a UMOS device having excellent forward and reverse conduction characteristics according to embodiment 2 of the present invention; wherein, (a) is a top view of a portion of the polysilicon at the bottom of the trench, the alternating arrangement direction of the polysilicon is perpendicular to fig. 5 (a), (b) is a cross-sectional view of the device as a whole along the section line BB ', and (c) is a cross-sectional view of the device as a whole along the section line CC'.
Wherein 1 is a metalized drain, 2 is a heavily doped first conductivity type semiconductor substrate, 3 is a lightly doped first conductivity type semiconductor body region, 4 is a heavily doped second conductivity type semiconductor shield layer, 5 is a heavily doped second conductivity type polysilicon source electrode region, 6 is a gate oxide layer, 7 is a lightly doped second conductivity type polysilicon body region, 8 is a first conductivity type semiconductor highly doped region, 9 is a highly doped second conductivity type semiconductor body region, 10 is a heavily doped first conductivity type polysilicon gate electrode region, 11 is a heavily doped first conductivity type semiconductor source region, 12 is a heavily doped second conductivity type semiconductor contact region, 13 is a dielectric layer, and 14 is a metalized source.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
As shown in fig. 1, the present embodiment provides a UMOS device having excellent forward and reverse conduction characteristics, including a metalized drain 1, a heavily doped first conductivity type semiconductor substrate 2 on the metalized drain 1, a lightly doped first conductivity type semiconductor body 3 on the heavily doped first conductivity type semiconductor substrate 2, and a first conductivity type semiconductor highly doped region 8 on the lightly doped first conductivity type semiconductor body 3;
a highly doped second conductivity type semiconductor body 9 located over said first conductivity type semiconductor highly doped region 8; a heavily doped first conductivity type semiconductor source region 11 and a heavily doped second conductivity type semiconductor contact region 12 located immediately above the highly doped second conductivity type semiconductor body region 9; the heavily doped first conductivity type semiconductor source region 11 and the heavily doped second conductivity type semiconductor contact region 12 are in direct contact with the metalized source 14 in the form of ohmic contacts;
the upper part of the lightly doped first conductivity type semiconductor body region 3 is also provided with a groove structure, and the upper surface of the groove is electrically isolated from the metalized source 14 through a dielectric layer 13; the side surface of the groove is provided with a gate oxide layer 6, and the gate oxide layer 6 is in direct contact with the side surfaces of the first conductive type semiconductor high doping area 8, the high doping second conductive type semiconductor body area 9 and the heavily doping first conductive type semiconductor source area 11; the part of the high doped second conductivity type semiconductor body 9 close to the trench wall is a channel region; the trench is filled with a heavily doped first-conductivity-type polysilicon gate electrode region 10 and a lightly doped second-conductivity-type polysilicon body region 7, wherein the lightly doped second-conductivity-type polysilicon body region 7 is positioned below the heavily doped first-conductivity-type polysilicon gate electrode region 10 and is in direct contact with the lower surface of the heavily doped first-conductivity-type polysilicon gate electrode region; a heavily doped second conductivity type polysilicon source electrode region 5 is arranged right below the lightly doped second conductivity type polysilicon body region 7; a heavily doped second conductivity type semiconductor shielding layer 4 is arranged right below the heavily doped second conductivity type polycrystalline silicon source electrode region 5;
the heavily doped first conductivity type polysilicon gate electrode region 10 completely covers the side surface of the highly doped second conductivity type semiconductor body region 9; the heavily doped first conductivity type polysilicon gate electrode region 10 is connected to a gate potential; the heavily doped second conductivity type polycrystalline silicon source electrode region 5 is connected with the potential of the metalized source 14 through a through hole by layout design;
the heavily doped first conductive type polysilicon gate electrode region 10 completely covers the channel region, so that the switching performance of the semiconductor device can be realized; the heavily doped first conductivity type polysilicon gate electrode region 10 is connected to a gate potential; the heavily doped second conductivity type polysilicon source electrode region 5 and the metalized source 14 are connected to a source potential; under the reverse operation of the semiconductor device, the gate contact and the drain contact are shorted.
The first conductivity type is n-type and the second conductivity type is p-type.
Or the first conductivity type is p-type and the second conductivity type is n-type.
Preferably, the semiconductor is SiC.
The doping concentration of heavy doping is more than 1E19cm -3 The doping concentration of the light doping is less than 1E17cm -3 The doping concentration of the high doping is 1E19cm -3 And 1E17cm -3 Between them.
In the above embodiment, the length of the lightly doped second conductivity type polysilicon body should be long enough to ensure that the middle lightly doped second conductivity type polysilicon body does not break through when the gate-source voltage falls at both ends of the polysilicon, thereby ensuring that the device can normally operate in a forward conduction state.
The working principle of the present invention will be explained below by taking example 1 as an example, where the first conductivity type is n-type and the second conductivity type is p-type:
when the device works under the forward conduction condition, the heavily doped first conductivity type polysilicon gate electrode region 10 is connected with a gate potential, a positive potential is applied to the gate, the metalized source 14 and the heavily doped second conductivity type polysilicon source electrode region 5 are both connected with a ground potential, and the metalized drain 1 is connected with a high potential. The polysilicon diode formed by the heavily doped polysilicon gate electrode region of the first conductivity type and the lightly doped polysilicon body region of the second conductivity type is reversely biased to form PN junction self-isolation, thereby realizing electrical isolation between the gate electrode and the source electrode. And the polysilicon gate electrode region is connected with positive potential to enable the channel region to be in inversion, so that the forward conduction function of the device is realized. Meanwhile, because a reverse bias PN junction exists between the heavily doped polysilicon gate electrode region and the heavily doped polysilicon source electrode region, the overlapping area between the polysilicon gate electrode and the drain electrode is reduced, so that the Miller capacitance of the device is effectively reduced, the switching speed of the device is improved, and the switching loss is reduced. In addition, in order to ensure that the device normally works in a forward conduction state, it is necessary to ensure that the polysilicon gate electrode region and the polysilicon source electrode region do not break through, so that the doping concentration of the lightly doped polysilicon body region should be low and have a certain width, and specific values can be correspondingly adjusted according to the highest gate voltage applied during actual working.
When the device works under the reverse blocking condition, the polysilicon gate electrode region and the metal source electrode are grounded, and the metal drain electrode is connected with high potential. At this time, the channel is turned off, and the polysilicon diode formed by the polysilicon gate electrode region, the lightly doped polysilicon body region and the polysilicon source electrode region is zero biased, so that a conductive path does not appear between the gate and the source. The heavily doped semiconductor shielding layer can effectively shield the electric field of the oxide layer and effectively improve the reliability of the oxide layer of the device.
When the device works under the reverse conduction condition, the polysilicon gate electrode region and the metal drain electrode are both connected with ground potential, and the polysilicon source electrode region and the metal source electrode are connected with positive potential. At this time, the polysilicon diode formed by the polysilicon gate electrode region, the lightly doped polysilicon body region and the polysilicon source electrode region is forward biased and is first conducted, so that current flows from the polysilicon source electrode region to the polysilicon gate electrode region first, and when the potential on the metal source and the polysilicon source electrode region further rises, the SiC body diode formed by the lightly doped first conductivity type semiconductor body region and the heavily doped second conductivity type semiconductor shielding layer and the SiC body diode formed by the lightly doped first conductivity type semiconductor body region and the second conductivity type highly doped body region are forward conducted, as shown in fig. 3. The body diode1 is a body diode formed by the highly doped second conductive type semiconductor body region 9, the first conductive type semiconductor highly doped region 8 and the lightly doped first conductive type semiconductor body region 3; the body diode2 is a body diode formed by the heavily doped second conductive type semiconductor shielding layer 4 and the lightly doped first conductive type semiconductor body region 3; polySi diode is a polysilicon diode. The two diodes and the polysilicon diode can be used as current paths under the reverse conduction condition, so that the reverse current driving capability of the device can be improved, and the problem of overhigh local junction temperature caused by current concentration is effectively solved.
Example 2
As shown in fig. 4, the present embodiment provides a UMOS device having excellent forward and reverse conduction characteristics, and differs from embodiment 1 in that: lightly doped second conductivity type polysilicon body regions 7 are alternately arranged between heavily doped second conductivity type polysilicon source electrode regions 5 directly below lightly doped second conductivity type polysilicon body regions 7.
The top view of the polysilicon diode is shown in fig. 5, and the polysilicon source electrode region is designed into the structure with heavy and light doping alternation, so that the anode injection efficiency of the polysilicon diode can be effectively controlled, and the reverse recovery time is shortened. Fig. 6 shows another design of a polysilicon source electrode region, similar to fig. 5, but with a change in the direction of the heavily lightly doped alignment of the polysilicon source electrode region.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.
Claims (6)
1. A UMOS device having excellent forward and reverse conduction characteristics, comprising a metalized drain (1), a heavily doped first conductivity type semiconductor substrate (2) on the metalized drain (1), a lightly doped first conductivity type semiconductor body (3) on the heavily doped first conductivity type semiconductor substrate (2), a first conductivity type semiconductor highly doped region (8) on the lightly doped first conductivity type semiconductor body (3);
a highly doped second conductivity type semiconductor body region (9) located over said first conductivity type semiconductor highly doped region (8); a heavily doped first conductivity type semiconductor source region (11) and a heavily doped second conductivity type semiconductor contact region (12) located immediately above the highly doped second conductivity type semiconductor body region (9); the heavily doped first-conductivity-type semiconductor source region (11) and the heavily doped second-conductivity-type semiconductor contact region (12) are both in direct contact with the metalized source (14) in the form of ohmic contacts;
the upper part of the lightly doped first conductivity type semiconductor body region (3) is also provided with a groove structure, and the upper surface of the groove is electrically isolated from the metalized source electrode (14) through a dielectric layer (13); the side surface of the groove is provided with a gate oxide layer (6), and the gate oxide layer (6) is in direct contact with the side surfaces of the first conductive type semiconductor high doping area (8), the high doping second conductive type semiconductor body area (9) and the heavily doping first conductive type semiconductor source area (11); the part of the high-doped second conductive type semiconductor body region (9) close to the trench wall is a channel region; the trench is filled with a heavily doped first-conductivity-type polysilicon gate electrode region (10) and a lightly doped second-conductivity-type polysilicon body region (7), and the lightly doped second-conductivity-type polysilicon body region (7) is positioned below the heavily doped first-conductivity-type polysilicon gate electrode region (10) and is in direct contact with the lower surface of the heavily doped first-conductivity-type polysilicon gate electrode region; a heavily doped second conductivity type polycrystalline silicon source electrode region (5) is arranged right below the lightly doped second conductivity type polycrystalline silicon body region (7); a heavily doped second conductivity type semiconductor shielding layer (4) is arranged right below the heavily doped second conductivity type polycrystalline silicon source electrode region (5);
the heavily doped first conductivity type polysilicon gate electrode region (10) completely covers the side surface of the highly doped second conductivity type semiconductor body region (9); the heavily doped first conductivity type polysilicon gate electrode region (10) is connected with a gate potential; the heavily doped second conductive type polycrystalline silicon source electrode region (5) is connected with the potential of the metalized source electrode (14) through a through hole by layout design;
the method is characterized in that: the heavily doped first conductivity type polysilicon gate electrode region (10) completely covers the channel region, so that the switching performance of the semiconductor device can be realized; the heavily doped first conductivity type polysilicon gate electrode region (10) is connected with a gate potential; the heavily doped second conductivity type polysilicon source electrode region (5) and the metallized source electrode (14) are connected to a source potential; under the reverse operation of the semiconductor device, the gate contact and the drain contact are shorted.
2. A UMOS device having excellent forward and reverse conduction characteristics as claimed in claim 1, wherein: lightly doped second conductivity type polycrystalline silicon body regions (7) are alternately arranged between heavily doped second conductivity type polycrystalline silicon source electrode regions (5) right below the lightly doped second conductivity type polycrystalline silicon body regions (7).
3. A UMOS device having excellent forward and reverse conduction characteristics as claimed in claim 1, wherein: the first conductivity type is n-type and the second conductivity type is p-type.
4. A UMOS device having excellent forward and reverse conduction characteristics as claimed in claim 1, wherein: the first conductivity type is p-type and the second conductivity type is n-type.
5. A UMOS device having excellent forward and reverse conduction characteristics as claimed in claim 1, wherein: the semiconductor is SiC.
6. A UMOS device having excellent forward and reverse turn-on characteristics as claimed in any one of claims 1 to 5, wherein: the doping concentration of heavy doping is more than 1E19cm -3 The doping concentration of the light doping is less than 1E17cm -3 The doping concentration of the high doping is 1E19cm -3 And 1E17cm -3 Between them.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210757304.7A CN114914295B (en) | 2022-06-30 | 2022-06-30 | UMOS device with excellent forward and reverse conduction characteristics |
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