CN114883395B - 一种具有部分p型漂移区的igbt - Google Patents

一种具有部分p型漂移区的igbt Download PDF

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CN114883395B
CN114883395B CN202210479778.XA CN202210479778A CN114883395B CN 114883395 B CN114883395 B CN 114883395B CN 202210479778 A CN202210479778 A CN 202210479778A CN 114883395 B CN114883395 B CN 114883395B
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CN114883395A (zh
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郑崇芝
夏云
程峥
孙瑞泽
刘超
陈万军
张波
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7398Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Power Engineering (AREA)
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Abstract

本发明属于功率半导体技术领域,特别涉及一种具有部分P型漂移区的IGBT。本发明将IGBT的耐压层设置为由N型漂移区(4)和P型漂移区(5)通过上下堆叠的形式,形成具有部分P型的漂移区,从而使器件内部形成了一个肖克来(Shockley)二极管结构,此肖克来二极管由一个PNP晶体管(发射极:P+集电极,基极:N型场截止层,集电极:P型漂移区和一个NPN晶体管(发射极:N型载流子存储层,基极:P型漂移区,集电极:N型漂移区构成,从而实现了更好的导通压降与关断损耗的折中关系。

Description

一种具有部分P型漂移区的IGBT
技术领域
本发明属于功率半导体技术领域,特别涉及一种具有部分P型漂移区的IGBT(Insulated gate bipolar transistor,绝缘栅双极型晶体管)结构。
背景技术
IGBT是一种重要的功率器件,被广泛使用。其追求更优的导通压降与关断损耗的折衷关系。传统优化IGBT导通压降与关断损耗的方法主要改变栅极、阴极结构来增强阴极侧载流子存储、改变阳极结构来减少阳极侧载流子积累,以及改变耐压层结构来加速漂移区内载流子的抽取。对耐压层的改变主要是在漂移区内引入交替的PN条形成超结结构来实现。但是超结结构对N/P条电荷要求高,设计制造难度高。
发明内容
本发明的目的,就是为了优化IGBT的导通压降与关断损耗,提出一种具有部分P型漂移区的IGBT。
本发明的技术方案:一种具有具有部分P型漂移区的IGBT,其元胞包括集电极结构、耐压层结构、发射极结构和栅极结构,其中耐压层结构位于集电极结构之上,发射极结构和栅极结构位于耐压层结构之上:
所述集电极结构包括集电极金属1、P+集电极区2和N型场截止层3;所述集电极金属1的下表面引出端为器件的集电极C;所述P+集电极区2位于集电极金属1的上表面;所述N型场截止层3位于P+集电极区2的上表面;
所述发射极结构包括P型阱区7、N型发射极区9、P型体接触区8以及发射极金属10;所述P型阱区7位于耐压层结构上表面;所述N型发射极区9和P型体接触区8位于P型阱区7上表面;所述发射极金属10的下表面同时与N型发射极区9和P型体接触区8的上表面接触,其上表面的引出端为器件的发射极E;
所述栅极结构为沟槽栅结构,包括绝缘介质12和导电材料11;所述导电材料11位于绝缘介质12内,引出端为器件的栅极G;所述绝缘介质12从器件表面垂直穿过P型阱区7与耐压层结构接触,绝缘介质12的侧面与P型阱区7和N型发射极区9接触;
所述耐压层结构包括N型漂移区4和P型漂移区5,两者呈现上下堆叠的形式;所述N型漂移区4的下表面与N型场截止层3的上表面接触,上表面与P型漂移区5的下表面接触;所述P型漂移区5的上表面同时与绝缘介质12以及的P型阱区7的下表面接触。
本发明的有益效果为,本发明的一种具有部分P型漂移区的IGBT实现了更好的导通压降与关断损耗的折中关系。
附图说明
图1是本发明的IGBT结构;
图2是本发明的IGBT关断时的等效电路;
图3是本发明的IGBT关断时的等效电路与结构对应图;
图4是本发明的IGBT导通时的等效电路;
图5是本发明的IGBT导通时的等效电路与结构对应图;
图6是常规IGBT结构;
图7是常规IGBT等效电路;
图8是常规IGBT等效电路与结构对应图;
具体实施方式
下面结合附图对本发明进行详细的描述
如图1所示,为本发明的一种具有部分P型漂移区的IGBT结构,其导通和关断时的等效电路分别如图2和图4所示。图3和图5分别是图2和图4中的等效电路在器件结构中的映射。图6和图7分别为常规IGBT结构和等效电路图。可以看出,本发明器件在导通和关断时的等效电路是不相同的,这和栅极沟道是否开启存在关系。开启时,NP叠型漂移区使器件内部形成了一个肖克来(Shockley)二极管结构。此肖克来二极管由一个PNP晶体管(发射极:P+集电极2,基极:N型场截止层3,集电极:P型漂移区5)和一个NPN晶体管(发射极:N型载流子存储层,基极:P型漂移区5,集电极:N型漂移区4)构成。
本发明器件工作原理如下:
耐压时:器件栅极关断,发射极接地和集电极接正电位。此时器件等效电路如图2所示,器件耐压由PNP晶体管(发射极:P+集电极2,基极:N型场截止层3/N型漂移区4,集电极:P型漂移区5/P型阱区7/P+短路区8)承担。耐压时电场峰值在N型漂移区4/P型漂移区5这个结上,电场峰值远离栅极区,这有利于提高器件的耐压。
正向导通时:器件栅极开启,发射极接地和集电极接正电位。栅极电压在P型漂移区5以及P型阱区7靠近栅极区的表面形成电子反型层,从而形成电子沟道。此电子反型层与P型漂移区5和N型漂移区4形成了一个寄生的NPN晶体管。随着阳极电压的增加,P+阳极2注入P型漂移区5的空穴逐渐使NPN晶体管(发射极:电子反型层,基极:P型漂移区5,集电极:N型漂移区4/N型电场截止层3)开启,开启后的NPN晶体管注入到电子到N型漂移区4中,使PNP晶体管(发射极:P+集电极2,基极:N型场截止层3,集电极:P型漂移区5)开启。最终肖克来二极管进入PNPN晶闸管导通模式。N型漂移区4以及P型漂移区5都存在电导调制效应,器件导通压降低。
关断时:器件栅极关断,发射极接地和集电极接正电位。此时栅极沟道从开启到关断,电子反型层消失,寄生的NPN晶体管(发射极:电子反型层,基极:P型漂移区5,集电极:N型漂移区4/N型电场截止层3)的发射极消失,肖克来二极管逐渐从PNPN晶闸管导通模式退出,进入PNP晶体管(发射极:P+集电极2,基极:N型场截止层3,集电极:P型漂移区5)耐压状态。由于耐压的N型漂移区4和P型漂移区5这个结位于漂移区内部,器件要耐压的话,电场需在此处建立。由于漂移区内有大量空穴载流子,需要将此PN结附近的浓度降低才能使电场在此PN结建立,因此的话,位于P型漂移区内的空穴在PN结处电场建立前已通过发射极排出,而位于N型漂移区的空穴也降低了。从而在电场建立的时候,P型漂移区内以及N型漂移区内的载流子已急剧降低,并且耗尽区是往两个方向进行耗尽,因此的话,器件内电场建立速度更快,电压上升时间降低,从而器件关断损耗将降低。

Claims (1)

1.一种具有部分P型漂移区的IGBT,其元胞包括集电极结构、耐压层结构、发射极结构和栅极结构,其中耐压层结构位于集电极结构之上,发射极结构和栅极结构位于耐压层结构之上;
所述集电极结构包括集电极金属(1)、P+集电极区(2)和N型场截止层(3);所述集电极金属(1)的下表面引出端为器件的集电极(C);所述P+集电极区(2)位于集电极金属(1)的上表面;所述N型场截止层(3)位于P+集电极区(2)的上表面;
所述发射极结构包括P型阱区(7)、N型发射极区(9)、P型体接触区(8)以及发射极金属(10);所述P型阱区(7)位于耐压层结构上表面;所述N型发射极区(9)和P型体接触区(8)位于P型阱区(7)上表面;所述发射极金属(10)的下表面同时与N型发射极区(9)和P型体接触区(8)的上表面接触,其上表面的引出端为器件的发射极(E);
所述栅极结构为沟槽栅结构,包括绝缘介质(12)和导电材料(11);所述导电材料(11)位于绝缘介质(12)内,引出端为器件的栅极(G);所述绝缘介质(12)从器件表面垂直穿过P型阱区(7)与耐压层结构接触,绝缘介质(12)的侧面与P型阱区(7)和N型发射极区(9)接触;
其特征在于,所述耐压层结构包括N型漂移区(4)和P型漂移区(5),两者呈现上下堆叠的形式;所述N型漂移区(4)的下表面与N型场截止层(3)的上表面接触,上表面与P型漂移区(5)的下表面接触;所述P型漂移区(5)的上表面同时与绝缘介质(12)以及P型阱区(7)的下表面接触。
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