CN117672865B - Silicon carbide groove type MOSFET device and preparation process thereof - Google Patents
Silicon carbide groove type MOSFET device and preparation process thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000007943 implant Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 230000002596 correlated effect Effects 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 7
- 238000002513 implantation Methods 0.000 description 20
- 238000010586 diagram Methods 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000012995 silicone-based technology Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention relates to the field of silicon carbide MOSFET device manufacturing, and discloses a silicon carbide trench MOSFET device and a preparation process thereof; s1, providing a semiconductor substrate with a first surface and a second surface; s2, forming an epitaxial layer on the first surface; s3, depositing a first oxide layer on the epitaxial layer; s4, photoetching the first oxide layer to form a groove; s5, etching is carried out by taking the groove as a reference to form a groove; s6, removing the first oxide layer; s7, forming a second oxide layer in the epitaxial layer and the groove; s8, performing N-type doping injection in an inclined mode, and forming a JFET region in the epitaxial layer; s9, depositing polysilicon in the groove; s10, P-type doping injection is carried out in a vertical mode, and a Pwell region is formed in the epitaxial layer; the Pwell region covers a portion of the JFET region; s11, performing ion implantation and annealing in the Pwell region to form an N+ source region; and S12, preparing a source electrode on the epitaxial layer, and forming a drain electrode on the second surface to finish the preparation.
Description
Technical Field
The invention relates to the technical field of silicon carbide MOSFET device manufacturing, in particular to a silicon carbide trench type MOSFET device and a preparation process thereof.
Background
Silicon carbide MOSFET technology is a power semiconductor device technology based on silicon carbide materials, has excellent characteristics of high temperature, high voltage, high frequency and the like, and gradually becomes one of research hot spots of next-generation power electronic devices. As a third-generation semiconductor material, silicon carbide (SiC) has the advantages of large forbidden bandwidth, high melting point, low dielectric constant, high breakdown field intensity, high saturated electron drift rate, high thermal conductivity, stable chemical property and the like, so that the silicon carbide-based power device has great application prospect in the aspects of high voltage, high temperature, high frequency, high power, strong radiation and the like, and is particularly suitable for manufacturing high-voltage high-power electronic devices. Silicon carbide is a subverted technology, and with the development of new energy automobiles and photovoltaic energy storage fields, silicon-based technology is being replaced, and the silicon carbide is beginning to be widely focused on the market.
However, any kind of dopant in silicon carbide materials is difficult to diffuse. Thus, for silicon carbide devices, multiple implants of dopants at different implant energies are required to form junctions in the epitaxial layer of silicon carbide. Particularly for silicon carbide trench MOSFET processes, JFET junctions are difficult to form due to the very high implantation energy required. The channel length in a trench gate process is defined as the P-well depth. Typically, the P-well junction depth of a trench gate is deeper than the P-well depth of a planar gate. The JFET junction of the trench gate should be at the bottom of the P-well. Thus, a higher energy implant is required to form the JFET junction structure at the bottom of the P-well. As such, JFET junction processes are difficult to form, and JFET junction structures are typically skipped in silicon carbide trench MOSFET processes.
Disclosure of Invention
The invention aims at: aiming at the problem that a JFET structure is difficult to form at the bottom of a P well due to the fact that the P well is deeper in a silicon carbide groove type MOSFET device, the preparation process of the silicon carbide groove type MOSFET device is provided, and the problem is effectively solved.
In order to solve the problems, the invention is realized by the following technical scheme:
the preparation process of the silicon carbide groove type MOSFET device comprises the following steps:
S1, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first surface and a second surface which are opposite;
s2, epitaxially growing on the first surface of the semiconductor substrate to form an epitaxial layer;
S3, depositing a first oxide layer on the upper surface of the epitaxial layer;
S4, photoetching the first oxide layer to form a plurality of grooves, wherein the bottoms of the grooves are epitaxial layers;
s5, etching the epitaxial layer by taking the groove as a reference, so that a plurality of grooves are etched in the epitaxial layer;
s6, removing the residual first oxide layer on the epitaxial layer to obtain the epitaxial layer with the groove structure;
s7, continuing deposition of an oxide layer to form a continuous second oxide layer on the upper surface of the epitaxial layer and inside the groove;
s8, performing N-type doping injection in a manner of inclining relative to the upper surface of the epitaxial layer so as to form a JFET region in the epitaxial layer below the second oxide layer;
s9, polysilicon deposition and planarization are carried out in the grooves;
S10, P-type doping injection is carried out in a mode perpendicular to the upper surface of the epitaxial layer, so that a Pwell region is formed in the epitaxial layer; wherein: the Pwell region covers part of the JFET region;
s11, performing ion implantation in the Pwell region and annealing to form an N+ source region;
and S12, preparing a source electrode on the epitaxial layer, and forming a drain electrode on the second surface of the semiconductor substrate to complete preparation of the MOSFET device.
Specifically, the invention provides a preparation process of a silicon carbide trench MOSFET device with a self-aligned JFET structure.
Further, the semiconductor substrate in step S1 is an N-type heavily doped silicon nitride substrate (n+ substrate), and the doping ions of the substrate are phosphorus ions.
Further, in step S2, the thickness of the epitaxial layer is positively related to the voltage withstanding requirement of the MOSFET device, and the higher the voltage withstanding requirement is, the thicker the thickness of the epitaxial layer is.
Further, in the steps S3 and S7, the first oxide layer and the second oxide layer are both made of silicon dioxide, and the first oxide layer and the second oxide layer are formed by adopting a high-temperature furnace tube process, and the thickness of the first oxide layer and the second oxide layer is set to be 1.0-2.0 μm respectively.
Further, the depth of the trench in step S5 is 6.0-10.0 μm.
Further, the inclination angle of the N-type doped implantation in the step S8 is alpha, and the alpha is more than or equal to 30 degrees and less than or equal to 60 degrees, and the thickness of the JFET region is 1.0-2.0 mu m.
Further, in step S10, the dosage of the P-type doping implantation is higher than that of the N-type doping implantation, and the Pwell region formed after the P-type doping implantation will cover a portion of the JFET region, only a portion of the JFET region near the bottom of the trench sidewall remains, and at this time, the thickness of the remaining JFET region is 1.0-2.0 μm, and the height is 2.0-4.0 μm. Due to the blocking effect of the polysilicon, a Pwell region is not formed in the epitaxial layer at the bottom of the corresponding trench. In addition, since the dosage of the P-type doping implantation is higher than that of the N-type doping implantation, the overlapped area between the JFET region and the Pwell region becomes the Pwell region after the P-type doping implantation.
Further, the annealing temperature in the step S11 is 850-900 ℃, and the annealing time is 90-120 minutes.
Further, in step S12, the source electrode and the drain electrode are formed by using a magnetron sputtering or an electron beam evaporation process, respectively.
The silicon carbide groove type MOSFET device is manufactured by the manufacturing process.
The invention has the beneficial effects that:
Aiming at the problem that a JFET structure is difficult to form at the bottom of a P well because of deeper P well in a silicon carbide trench MOSFET device, the invention provides a preparation process of the silicon carbide trench MOSFET device with a self-aligned JFET structure. The process can realize the formation of JFET structures at different positions by adjusting the injection angle, and solves the problem that the JFET structures are difficult to form at the bottom of the P well of the silicon carbide trench MOSFET device in the prior art.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor substrate in step S1 of embodiment 1 of the present invention;
fig. 2 is a schematic diagram of the structure of the semiconductor substrate after an epitaxial layer is grown in step S2 of embodiment 1 of the present invention;
fig. 3 is a schematic structural diagram of the embodiment 1 of the present invention after depositing a first oxide layer on the surface of the epitaxial layer in step S3;
Fig. 4 is a schematic structural diagram of the embodiment 1 after etching a groove on the first oxide layer in step S4;
Fig. 5 is a schematic structural diagram of the embodiment 1 after etching a trench on an epitaxial layer in step S5;
fig. 6 is a schematic structural diagram of an epitaxial layer with a trench structure formed after removing the first oxide layer in step S6 of embodiment 1;
FIG. 7 is a schematic diagram of the structure of the second oxide layer deposited in step S7 of embodiment 1 of the present invention;
FIGS. 8-10 are schematic diagrams of the N-type dopant oblique implantation in step S8 of embodiment 1 of the present invention;
FIG. 11 is a schematic diagram of the structure of the embodiment 1 after depositing polysilicon in step S9;
FIG. 12 is a schematic diagram of the structure of the P-doped substrate in step S10 of embodiment 1;
fig. 13 is a schematic diagram of a structure of forming an n+ source region in step S11 of embodiment 1 of the present invention.
The marks in the figure: 1-semiconductor substrate, 2-epitaxial layer, 3-first oxide layer, 4-second oxide layer, 5-JFET region, 6-polysilicon, 7-Pwell region, 8-N+ source region, 11-first surface, 12-second surface, 21-trench, 31-recess.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the terms "upper," "lower," "left," "right," "top," "bottom," and the like indicate orientations or positional relationships, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or elements being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
Example 1
The preparation process of the silicon carbide groove type MOSFET device comprises the following specific steps:
S1, providing a semiconductor substrate 1, wherein the semiconductor substrate 1 is provided with a first surface 11 and a second surface 12 which are opposite, as shown in FIG. 1; the semiconductor substrate 1 is an N-type heavily doped silicon nitride substrate (N+ substrate), and the doping ions of the substrate are phosphorus ions;
s2, epitaxially growing on the first surface 11 of the N-type heavily doped silicon nitride substrate 1 to form an epitaxial layer 2, wherein the thickness of the epitaxial layer 2 is positively correlated with the voltage withstand requirement of the MOSFET device, and the higher the voltage withstand requirement is, the thicker the thickness of the epitaxial layer 2 is, as shown in figure 2;
S3, growing a first oxide layer 3 with the thickness of 2.0 mu m on the upper surface of the epitaxial layer 2 by adopting a high-temperature furnace tube process, as shown in FIG. 3; the first oxide layer 3 is a silicon dioxide layer;
s4, photoetching and etching the first oxide layer 3 to form a plurality of grooves 31, wherein the bottoms of the grooves 31 are the epitaxial layers 2, as shown in FIG. 4;
s5, etching the epitaxial layer 2 by taking the groove 31 as a reference, so as to etch a plurality of grooves 21 with the depth of 7.0 mu m in the epitaxial layer 2, as shown in FIG. 5;
S6, removing the residual first oxide layer 3 on the epitaxial layer 2 by using hydrofluoric acid, and obtaining the epitaxial layer 2 with the groove 21 structure, as shown in FIG. 6;
S7, continuing to deposit an oxide layer to form a continuous second oxide layer 4 on the upper surface of the epitaxial layer 2 and the side walls and the bottom of the groove 21, as shown in FIG. 7; the second oxide layer 4 is a silicon dioxide layer with a thickness of 2.0 μm;
S8, performing N-type doping injection in an inclined mode relative to the upper surface of the epitaxial layer 2 so as to form a JFET region 5 with the thickness of 1.5 mu m in the epitaxial layer 2 below the second oxide layer 4; in this process step S8: the inclination angle of N-type doping implantation is defined as alpha, and the alpha is more than or equal to 30 degrees and less than or equal to 60 degrees; in this embodiment, the width-depth ratio 1 of the trench 21 is: 1, for example, a 1.5 μm-thick JFET region 5 is formed in the epitaxial layer 2 below the second oxide layer 4 except for the bottom region of the trench 21 after the N-type doping implantation at an inclination angle α=45°, as shown in fig. 8;
S9, depositing and flattening the polysilicon 6 in the groove 21, as shown in FIG. 11;
S10, performing P-type doping injection in a mode perpendicular to the upper surface of the epitaxial layer 2, so as to form a Pwell region 7 in the epitaxial layer 2; the dosage of the P type doping implantation in the step S10 is higher than that of the N type doping implantation in the step S8;
In this process step S10: the Pwell region 7 formed after P-type doping implantation will cover a portion of the JFET region 5, and only a portion of the JFET region 5 near the bottom of the sidewall of the trench 21 remains, where the thickness of the remaining JFET region 5 is 2.0 μm and the height is 3.0 μm; due to the blocking effect of the polysilicon, a Pwell region 7 is not formed in the epitaxial layer 2 at the bottom of the corresponding trench 21; in addition, since the dosage of the P-type doping implantation is higher than that of the N-type doping implantation, the overlapping area between the JFET region 5 and the Pwell region 7 becomes the Pwell region 7 after the P-type doping implantation; since the etching depth of the trench 21 is 7.0 μm, the Pwell region 7 formed after the P-type doping implantation covers the JFET region 5 4.0 μm high inside the sidewall of the trench 21, thereby including the JFET region 5 3.0 μm high near the bottom of the sidewall of the trench 21, as shown in fig. 12;
s11, performing ion implantation in the Pwell region 7 and annealing at 900 ℃ for 90 minutes, so as to form an N+ source region 8, as shown in FIG. 13;
S12, preparing a source electrode on the epitaxial layer 2 by adopting a magnetron sputtering process, and forming a drain electrode on the second surface 12 of the semiconductor substrate 1 by adopting the magnetron sputtering process to finish the preparation of the silicon carbide groove type MOSFET device; wherein: the metal material of the source electrode is nickel and aluminum, and the metal material of the drain electrode is nickel, titanium and silver.
Example 2
Example 2 differs from example 1 in that: in example 2, the thicknesses of the first oxide layer 3 and the second oxide layer 4 were 1.0 μm; the depth of the trench 21 is 10.0 μm; in the step S11, the annealing temperature is 850 ℃ and the annealing time is 120 minutes; in step S12, the source electrode and the drain electrode are formed by using an electron beam evaporation process.
In the process of the invention: the JFET structure (JFET region 5) can be formed at different positions by adjusting the size of the tilt angle α, and the width-to-depth ratio of the trench 21 is 1:1 example, when the tilt angle α is increased, for example, when the tilt angle α=60°, the JFET region 5 is not formed at the bottom of the trench 21 and at the region near the bottom inside the sidewall of the trench 21 after the N-type doping implantation, and the JFET region 5 with a thickness of 1.5 μm is formed under the second oxide layer 4 in the other region, and the JFET structure is located near the opening of the trench 21, as shown in fig. 9;
Conversely, when the tilt angle α is smaller, for example, when the tilt angle α=30°, the JFET region 5 is also formed at the bottom of the trench 21 after the N-type doping implantation, as shown in fig. 10.
Remarks: MOSFET: a metal oxide semiconductor field effect transistor; JFET region: junction field effect transistor regions; pwell region: and P well injection region.
The above-described preferred embodiments of the present invention are only for illustrating the present invention, and are not to be construed as limiting the present invention. Obvious changes and modifications of the invention, which are introduced by the technical solution of the present invention, are still within the scope of the present invention.
Claims (10)
1. The preparation process of the silicon carbide groove type MOSFET device is characterized by comprising the following steps of:
s1, providing a semiconductor substrate (1), wherein the semiconductor substrate (1) is provided with a first surface (11) and a second surface (12) which are opposite;
s2, epitaxially growing on the first surface (11) of the semiconductor substrate (1) to form an epitaxial layer (2);
s3, depositing a first oxide layer (3) on the surface of the epitaxial layer (2);
S4, photoetching the first oxide layer (3) to form a plurality of grooves (31);
S5, etching the epitaxial layer (2) by taking the groove (31) as a reference, so as to form a plurality of grooves (21) in the epitaxial layer (2);
S6, removing the residual first oxide layer (3) on the epitaxial layer (2);
S7, continuing the deposition of an oxide layer to form a continuous second oxide layer (4) on the surface of the epitaxial layer (2) and in the groove (21);
S8, performing N-type doping injection in an inclined mode relative to the surface of the epitaxial layer (2) so as to form a JFET region (5) in the epitaxial layer (2) below the second oxide layer (4);
wherein: the inclination angle of the N-type doping injection is alpha, and the alpha is more than or equal to 30 degrees and less than or equal to 60 degrees;
s9, depositing and flattening polycrystalline silicon (6) in the groove (21);
s10, performing P-type doping injection in a mode perpendicular to the surface of the epitaxial layer (2) so as to form a Pwell region (7) in the epitaxial layer (2);
Wherein: the Pwell region (7) covers part of the JFET region (5);
s11, performing ion implantation in the Pwell region (7) and annealing to form an N+ source region (8);
s12, preparing a source electrode on the epitaxial layer (2), and forming a drain electrode on the second surface (12) of the semiconductor substrate (1), so as to complete preparation of the MOSFET device.
2. The process for fabricating a silicon carbide trench MOSFET device according to claim 1, wherein the semiconductor substrate (1) in step S1 is an N-type heavily doped silicon nitride substrate.
3. A process for the preparation of a silicon carbide trench MOSFET device according to claim 1, wherein the thickness of the epitaxial layer (2) in step S2 is positively correlated to the withstand voltage requirements of the MOSFET device.
4. The process for preparing a silicon carbide trench MOSFET device according to claim 1, wherein in steps S3 and S7, the materials of the first oxide layer (3) and the second oxide layer (4) are silicon dioxide, and the first oxide layer (3) and the second oxide layer (4) are grown by a high temperature furnace tube process, and the thickness of the first oxide layer and the second oxide layer is set to be 1.0-2.0 μm respectively.
5. The process for fabricating a silicon carbide trench MOSFET device according to claim 1, wherein the depth of the trench (21) in step S5 is 6.0-10.0 μm.
6. The process for fabricating a silicon carbide trench MOSFET device according to claim 1, characterized in that the JFET region (5) has a thickness of 1.0 μm to 2.0 μm.
7. The process according to claim 1, wherein the P-type doping implant is performed at a higher dose than the N-type doping implant in step S10, and the Pwell region (7) formed by the P-type doping implant covers a portion of the JFET region (5), leaving only the JFET region (5) near the bottom of the sidewall of the trench (21).
8. The process for fabricating a silicon carbide trench MOSFET device according to claim 1, wherein the annealing temperature in step S11 is 850-900 ℃ and the annealing time is 90-120 minutes.
9. The process according to claim 1, wherein the source and the drain are formed in step S12 by using a magnetron sputtering or electron beam evaporation process.
10. A silicon carbide trench MOSFET device produced by the process of any one of claims 1 to 9.
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| CN202410125190.3A CN117672865B (en) | 2024-01-30 | 2024-01-30 | Silicon carbide groove type MOSFET device and preparation process thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2010232627A (en) * | 2009-03-04 | 2010-10-14 | Fuji Electric Systems Co Ltd | Semiconductor device and method of manufacturing the same |
| CN203983264U (en) * | 2013-10-30 | 2014-12-03 | 英飞凌科技奥地利有限公司 | Semiconductor device |
| CN110366782A (en) * | 2017-03-06 | 2019-10-22 | 三菱电机株式会社 | The manufacturing method of manufacturing silicon carbide semiconductor device, power-converting device, the manufacturing method of manufacturing silicon carbide semiconductor device and power-converting device |
| JP2020096080A (en) * | 2018-12-12 | 2020-06-18 | トヨタ自動車株式会社 | Method of manufacturing semiconductor device |
| CN114823910A (en) * | 2022-06-29 | 2022-07-29 | 瑞能半导体科技股份有限公司 | Short channel trench type silicon carbide transistor and method of manufacturing the same |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010232627A (en) * | 2009-03-04 | 2010-10-14 | Fuji Electric Systems Co Ltd | Semiconductor device and method of manufacturing the same |
| CN203983264U (en) * | 2013-10-30 | 2014-12-03 | 英飞凌科技奥地利有限公司 | Semiconductor device |
| CN110366782A (en) * | 2017-03-06 | 2019-10-22 | 三菱电机株式会社 | The manufacturing method of manufacturing silicon carbide semiconductor device, power-converting device, the manufacturing method of manufacturing silicon carbide semiconductor device and power-converting device |
| JP2020096080A (en) * | 2018-12-12 | 2020-06-18 | トヨタ自動車株式会社 | Method of manufacturing semiconductor device |
| CN114823910A (en) * | 2022-06-29 | 2022-07-29 | 瑞能半导体科技股份有限公司 | Short channel trench type silicon carbide transistor and method of manufacturing the same |
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