CN114880972A - Verification method supporting error injection verification test and computer readable medium - Google Patents
Verification method supporting error injection verification test and computer readable medium Download PDFInfo
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- CN114880972A CN114880972A CN202210418192.2A CN202210418192A CN114880972A CN 114880972 A CN114880972 A CN 114880972A CN 202210418192 A CN202210418192 A CN 202210418192A CN 114880972 A CN114880972 A CN 114880972A
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- 238000002347 injection Methods 0.000 title claims abstract description 90
- 239000007924 injection Substances 0.000 title claims abstract description 90
- 238000012795 verification Methods 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000012360 testing method Methods 0.000 title claims abstract description 28
- 238000012544 monitoring process Methods 0.000 claims abstract description 13
- 238000012986 modification Methods 0.000 claims abstract description 5
- 230000004048 modification Effects 0.000 claims abstract description 5
- 238000004891 communication Methods 0.000 claims description 4
- 238000013461 design Methods 0.000 description 12
- 238000001514 detection method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 230000005284 excitation Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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Abstract
The invention discloses a verification method and a computer readable medium for supporting error injection verification test, wherein the verification method comprises the following steps: creating a sequence element, wherein the sequence element carries the type of error injection to be tested; creating a driver, performing error injection and modification on the received data of the sequence elements by the driver according to the type of the error injection, and driving the modified data of the sequence elements to an external interface bus; adding a member variable capable of identifying the type of error injection into the transaction data; creating a monitor, wherein the monitor monitors the type of error injection contained in the current path of the interface bus; a verification analysis component is created and the monitor inputs the type of error injection monitored under the verification analysis component and a functional component of an error monitoring mechanism associated with the DUT for verification analysis. The invention can flexibly control the switch according to the actual project requirements, thus being completely compatible with the structure of the verification platform under the existing scheme.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to a verification method and a computer readable medium for supporting an error injection verification test.
Background
In a verification environment, a verification platform for an RTL (Register Transfer Level) design (here, DUT, design to be tested) is usually built by using a UVM, as shown in fig. 1, which is a typical architecture based on the UVM verification platform, where a DUT is connected to the verification platform by using an interface, and then a sequence stimulus is written and driven to the interface via a related verification component to be applied to an input end of the DUT, and then an output end signal of the DUT is monitored and broadcast to an analysis component for analysis and comparison, so as to determine correctness of a behavior function of the DUT.
The above scheme is the verification scheme for the DUT that we usually adopt, but in the actual verification work, the following two cases of data errors need to be considered:
(1) violation errors of the timing bus protocol may occur in a real verification platform
This should not be the case and should be avoided by design and verification personnel, but the verification platform needs to be able to identify and alert developers to make corrections.
(2) Errors in signal transmission
During data transmission in an actual chip, errors occur in one or more frame data transmitted on a link due to a transmission system. In this case, it is necessary for the RTL design to have an error detection mechanism, and only receive the data when the detection result is correct, so as to improve the correctness of data transmission as much as possible.
In this case, then, we correspondingly need to test the RTL design with error detection mechanism for error injection to verify the relevant error detection function of the RTL design in case of erroneous transmission data.
The above prior art schemes do not take the scenario of the erroneous injection test into consideration at the beginning, and therefore, the prior art schemes need to be improved to meet the requirement of the actual chip verification. The patent provides a verification platform structure suitable for error injection test on the basis of the existing scheme, and can be conveniently applied to perform verification of behavior function on an RTL design with a similar error detection mechanism function.
Disclosure of Invention
According to an embodiment of the present invention, a verification method supporting an error injection verification test is provided, which includes the following steps:
creating a sequence element, wherein the sequence element carries the type of error injection to be tested;
creating a driver, performing error injection and modification on the received data of the sequence elements by the driver according to the type of the error injection, and driving the modified data of the sequence elements to an external interface bus;
adding a member variable capable of identifying the type of error injection into the transaction data;
creating a monitor, wherein the monitor monitors the type of error injection contained in the current path of the interface bus;
a verification analysis component is created and the monitor inputs the type of error injection monitored under the verification analysis component and a functional component of an error monitoring mechanism associated with the DUT for verification analysis.
Further, the type of error injection carried by the sequence element and required to be tested is specifically:
adding data members related to local error injection in sequence elements;
creating a sequence with error injection, and randomly generating sequence elements contained in the sequence with error injection;
and covering the error injection related data member variable of the contained sequence element by using the local error injection related data member variable as the type of error injection needing to be tested.
Further, error injection is turned off by default through random constraints when adding local error injection related data members in the sequence elements.
Further, a driving logic with error injection is added to a driving method in the driver.
Further, error injection monitoring logic is added in the monitor.
Further, the monitor broadcasts the type of error injection monitored to the verification analysis component and the functional component of the DUT related error monitoring mechanism through the communication port for verification analysis.
According to yet another embodiment of the present invention, there is provided a computer readable medium having non-volatile program code executable by a processor, the program code causing the processor to execute a verification method that supports an error injection verification test.
The verification method and the computer readable medium for supporting the error injection verification test according to the embodiment of the invention have the following beneficial effects:
(1) under the default condition, the error injection test is not carried out, and the on-off control can be flexibly carried out according to the actual project requirement, so that the method is completely compatible with the verification platform structure under the existing scheme.
(2) And sufficient flexibility is provided, and a verification developer can select a fault injection mode to be added by himself so as to carry out various types of fault injection tests according to actual project requirements, thereby comprehensively verifying the fault monitoring behavior function of the DUT.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the claimed technology.
Drawings
Fig. 1 is a typical architecture diagram of a UVM-based verification platform.
FIG. 2 is a flowchart of a verification method for supporting error injection verification testing according to an embodiment of the present invention.
Fig. 3 is a schematic view of the method according to fig. 2.
FIG. 4 is a diagram of an example of a frame data format of an error monitoring mechanism of a verification method supporting an error injection verification test according to an embodiment of the invention.
Detailed Description
The present invention will be further explained by describing preferred embodiments of the present invention in detail with reference to the accompanying drawings.
First, a verification method supporting error injection verification testing according to an embodiment of the present invention will be described with reference to fig. 2 to 3, which is used for verifying chips with different performances and different modes, and has a wide application range.
As shown in fig. 2 to 3, the verification method for supporting the error injection verification test according to the embodiment of the present invention includes the following steps:
in S1, as shown in fig. 2, a sequence element sequence _ item is created, which carries the type of error injection that needs to be tested.
Further, the type of error injection carried by the sequence element and required to be tested is specifically: adding a local error injection related data member in the sequence _ item of the sequence element; creating a sequence with error injection, and randomly generating a sequence element sequence item contained in the sequence with error injection; and covering the error injection related data member variable of the contained sequence element sequence item by using the local error injection related data member variable as the type of error injection needing to be tested.
Further, error injection is turned off by default through random constraints when adding local error injection related data members in the sequence elements.
In S2, as shown in fig. 2, a driver is created, and the driver performs error injection and modification on the received data of the sequence element sequence _ item according to the type of error injection, and drives the modified data of the sequence element sequence _ item to an external interface bus. In this embodiment, a driving logic with error injection is added to the driving method in the driver.
In S3, as shown in fig. 2, a member variable capable of identifying the type of error injection is added to the transaction data transaction. In this embodiment, transaction data (transaction) is the smallest data unit in each submodule of the chip, which is a class, and interface signal data for communication between modules is packaged. Adding member variables of the type of error injection means that the input excitation signal which we want to apply is driven to an interface of the design to be tested by writing transaction data, and signals which can cause errors or abnormalities of the function of the design to be tested are added in the input excitation signal to detect the behavior and output of the design to be tested in the error excitation scene, so as to further judge whether the function of the design to be tested meets the design target.
In S4, as shown in fig. 2, a monitor is created that monitors the type of error injection contained on the current path of the interface bus. In this embodiment, an error injection monitoring logic is added to the monitor.
At S5, as shown in fig. 2, a verification analysis component is created, and the monitor broadcasts and inputs the type of error injection monitored to the verification analysis component and the DUT-related error monitoring mechanism functional component for verification analysis through the communication port. In this embodiment, as shown in fig. 4, an example of a frame data format of the error monitoring mechanism includes: start of frame data (SOF), Payload data (Payload), Cyclic Redundancy Check (CRC) data, and end of frame data (EOF).
Verification methods for supporting error injection verification tests according to embodiments of the present invention are described above with reference to fig. 2-3. Further, the present invention can also be applied to a computer-readable medium having a non-volatile program code executable by a processor.
A computer-readable medium having non-volatile program code executable by a processor, the program code causing the processor to run a verification method that supports an error injection verification test, in accordance with an embodiment of the present invention.
The verification method and the computer readable medium for supporting the error injection verification test according to the embodiment of the invention are described above with reference to fig. 2 to 3, and have the following beneficial effects:
(1) under the default condition, the error injection test is not carried out, and the on-off control can be flexibly carried out according to the actual project requirement, so that the method is completely compatible with the verification platform structure under the existing scheme.
(2) And sufficient flexibility is provided, and a verification developer can select a fault injection mode to be added by himself so as to carry out various types of fault injection tests according to actual project requirements, thereby comprehensively verifying the fault monitoring behavior function of the DUT.
It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (7)
1. A verification method for supporting error injection verification testing, comprising the steps of:
creating a sequence element, wherein the sequence element carries the type of error injection to be tested;
creating a driver, performing error injection and modification on the received data of the sequence elements by the driver according to the type of the error injection, and driving the modified data of the sequence elements to an external interface bus;
adding a member variable capable of identifying the type of error injection into the transaction data;
creating a monitor that monitors a type of the error injection contained on a current path of the interface bus;
creating a verification analysis component, wherein the monitor inputs the type of error injection monitored under the verification analysis component and an error monitoring mechanism functional component related to the DUT for verification analysis.
2. The verification method supporting error injection verification testing as claimed in claim 1, wherein the type of error injection carried by the sequence element to be tested is specifically:
adding local error injection related data members in the sequence elements;
creating a sequence with error injection, and randomly distributing sequence elements contained in the sequence with error injection;
and covering the error injection related data member variable of the contained sequence element by using the local error injection related data member variable as the type of error injection needing to be tested.
3. The verification method supporting error injection verification testing of claim 2, wherein error injection defaults are turned off by random constraints when adding local error injection related data members in the sequence elements.
4. The verification method for supporting error injection verification testing of claim 1, wherein a driving logic with error injection is added to a driving method in the driver.
5. A verification method supporting error injection verification testing as claimed in claim 1, wherein error injection monitoring logic is added to said monitor.
6. A verification method supporting error injection verification testing as claimed in claim 1 wherein said monitor broadcasts the type of said error injection monitored to said verification analysis component and DUT related error monitoring mechanism functional component for verification analysis via a communication port.
7. A computer-readable medium having non-volatile program code executable by a processor, the program code causing the processor to execute the verification method supporting error injection verification testing of any one of claims 1 to 6.
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| CN202210418192.2A CN114880972A (en) | 2022-04-21 | 2022-04-21 | Verification method supporting error injection verification test and computer readable medium |
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| CN202210418192.2A CN114880972A (en) | 2022-04-21 | 2022-04-21 | Verification method supporting error injection verification test and computer readable medium |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117687395A (en) * | 2024-02-02 | 2024-03-12 | 苏州旗芯微半导体有限公司 | Self-checking circuit and self-checking method for safety mechanism of microcontroller functional module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117687395A (en) * | 2024-02-02 | 2024-03-12 | 苏州旗芯微半导体有限公司 | Self-checking circuit and self-checking method for safety mechanism of microcontroller functional module |
| CN117687395B (en) * | 2024-02-02 | 2024-04-16 | 苏州旗芯微半导体有限公司 | Self-checking circuit and self-checking method for safety mechanism of microcontroller functional module |
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