CN114823967A - Preparation method of solar cell and solar cell - Google Patents
Preparation method of solar cell and solar cell Download PDFInfo
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- CN114823967A CN114823967A CN202210235077.1A CN202210235077A CN114823967A CN 114823967 A CN114823967 A CN 114823967A CN 202210235077 A CN202210235077 A CN 202210235077A CN 114823967 A CN114823967 A CN 114823967A
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- 238000000034 method Methods 0.000 claims abstract description 127
- 239000000758 substrate Substances 0.000 claims abstract description 56
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a preparation method of a solar cell and the solar cell, and relates to the technical field of solar photovoltaics. The method adopts one-time wet etching and multiple times of laser ablation in the process of carrying out emitter and back surface field patterning on the back surface of the silicon substrate, and the laser ablation process has the advantages of high processing speed, high precision, low cost and little pollution, so the laser ablation is adopted to effectively simplify the process and reduce the cost, improve the patterning precision and reduce the damage by reducing the wet etching times with fussy implementation operation, high cost and great pollution, thereby improving the finished product quality of the HBC battery.
Description
Technical Field
The invention relates to the technical field of solar photovoltaics, in particular to a solar cell and a preparation method thereof.
Background
A Silicon-amorphous Silicon Heterojunction (SHJ) cell is characterized in that intrinsic hydrogenated amorphous Silicon is deposited on the surface of crystalline Silicon to passivate surface defects, and a doped hydrogenated amorphous Silicon film is deposited to prepare a heterojunction. Furthermore, in order to improve the short-circuit current of the SHJ cell, a back contact Heterojunction-IBC (HBC) cell can be adopted, and the HBC cell is provided with an electron collection layer and a hole collection layer at the same time by adopting interdigital arrangement at the back surface, so that the two collection layers are arranged in a periodic finger shape and a comb shape at the back surface, thereby avoiding the loss caused by arranging grid lines, amorphous silicon, a transparent conductive film and the like at the front surface of the solar cell, and improving the short-circuit current of the SHJ cell.
At present, two collecting layers in interdigital arrangement are generally prepared on the back surface of an HBC battery by adopting the processes of photoetching, screen printing, masking and the like, most processes need to place a masking plate at least twice or etch different patterns at least twice by a wet method, so that the operation of using the masking plate and etching solution is complex, the cost is higher, and meanwhile, the problems of low alignment precision and large damage can exist, and the quality of a finished product is influenced.
Disclosure of Invention
The invention provides a preparation method of a solar cell and the solar cell, aiming at simplifying the preparation process of an HBC cell, reducing the manufacturing cost, improving the patterning precision in the process, reducing the damage and improving the finished product quality of the HBC cell.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a solar cell, where the method may include:
providing a silicon substrate, wherein the silicon substrate comprises a back surface provided with an electrode and a front surface opposite to the back surface;
depositing a first passivation layer and a dielectric insulating layer on the back surface in sequence;
forming a first opening on the first passivation layer and the dielectric insulating layer by laser ablation;
preparing a back surface field on the back surface, wherein the back surface field comprises a second passivation layer and an electron collection layer;
forming a second opening in the electron collection layer by laser ablation, the second opening being spaced apart from the first opening;
forming a third opening at the position of the second opening on the second passivation layer, the dielectric insulating layer and the first passivation layer by wet etching, wherein the etching rate of an etchant used by the wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer is greater than that of the etchant used by the wet etching on the electron collecting layer;
preparing an emitter on the back surface, wherein the emitter comprises a third passivation layer and a hole collecting layer;
forming a fourth opening in the third passivation layer and the hole collection layer at the location of the first opening using laser ablation.
Optionally, a center position of the fourth opening overlaps a center position of the first opening.
Optionally, a width of the fourth opening is smaller than or equal to a width of the first opening and smaller than a width of the third opening.
Optionally, the second passivation layer is a SiOx layer.
Optionally, the electron collection layer is a Poly-Si (n +) layer.
Optionally, the third passivation layer is an a-Si: h (i) layer.
Optionally, the hole-collecting layer is any one of an a-Si: H (p +) layer, an a-SiOx: H (p +) layer, an a-SiCx: H (p +) layer, and an a-SiOxCy: H (p +) layer.
Optionally, the laser ablation comprises any one of a nano-pulse laser, a picosecond pulse laser.
Optionally, the laser wavelength of the laser ablation comprises any one of 355 nm, 532 nm, 1064 nm.
Optionally, the thickness of the first passivation layer is less than 50 nm.
Optionally, the dielectric insulating layer has a thickness of less than 500 nm.
Optionally, the thickness of the second passivation layer is less than 5 nm.
Optionally, the thickness of the electron collection layer is less than 500 nm.
Optionally, the thickness of the third passivation layer is less than 50 nm.
Optionally, the hole-collecting layer has a thickness of less than 100 nm.
Optionally, after the preparing an emitter on the back side, the emitter including a third passivation layer and a hole collection layer, the method further includes:
depositing a fourth passivation layer and an anti-reflection layer on the front surface in sequence;
optionally, after forming a fourth opening on the third passivation layer and the hole collection layer at the position of the first opening by using laser ablation, the method further includes:
depositing a transparent conductive layer on the back surface;
forming a fifth opening between the fourth opening and the third opening of the back surface by using laser ablation, wherein the fifth opening penetrates through the transparent conducting layer and at least partially retains the dielectric insulating layer;
and preparing a metal electrode on the back surface.
Optionally, the thickness of the fourth passivation layer is less than 20 nm.
Optionally, the thickness of the anti-reflection layer is less than 100 nm.
In a second aspect, embodiments of the present invention provide a solar cell, including a back side on which electrodes are disposed, and a front side opposite to the back side;
the emitter and the back surface field in the back surface are arranged in an interdigital periodic manner, and the back surface field comprises SiOx/Poly-Si (n +) layers.
Optionally, the solar cell is prepared by the preparation method of the first aspect.
In the implementation of the invention, one side of the silicon substrate, which is provided with the electrodes, is used as a back surface, one side opposite to the back surface is used as a front surface, in a back surface field and emitter patterning process of the back surface, a first passivation layer and a dielectric insulating layer are sequentially deposited on the back surface, and then laser ablation is adopted to form a first opening on the first passivation layer and the dielectric insulating layer to expose the silicon substrate; preparing a back surface field layer on the back surface, wherein the back surface field comprises a second passivation layer and an electron collection layer; forming a second opening on the electron collection layer by laser ablation, wherein the second opening is spaced from the first opening; forming a third opening at the position of the second opening on the second passivation layer, the dielectric insulating layer and the first passivation layer by wet etching, wherein the etching rate of an etchant adopted by the wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer is greater than that of an etchant adopted by the wet etching on the electron collecting layer, so that the electron collecting layer containing the second opening is used as a mask in the process of wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer, and a third opening penetrating through the electron collecting layer, the second passivation layer, the dielectric insulating layer and the first passivation layer is formed at the second opening; and preparing an emitter electrode on the back surface, wherein the emitter electrode comprises a third passivation layer and a hole collecting layer, and laser ablation can be adopted to form a fourth opening on the third passivation layer and the hole collecting layer at the position of the first opening. In the implementation of the invention, the process of patterning the back emitter and the back surface field of the silicon substrate adopts one-time wet etching and multiple times of laser ablation, and the laser ablation process has the advantages of high processing speed, high precision, low cost and little pollution, so the process can be effectively simplified, the cost can be reduced, the patterning precision can be improved, the damage can be reduced by reducing the wet etching with fussy implementation operation, high cost and great pollution, and the finished product quality of the HBC battery can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 shows one of the steps of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 2 is a flow chart showing a second step of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 3 is a schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 4 is a second schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 5 is a third schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 6 is a fourth schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 7 is a fifth schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 8 is a sixth schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 9 is a seventh schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 10 is an eighth schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 11 is a ninth schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 12 is a ten-step schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 13 is an eleventh schematic view of a process flow of a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 14 is a twelve-step schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 shows one of the flow charts of the steps of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 1, the method may include:
In the embodiment of the invention, the patterning process can be applied to the patterning process of the back emitter and the back surface field of the HBC cell, wherein the silicon substrate can be a crystalline silicon substrate which is subjected to cleaning, texturing and the like, the silicon substrate can comprise a back surface on which the electrodes are arranged on one side, and a front surface opposite to the back surface, and the front surface of the silicon substrate is the light incident side of the solar cell. Optionally, the light incident side of the silicon substrate may be subjected to texturing treatment, so that the front side of the silicon substrate on the light incident side has a light trapping structure, an antireflection effect is achieved, and the performance of a finished solar cell is ensured.
And 102, sequentially depositing a first passivation layer and a dielectric insulating layer on the back surface.
In the embodiment of the invention, the first passivation layer can be deposited on the back surface of the silicon substrate firstly, the first passivation layer can passivate dangling bonds on the surface of the silicon substrate, surface recombination of surface carriers is reduced, and the efficiency of the cell is improved.
In the embodiment of the invention, a dielectric insulating layer can be deposited on the first passivation layer to form a composite layer of the first passivation layer and the dielectric insulating layer on the back surface of the silicon substrate, and the dielectric insulating layer is used for insulating an electron collecting region and a hole collecting region on the back surface of the solar cell. The dielectric insulating layer can be prepared by deposition by adopting a chemical vapor deposition method.
In the embodiment of the invention, laser ablation may be adopted to remove a part of the composite layer of the first passivation layer and the dielectric insulating layer to form the first opening, a part of the area of the silicon substrate is exposed through the first opening after removal, and the other area is covered by the first passivation layer and the dielectric insulating layer.
And 104, preparing a back surface field on the back surface, wherein the back surface field comprises a second passivation layer and an electron collection layer.
In the embodiment of the present invention, a back surface field may be prepared on the back surface, for example, a second passivation layer may be deposited on the back surface of the silicon substrate, and then an electron collection layer is deposited on the second passivation layer to form a composite layer, so as to obtain the back surface field, where the second passivation layer contacts the silicon substrate through the first opening portion, and the other portions cover the dielectric insulating layer, and the second passivation layer may correspond to the description related to the first passivation layer, and is not repeated herein in order to avoid repetition; the electron collecting layer is used for realizing selective electron transport, a material having selective electron transport performance can be selected, and optionally, the electron collecting layer can be prepared by adopting a chemical vapor deposition method.
And 105, forming a second opening on the electron collecting layer by using laser ablation, wherein the second opening is spaced from the first opening.
In an embodiment of the present invention, laser ablation may be adopted to remove a portion of the electron collection layer, so as to form a second opening on the electron collection layer, after removal, the second passivation layer is exposed through the second opening portion on the electron collection layer, and other portions are covered by the electron collection layer, where the shape, position, and size of the second opening may be arranged according to a patterning requirement of the emitter, the second opening and the first opening are spaced at the back based on a requirement that the surface field and the emitter are arranged in an interdigitated manner, and widths, intervals, and the like of the second opening and the first opening may be set according to performance, specification, and the like of a specific battery, and process conditions, and the like, which is not particularly limited in this embodiment of the present invention.
And 106, forming a third opening at the position of the second opening on the second passivation layer, the dielectric insulating layer and the first passivation layer by adopting wet etching, wherein the etching rate of an etchant adopted by the wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer is greater than that of the etchant adopted by the wet etching on the electron collecting layer.
In the embodiment of the invention, the second passivation layer, the dielectric insulating layer and the first passivation layer under the second opening on the electron collecting layer can be removed by wet etching to form the third opening. Due to the difference of material characteristics, an etchant with the etching rate of the second passivation layer, the dielectric insulating layer and the first passivation layer higher than that of the electron collecting layer can be adopted, so that the electron collecting layer can be used as a mask in wet etching in the etching process, the silicon substrate is exposed through the third opening after etching, and other parts are covered by the first passivation layer.
In the embodiment of the present invention, an emitter may be prepared on the back surface of the silicon substrate, for example, a third passivation layer may be deposited on the back surface of the silicon substrate, and then a hole collection layer may be deposited on the third passivation layer to prepare a composite layer as the emitter, where a portion of the third passivation layer contacts the silicon substrate through the third opening, and the other portion covers the electron collection layer, where the third passivation layer may refer to the related description of the first passivation layer, and is not described herein again to avoid repetition; the hole collecting layer is used for realizing hole selective transmission, a material with selective transmission performance on holes can be selected, and optionally, the hole collecting layer can be prepared by adopting a chemical vapor deposition method.
In the embodiment of the invention, the third passivation layer and the hole collection layer at the position of the first opening may be removed by laser ablation to form a fourth opening, so that the electron collection layer is exposed through the fourth opening, and the hole collection layer is exposed through a third opening spaced from the fourth opening, so that the electron collection layer and the hole collection layer may be spaced apart from each other in the back surface of the silicon substrate.
In the implementation of the invention, one side of the silicon substrate, which is provided with the electrodes, is used as a back surface, one side opposite to the back surface is used as a front surface, in a back surface field and emitter patterning process of the back surface, a first passivation layer and a dielectric insulating layer are sequentially deposited on the back surface, and then laser ablation is adopted to form a first opening on the first passivation layer and the dielectric insulating layer to expose the silicon substrate; preparing a back surface field layer on the back surface, wherein the back surface field comprises a second passivation layer and an electron collection layer; forming a second opening on the electron collection layer by laser ablation, wherein the second opening is spaced from the first opening; forming a third opening at the position of the second opening on the second passivation layer, the dielectric insulating layer and the first passivation layer by wet etching, wherein the etching rate of an etchant adopted by the wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer is greater than that of an etchant adopted by the wet etching on the electron collecting layer, so that the electron collecting layer containing the second opening is used as a mask in the process of wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer, and a third opening penetrating through the electron collecting layer, the second passivation layer, the dielectric insulating layer and the first passivation layer is formed at the second opening; and preparing an emitter electrode on the back surface, wherein the emitter electrode comprises a third passivation layer and a hole collecting layer, and laser ablation can be adopted to form a fourth opening on the third passivation layer and the hole collecting layer at the position of the first opening. In the implementation of the invention, the process of patterning the back emitter and the back surface field of the silicon substrate adopts one-time wet etching and multiple times of laser ablation, and the laser ablation process has the advantages of high processing speed, high precision, low cost and little pollution, so the process can be effectively simplified, the cost can be reduced, the patterning precision can be improved, the damage can be reduced by reducing the wet etching with fussy implementation operation, high cost and great pollution, and the finished product quality of the HBC battery can be improved.
Referring to fig. 2, fig. 2 shows a second flow chart of steps of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 2, the method may include:
In the embodiment of the present invention, step 201 may correspond to the related description referring to step 101, so as to avoid repetition, which is not described herein again.
Fig. 3 is a schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 3, a silicon substrate 1 is provided, where the silicon substrate 1 includes a back surface 1a provided with an electrode and a front surface 1b opposite to the back surface 1a, the back surface 1a is a planar structure, and the front surface 1b is a textured light trapping structure.
In this embodiment of the present invention, the first passivation layer 2 may include silicon oxide, hydrogenated amorphous silicon, and other materials capable of passivating the surface dangling bonds, and the dielectric insulating layer 3 may include silicon oxide, silicon nitride, and other insulating materials, which may be referred to the related description of step 102 specifically, and will not be described herein again to avoid repetition.
Optionally, the thickness of the first passivation layer 2 is less than 50 nm.
Optionally, the thickness of the dielectric insulating layer 3 is less than 500 nm.
In the embodiment of the present invention, the thicknesses of the first passivation layer 2 and the dielectric insulating layer 3 deposited on the back surface 1a of the silicon substrate 1 may be selected according to process conditions, application requirements, and the like, optionally, the thickness of the first passivation layer 2 may be any thickness smaller than 50nm, and the thickness of the dielectric insulating layer 3 may be any thickness smaller than 500 nm.
Fig. 4 is a second process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 4, a first passivation layer 2 and a dielectric insulating layer 3 are sequentially deposited on the back surface 1a of the silicon substrate 1.
In the embodiment of the present invention, step 203 may refer to the related description of step 103, and is not repeated herein to avoid repetition.
Optionally, the laser ablation comprises a nano-pulsed laser or a picosecond pulsed laser.
In the embodiment of the invention, laser ablation is a process of forming a microstructure by transmitting heat to the surface of a material through a high-energy laser beam to melt and gasify the irradiated area, and the laser ablation can adopt nano pulse laser, picosecond pulse laser and the like, wherein the nano pulse laser refers to a laser process of adopting a nano material as a resonant cavity and generating laser under optical excitation or electric excitation, and the size of the nano pulse laser can reach the nano level; the picosecond pulse laser is a laser process with picosecond-level ultrashort pulse width, adjustable repetition frequency and high pulse energy, can realize high-speed and high-precision material processing, and can realize rapid and high-precision patterning by adopting the process to implement laser ablation.
Optionally, the laser wavelength of the laser ablation comprises 355 nm, 532 nm or 1064 nm.
In the embodiment of the present invention, the laser wavelength selected in the laser ablation process may be 355 nm, 532 nm, or 1064 nm, and different laser wavelengths may be selected and used according to the characteristics of the material to the laser wavelength absorption, the process conditions, and the like, which is not limited in the embodiment of the present invention.
Fig. 5 is a third process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 5, a first opening 4 is formed by removing a portion of the first passivation layer 2 and the dielectric insulating layer 3 by laser ablation, and at this time, the silicon substrate 1 is exposed through the first opening 4. The first opening 4 is merely an example, and the shape, position, and number of the first opening 4 are not particularly limited in the implementation of the present invention.
In the embodiment of the present invention, step 204 may correspond to the related description of step 104, and is not repeated herein to avoid repetition.
Optionally, the second passivation layer 5 is a SiOx layer.
Optionally, the electron collection layer 6 is a Poly-Si (n +) layer.
In the embodiment of the invention, the second passivation layer 5 in the back surface field can be a silicon oxide SiOx layer, the electron collection layer 6 can be a Poly-Si (n +) layer, so that the back surface field of the back surface 1a in the solar cell adopts a silicon oxide passivation layer/phosphorus-doped polysilicon SiOx/Poly-Si (n +) layer structure with higher electron collection capability, and the hole collection adopts an intrinsic hydrogenated amorphous silicon passivation layer/boron-doped hydrogenated amorphous silicon a-Si (H) (i)/a-Si: H (p +) layer structure.
Optionally, the thickness of the second passivation layer 5 is less than 5 nm.
Optionally, the thickness of the electron collecting layer 6 is less than 500 nm.
In the embodiment of the present invention, when the back surface field is prepared on the back surface 1a of the silicon substrate 1, the thicknesses of the deposited second passivation layer 5 and the electron collection layer 6 may be selected according to process conditions, application requirements, and the like, optionally, the thickness of the second passivation layer 5 may be any thickness less than 5nm, and the thickness of the electron collection layer 6 may be any thickness less than 500 nm.
Fig. 6 is a fourth process flow diagram of the method for manufacturing a solar cell according to the embodiment of the present invention, as shown in fig. 6, a SiOx layer is deposited on the back surface 1a of the silicon substrate 1 as a second passivation layer 5, and then a phosphorus-doped polysilicon Poly-Si (n +) layer is deposited on the second passivation layer 5 as an electron collecting layer 6, wherein the second passivation layer 5 contacts the silicon substrate 1 through the first opening 4.
In the embodiment of the present invention, step 205 may refer to the related description of step 105, and is not repeated herein to avoid repetition.
Fig. 7 is a fifth process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 7, a laser ablation is used to remove a portion of the electron collecting layer 6 to form a second opening 7, and the second opening 7 is spaced apart from the first opening 4.
Step 206, forming a third opening 8 at the position of the second opening 7 on the second passivation layer 5, the dielectric insulating layer 3 and the first passivation layer 2 by wet etching, wherein an etching rate of an etchant used in the wet etching on the second passivation layer 5, the dielectric insulating layer 3 and the first passivation layer 2 is greater than an etching rate of the etchant used in the wet etching on the electron collecting layer 6.
In the embodiment of the invention, the cavity collecting layer 10 in the subsequent process has high requirements on the surface of the crystalline silicon, and the process temperature of laser ablation is high, so that the surface of the crystalline silicon can be damaged, therefore, the third opening can adopt wet etching to meet the preparation requirements of the subsequent cavity collecting layer, but the wet etching process is complicated and high in cost, and other steps can select laser ablation instead of adopting wet etching to simplify the process and improve the precision. The wet etching can adopt acid liquor corrosion, the acid liquor has a corrosion effect, the reaction rate of the first passivation layer 2, the dielectric insulating layer 3 and the second passivation layer 5 is high, and the reaction rate of the electronic collection layer 6 is low, so that the electronic collection layer 6 forming the second opening 7 can be used as a mask to etch the first passivation layer 2, the dielectric insulating layer 3 and the second passivation layer 5, a third opening 8 is formed at the second opening 7, the mask does not need to be placed, removed or replaced, and the like, the preparation cost is reduced, and the alignment precision is improved. Other etching agents with fast reaction rates on the first passivation layer 2, the dielectric insulating layer 3 and the second passivation layer 5 and slow reaction rates on the electron collecting layer 6 may also be selected in the implementation of the present invention, which is not particularly limited in the embodiment of the present invention.
Fig. 8 is a sixth schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 8, wet etching is performed using an acidic solution, etching of the first passivation layer 2, the dielectric insulating layer 3, and the second passivation layer 5 is performed using the electron collecting layer 6 forming the second opening 7 as a mask, a third opening 8 is formed at the position of the second opening 7, and the silicon substrate 7 may be exposed through the third opening 8.
Step 207 of preparing an emitter on said back side 1a, said emitter comprising a third passivation layer 9 and a hole collection layer 10.
In the embodiment of the present invention, step 207 may correspond to the related description of step 107, and is not repeated herein to avoid repetition.
Optionally, the third passivation layer 9 is an a-Si: h (i) layer.
Alternatively, the hole-collecting layer 10 is any of an a-Si: H (p +) layer, an a-SiOx: H (p +) layer, an a-SiCx: H (p +) layer, and an a-SiOxCy: H (p +) layer.
In the embodiment of the present invention, the third passivation layer 9 in the emitter may be an intrinsic hydrogenated amorphous silicon a-Si: H (i) layer, the hole transport layer 10 may be a boron-doped amorphous silicon a-Si: H (p +), an oxygen-doped amorphous silicon a-SiOx: H (p +), a carbon-doped amorphous silicon a-SiCx: H (p +), or an amorphous silicon a-SiOxCy: H (p +), which is doped with oxygen and carbon simultaneously, and this is not limited in the embodiment of the present invention.
In an embodiment of the present invention, the amorphous silicon may include microcrystalline silicon, and the microcrystalline silicon refers to a semiconductor containing a plurality of microcrystalline grains in the amorphous silicon, wherein an average grain size of the microcrystalline grains may be in a range from 1nm to 50nm, for example, an average grain size of the microcrystalline grains may be any value in a range from 1nm to 50nm, such as 1nm, 2nm, 3nm, 4nm, 5nm, 10nm, 15nm, 20nm, 30nm, 40nm, and 50 nm.
Optionally, the thickness of the third passivation layer 9 is less than 50 nm.
Optionally, the thickness of the hole-collecting layer 10 is less than 100 nm.
In the embodiment of the present invention, when the emitter is prepared on the back surface 1a of the silicon substrate 1, the thicknesses of the deposited third passivation layer 9 and the deposited hole collection layer 10 may be selected according to process conditions, application requirements, and the like, optionally, the thickness of the third passivation layer 9 may be any thickness less than 50nm, and the thickness of the hole collection layer 10 may be any thickness less than 100 nm.
Fig. 9 is a seventh schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, as shown in fig. 9, an a-Si: H (i) layer is deposited on the back surface 1a of the silicon substrate 1 as a third passivation layer 9, and an a-Si: H (p +) layer is further deposited on the third passivation layer 9 as a hole collecting layer 10, wherein the third passivation layer 9 is in contact with the silicon substrate 1 through a third opening 8.
In an embodiment of the present invention, a fourth passivation layer 11 may be deposited on the front surface 1b of the silicon substrate 1, and the fourth passivation layer 11 may correspond to the description of the first passivation layer 2 in step 102, and is not repeated herein for avoiding repetition. An anti-reflection layer 12 may be further deposited on the fourth passivation layer 11 to form a composite layer, the anti-reflection layer 12 is used to reduce the reflection loss of the incident light on the front surface 1b, and the anti-reflection layer 12 may be selected from silicon nitride, silicon oxide, or the like, and in the implementation of the present invention, the anti-reflection layer may be prepared by a chemical vapor deposition method, or may be prepared by other processes.
In the embodiment of the present invention, the fourth passivation layer 11 and the anti-reflection layer 12 are functionally described, in the preparation process, the fourth passivation layer 11 and the anti-reflection layer 12 may be formed by the same film layer and simultaneously achieve a passivation function and an anti-reflection function, or by different film layers and respectively achieve a passivation function, and in the case that the fourth passivation layer 11 and the anti-reflection layer 12 are different film layers, a front field may be added between the fourth passivation layer 11 and the anti-reflection layer 12 to enhance a passivation effect on the battery, or the front field may not be added to avoid parasitic absorption caused by the front field, so as to reduce a short-circuit current of the battery.
Optionally, the thickness of the fourth passivation layer 11 is less than 20 nm.
Optionally, the thickness of the anti-reflection layer 12 is less than 100 nm.
In the embodiment of the present invention, the thicknesses of the fourth passivation layer 11 and the anti-reflection layer 12 deposited on the front surface 1b of the silicon substrate 1 may be selected according to process conditions, application requirements, and the like, alternatively, the thickness of the fourth passivation layer 11 may be any thickness smaller than 20nm, and the thickness of the anti-reflection layer 12 may be any thickness smaller than 100 nm.
Fig. 10 is an eighth process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 10, a hydrogenated amorphous silicon layer is deposited on the front surface 1b of the silicon substrate 1 as a fourth passivation layer 11, and an anti-reflection layer 12 is deposited on the fourth passivation layer 11.
Step 209 of forming a fourth opening 13 at the location of said first opening 4 on said third passivation layer 9 and hole collection layer 10 using laser ablation.
In the embodiment of the present invention, step 209 may correspond to the related description of step 108, and is not repeated herein to avoid repetition.
Optionally, a center position of the fourth opening 13 overlaps a center position of the first opening 4, and a width of the fourth opening 13 is smaller than or equal to a width of the first opening 4 and smaller than a width of the third opening 8.
In the embodiment of the present invention, the fourth opening 13 is formed at the position of the first opening 4, the center position of the fourth opening 13 may coincide with the center position of the first opening 4, and the width of the fourth opening 13 is less than or equal to the width of the first opening 4, further, the width of the fourth opening 13 should also be less than the width of the third opening 8, and the specific widths of the first opening 4, the third opening 8 and the fourth opening 13 may be set according to application requirements and process conditions, which is not particularly limited in the embodiment of the present invention.
Fig. 11 is a ninth schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 11, a fourth opening 13 is formed by removing a portion of the third passivation layer 9 and the hole collecting layer 10 at the position of the first opening 4 on the back surface 1a of the silicon substrate 1 by laser ablation, wherein the electron collecting layer 6 is exposed through the fourth opening 13.
In the embodiment of the present invention, the transparent conductive layer 14 is deposited on the back surface 1a, the deposited transparent conductive layer 14 may contact the electron collecting layer 6 through the fourth opening 13, and contact the hole collecting layer 10 through the third opening 8, the transparent conductive layer 14 has low resistivity and good photoelectric characteristics, and can efficiently collect carriers through the electron collecting layer 6 and the hole collecting layer 10, so as to ensure the efficiency of the finished solar cell, wherein the transparent conductive layer 14 may be prepared by a magnetron sputtering method, a reactive plasma deposition method, and the like, and the transparent conductive layer 14 may be an indium tin oxide layer, a zinc oxide layer, and the like.
Fig. 12 is a tenth schematic process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 12, an ito layer is deposited on the back surface 1a of the silicon substrate 1 as a transparent conductive layer 14, wherein the transparent conductive layer 14 is in contact with the electron collecting layer 6 through the fourth opening 13 and in contact with the hole collecting layer 10 through the third opening 8.
Optionally, the thickness of the transparent conductive layer 14 is less than 100 nm.
In the embodiment of the present invention, the thickness of the transparent conductive layer 14 deposited on the back surface 1a of the silicon substrate 1 may be selected according to process conditions, application requirements, and the like, and optionally, the thickness of the transparent conductive layer 14 may be any thickness less than 100 nm.
In the embodiment of the present invention, the position of the fourth opening 13 may be used as an electron collecting region, and the position of the third opening 8 may be used as a hole collecting region, in order to isolate the electron collecting region from the hole collecting region, the transparent conductive layer 14 between the electron collecting region and the hole collecting region may be isolated, and the dielectric insulating layer 3 between the electron collecting region and the hole collecting region is retained, so as to ensure the insulating effect between the electron collecting region and the hole collecting region, wherein a fifth opening 15 may be formed between the fourth opening 13 and the third opening 8 on the front surface 1b by laser ablation, the depth of the fifth opening 15 should completely penetrate through the thickness of the transparent conductive layer 14, and at least part of the thickness of the dielectric insulating layer 3 is retained, so that the transparent conductive layer 14 does not exist between the electron collecting region and the hole collecting region, and the dielectric insulating layer 3 is also retained for isolation.
Fig. 13 is an eleventh process flow diagram of a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 13, a fifth opening 15 is formed between the fourth opening 13 and the third opening 8 on the back surface 1a of the silicon substrate 1 by laser ablation, wherein the fifth opening 15 may penetrate through the transparent conductive layer 14 and leave the dielectric insulating layer 3, and other layers between the transparent conductive layer 14 and the dielectric insulating layer 3 may be removed or remained according to process conditions, application requirements, and the like.
In this embodiment of the present invention, after the patterning of the back surface 1a of the silicon substrate 1 is completed, a metal electrode may be further prepared on the electrode side, where the metal electrode may include a metal electrode 16a for collecting holes and a metal electrode 16b for collecting electrons, and optionally, the metal electrode may be prepared by using a screen printing process, an electroplating process, or the like, and the material of the metal electrode may be a metal such as silver, copper, aluminum, tin, or the like, or an alloy of at least two metals such as silver, copper, aluminum, tin, or the like, which is not particularly limited in this embodiment of the present invention.
Fig. 14 is a twelfth process flow diagram illustrating a method for manufacturing a solar cell according to an embodiment of the present invention, and as shown in fig. 14, a metal electrode is manufactured on the back surface 1a of the silicon substrate 1, wherein the method includes manufacturing a metal electrode 16a for collecting holes on the transparent conductive layer 14 at the position of the third opening 8, and manufacturing a metal electrode 16b for collecting electrons on the transparent conductive layer 14 at the position of the fourth opening 13.
In the implementation of the invention, one side of the silicon substrate, which is provided with the electrodes, is used as a back surface, one side opposite to the back surface is used as a front surface, in a back surface field and emitter patterning process of the back surface, a first passivation layer and a dielectric insulating layer are sequentially deposited on the back surface, and then laser ablation is adopted to form a first opening on the first passivation layer and the dielectric insulating layer to expose the silicon substrate; preparing a back surface field layer on the back surface, wherein the back surface field comprises a second passivation layer and an electron collection layer; forming a second opening on the electron collection layer by laser ablation, wherein the second opening is spaced from the first opening; forming a third opening at the position of the second opening on the second passivation layer, the dielectric insulating layer and the first passivation layer by wet etching, wherein the etching rate of an etchant adopted by the wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer is greater than that of an etchant adopted by the wet etching on the electron collecting layer, so that the electron collecting layer containing the second opening is used as a mask in the process of wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer, and a third opening penetrating through the electron collecting layer, the second passivation layer, the dielectric insulating layer and the first passivation layer is formed at the second opening; and preparing an emitter electrode on the back surface, wherein the emitter electrode comprises a third passivation layer and a hole collecting layer, and laser ablation can be adopted to form a fourth opening on the third passivation layer and the hole collecting layer at the position of the first opening. In the implementation of the invention, the process of patterning the back emitter and the back surface field of the silicon substrate adopts one-time wet etching and multiple times of laser ablation, and the laser ablation process has the advantages of high processing speed, high precision, low cost and little pollution, so the process can be effectively simplified, the cost can be reduced, the patterning precision can be improved, the damage can be reduced by reducing the wet etching with fussy implementation operation, high cost and great pollution, and the finished product quality of the HBC battery can be improved.
The embodiment of the invention also provides a solar cell, which comprises a back surface provided with the electrode and a front surface opposite to the back surface;
the emitter and the back surface field in the back surface are arranged in an interdigital periodic manner, and the back surface field comprises SiOx/Poly-Si (n +) layers.
Alternatively, the solar cell is prepared by using the preparation method of the solar cell described in any one of fig. 1 to 2.
In the implementation of the invention, the second passivation layer in the back surface field can be a silicon oxide SiOx layer, the electron collection layer can be a Poly-Si (n +) layer, so that the back surface field of the electrode side in the solar cell adopts a silicon oxide passivation layer/phosphorus-doped polysilicon SiOx/Poly-Si (n +) layer structure with higher electron collection capability, and the hole collection adopts an intrinsic hydrogenated amorphous silicon passivation layer/boron-doped hydrogenated amorphous silicon a-Si (H) (i)/a-Si: H (p +) layer structure, on the basis, based on the high carrier selectivity and low contact resistance of the back surface field of the SiOx/Poly-Si (n +) structure, the conversion efficiency of the solar cell can be effectively improved.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the embodiments of the application.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of fabricating a solar cell, the method comprising:
providing a silicon substrate, wherein the silicon substrate comprises a back surface provided with an electrode and a front surface opposite to the back surface;
depositing a first passivation layer and a dielectric insulating layer on the back surface in sequence;
forming a first opening on the first passivation layer and the dielectric insulating layer by laser ablation;
preparing a back surface field on the back surface, wherein the back surface field comprises a second passivation layer and an electron collection layer;
forming a second opening in the electron collection layer by laser ablation, the second opening being spaced apart from the first opening;
forming a third opening at the position of the second opening on the second passivation layer, the dielectric insulating layer and the first passivation layer by wet etching, wherein the etching rate of an etchant used by the wet etching on the second passivation layer, the dielectric insulating layer and the first passivation layer is greater than that of the etchant used by the wet etching on the electron collecting layer;
preparing an emitter on the back surface, wherein the emitter comprises a third passivation layer and a hole collecting layer;
forming a fourth opening in the third passivation layer and the hole collection layer at the location of the first opening using laser ablation.
2. The method of claim 1, wherein a center position of the fourth opening overlaps a center position of the first opening;
the width of the fourth opening is smaller than or equal to the width of the first opening and smaller than the width of the third opening.
3. The method of claim 1, wherein the second passivation layer is a SiOx layer;
the electron collecting layer is a Poly-Si (n +) layer.
4. The method of claim 1, wherein the third passivation layer is an a-Si: H (i) layer;
the hole-collecting layer is any one of an a-Si: H (p +) layer, an a-SiOx: H (p +) layer, an a-SiCx: H (p +) layer and an a-SiOxCy: H (p +) layer.
5. The method of claim 1, wherein the laser ablation comprises any one of a nano-pulsed laser, a picosecond pulsed laser;
the laser wavelength of the laser ablation comprises any one of 355 nm, 532 nm and 1064 nm.
6. The method of claim 1, wherein the first passivation layer has a thickness of less than 50 nm; and/or the presence of a gas in the gas,
the thickness of the dielectric insulating layer is less than 500 nm; and/or the presence of a gas in the gas,
the thickness of the second passivation layer is less than 5 nm; and/or the presence of a gas in the gas,
the thickness of the electron collection layer is less than 500 nm; and/or the presence of a gas in the gas,
the thickness of the third passivation layer is less than 50 nm; and/or the presence of a gas in the gas,
the thickness of the hole collecting layer is less than 100 nm.
7. The method of claim 1, wherein after the fabricating an emitter on the backside, the emitter comprising a third passivation layer and a hole collection layer, further comprising:
depositing a fourth passivation layer and an anti-reflection layer on the front surface in sequence;
after forming a fourth opening on the third passivation layer and the hole collection layer at the location of the first opening using laser ablation, further comprising:
depositing a transparent conductive layer on the back surface;
forming a fifth opening between the fourth opening and the third opening of the back surface by using laser ablation, wherein the fifth opening penetrates through the transparent conducting layer and at least partially retains the dielectric insulating layer;
and preparing a metal electrode on the back surface.
8. The method of claim 7, wherein the thickness of the fourth passivation layer is less than 20 nm; and/or the presence of a gas in the gas,
the thickness of the anti-reflection layer is less than 100 nm.
9. A solar cell, comprising a back surface on which electrodes are provided, and a front surface opposite to the back surface;
the emitter and the back surface field in the back surface are arranged in an interdigital periodic manner, and the back surface field comprises SiOx/Poly-Si (n +) layers.
10. The solar cell according to claim 9, wherein the solar cell is prepared by the method according to any one of claims 1 to 8.
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| CN115207137A (en) * | 2022-09-16 | 2022-10-18 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and preparation method thereof |
| CN115312633A (en) * | 2022-10-11 | 2022-11-08 | 金阳(泉州)新能源科技有限公司 | Mask-layer-free combined passivation back contact battery and preparation method thereof |
| WO2023169245A1 (en) * | 2022-03-09 | 2023-09-14 | 西安隆基乐叶光伏科技有限公司 | Method for preparing solar cell, and solar cell |
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|---|---|---|---|---|
| CN108336154A (en) * | 2018-02-02 | 2018-07-27 | 中国科学院微电子研究所 | Crystal silicon solar energy battery and preparation method thereof |
| CN209675296U (en) * | 2019-02-01 | 2019-11-22 | 泰州隆基乐叶光伏科技有限公司 | Back contacts solar cell |
| CN112490324A (en) * | 2020-11-03 | 2021-03-12 | 浙江爱旭太阳能科技有限公司 | Preparation method of N-type monocrystalline silicon HBC solar cell |
| CN114038921B (en) * | 2021-11-05 | 2024-03-29 | 晶科能源(海宁)有限公司 | Solar cell and photovoltaic module |
| CN114823967A (en) * | 2022-03-09 | 2022-07-29 | 西安隆基乐叶光伏科技有限公司 | Preparation method of solar cell and solar cell |
-
2022
- 2022-03-09 CN CN202210235077.1A patent/CN114823967A/en active Pending
-
2023
- 2023-02-28 WO PCT/CN2023/078570 patent/WO2023169245A1/en unknown
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023169245A1 (en) * | 2022-03-09 | 2023-09-14 | 西安隆基乐叶光伏科技有限公司 | Method for preparing solar cell, and solar cell |
| CN115207137A (en) * | 2022-09-16 | 2022-10-18 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and preparation method thereof |
| CN115207137B (en) * | 2022-09-16 | 2023-02-17 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and preparation method thereof |
| WO2024055475A1 (en) * | 2022-09-16 | 2024-03-21 | 金阳(泉州)新能源科技有限公司 | Joint passivation back-contact battery and manufacturing method therefor |
| CN115312633A (en) * | 2022-10-11 | 2022-11-08 | 金阳(泉州)新能源科技有限公司 | Mask-layer-free combined passivation back contact battery and preparation method thereof |
| CN115312633B (en) * | 2022-10-11 | 2023-02-17 | 金阳(泉州)新能源科技有限公司 | Mask-layer-free combined passivation back contact battery and preparation method thereof |
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| Publication number | Publication date |
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| WO2023169245A1 (en) | 2023-09-14 |
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