CN114823389A

CN114823389A - Wafer level system packaging method

Info

Publication number: CN114823389A
Application number: CN202110130752.XA
Authority: CN
Inventors: 黄河; 刘孟彬; 向阳辉
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2021-01-29
Filing date: 2021-01-29
Publication date: 2022-07-29

Abstract

The invention discloses a wafer level system packaging method, which comprises the following steps: providing a device wafer, wherein the device wafer comprises a plurality of first chips, and the first chips are provided with a first interconnection electrode and an external electrode which are exposed out of the upper surface of the device wafer and are spaced; forming an external conductive bump on the external electrode by an electroplating process, and forming an interconnection conductive bump on the first interconnection electrode; providing a plurality of second chips and a plurality of interconnection chips, wherein the lower surfaces of the second chips are provided with exposed second interconnection electrodes; the interconnection chip is formed with an interconnection structure, and the lower surface of the interconnection chip exposes part of the interconnection structure; and bonding the second chip and the interconnection chip on the upper surface of the device wafer, electrically connecting the second interconnection electrode with the interconnection conductive bump, and electrically connecting the interconnection structure of the interconnection chip with the external conductive bump. According to the invention, the electrical property of the chip module is led out from the upper surface of the device wafer through the interconnection chip, so that the damage to the device wafer is reduced, and the packaging compatibility and reliability are improved.

Description

Wafer level system packaging method

Technical Field

The invention relates to the field of semiconductor device manufacturing, in particular to a wafer level system packaging method.

Background

With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), three-dimensional package (3D), and System In Package (SiP).

At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packaging, an advanced packaging method mainly adopts wafer level package in package (WLPSIP) in a three-dimensional stacking mode.

In the wafer level system packaging process, two bare chips need to be bonded together to realize physical connection, and interconnection leads thereof need to be connected to realize electrical connection.

Disclosure of Invention

The invention aims to provide a wafer level system packaging method which can simplify the packaging process.

In order to achieve the above object, the present invention provides a wafer level system packaging method, including:

providing a device wafer, wherein the device wafer is provided with a first chip, and the first chip is provided with a first interconnection electrode and an external electrode which are exposed out of the upper surface of the device wafer and are spaced;

forming an external connection conductive bump on the external connection electrode through an electroplating process, and forming an interconnection conductive bump on the first interconnection electrode;

providing a plurality of second chips and a plurality of interconnection chips, wherein the lower surfaces of the second chips are provided with exposed second interconnection electrodes; an interconnection structure is formed in the interconnection chip, and a part of the interconnection structure is exposed on the lower surface of the interconnection chip;

and bonding the second chip and the interconnection chip on the upper surface of the device wafer, electrically connecting the second interconnection electrode with the interconnection conductive bump, and electrically connecting the interconnection structure of the interconnection chip with the external conductive bump.

The invention has the beneficial effects that:

the external conductive bumps and the interconnection conductive bumps are formed through an electroplating process, then a welding process is carried out to complete wafer-level system integration, the electroplating process can simultaneously form a plurality of external conductive bumps and interconnection conductive bumps on the whole wafer, efficiency can be improved, and the wafer-level system integration is compatible with a front-stage process of a semiconductor, so that the front-stage process can be utilized to complete the wafer-level system integration, the process efficiency of the whole system integration is greatly improved, and the switching between the front-stage process and a packaging process is saved.

Further, by interconnecting the chips, the leading-out terminal (e.g., I/O terminal) of the chip module formed by the first chip and the second chip is led to the side of the device wafer having the first interconnection electrode and the external electrode, and compared with the scheme of leading the leading-out terminal to the side of the device wafer back to the first interconnection electrode and the external electrode, the method of the invention can subsequently process the device wafer without performing (e.g., performing back thinning processing or through silicon via interconnection process), thereby reducing damage to the device wafer and facilitating improvement of packaging reliability.

Further, the second chip and the first chip and the interconnection chip and the first chip are bonded through the dry film, on one hand, the dry film is a photoetching material, a required pattern can be formed through a semiconductor process, the process is simple, the semiconductor process is compatible, and batch production can be realized. And the elastic modulus of the dry film is smaller, so that the dry film can be easily deformed and cannot be damaged when being subjected to thermal stress, and the bonding stress of the second chip/interconnection chip and the first chip is reduced. When the dry film is photoetched, the dry film of the fence structure can be reserved on the periphery of the area where the external conductive lug and the interconnection conductive lug are preformed, so that when the external conductive lug and the interconnection conductive lug are formed, the external conductive lug and the interconnection conductive lug in expected shapes can be formed due to blocking of the dry film, and the external conductive lug and the interconnection conductive lug are prevented from transversely overflowing.

Each second chip and each interconnection chip are individually bonded on the device wafer in a chip-level manner, so that each second chip or each interconnection chip can be precisely bonded to a preset position, and the packaging reliability is improved.

Furthermore, the plurality of second chips and the interconnection conductive bumps and/or the plurality of interconnection chips and the external conductive bumps can be simultaneously subjected to hot-press bonding, so that the manufacturing efficiency is greatly improved compared with the single-point hot-press bonding of each second chip or interconnection chip.

Furthermore, when the photoetching bonding material is formed, the projection of the photoetching bonding material takes the center of the second chip/interconnection chip as the center, the coverage area is larger than 10% of the area of the second chip/interconnection chip, and preferably the whole lower surface (the area where the electrode is removed) of the second chip/interconnection chip is covered, so that when a plastic package layer is formed in a subsequent process, no gap is formed below the second chip/interconnection chip, the bonding strength is improved, and the yield is improved.

Further, the area of the overlapping region of the second interconnection electrode and the interconnection conductive bump in the direction vertical to the surface of the device wafer is larger than half of the area of the second interconnection electrode, so that the bonding strength of the second interconnection electrode and the interconnection conductive bump is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 to 8 are schematic structural diagrams illustrating different steps in a wafer level system packaging method according to embodiment 1 of the present invention.

Fig. 9 is a schematic structural diagram illustrating a step of forming an opening in a wafer level system packaging method according to embodiment 2 of the present invention.

Description of reference numerals:

10-a device wafer; 110 — a first interconnect electrode; 111-external electrodes; 101-a first chip; 12-a dielectric layer; 50-interconnected chips; 501-a welding pad; 502-a plug; 20-a second chip; 21-a second interconnect electrode; 30-interconnecting conductive bumps; 31-external connection conductive bump; 40-a lithographically-bondable material; 41-opening; 60-plastic packaging layer; 61-rewiring layer; 62-solder balls; 70-an insulating layer; 80-capping substrate; 81-a receiving cavity; 82-electrical lead-out structure.

Detailed Description

The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

If the method herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.

Example 1

An embodiment of the present invention provides a wafer level system packaging method, including the following steps:

s01: providing a device wafer, wherein the device wafer comprises a plurality of first chips, and the first chips are provided with first interconnection electrodes and external connection electrodes which are exposed out of the upper surface of the device wafer and are spaced;

s02: forming an external connection conductive bump on the external connection electrode through an electroplating process; forming an interconnection conductive bump on the first interconnection electrode;

s03: providing a plurality of second chips and a plurality of interconnection chips, wherein the lower surfaces of the second chips are provided with exposed second interconnection electrodes; an interconnection structure is formed in the interconnection chip, and a part of the interconnection structure is exposed on the lower surface of the interconnection chip;

s04: and bonding the second chip and the interconnection chip on the upper surface of the device wafer, electrically connecting the second interconnection electrode with the interconnection conductive bump, and electrically connecting the interconnection structure of the interconnection chip with the external conductive bump.

It should be noted that S0N in this specification does not represent the sequence of the manufacturing process.

Fig. 1 to 8 are schematic structural diagrams illustrating different steps of the wafer level system packaging method according to the present embodiment, and please refer to fig. 1 to 8 to describe each step in detail.

Referring to fig. 1, the packaging method of the present embodiment is used to implement wafer level system packaging, and provides a device wafer 10, where the device wafer 10 is used to bond with a chip to be integrated in a subsequent process. In this embodiment, the device wafer 10 is fabricated using integrated circuit fabrication techniques, and the device wafer 10 includes a substrate. As an example, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In this embodiment, the device wafer 10 includes opposing wafer front and back sides, the wafer back side referring to the bottom surface of the substrate in the device wafer 10.

The device wafer 10 has a plurality of first chips 101 formed on an upper surface thereof, and the first chips 101 include a first surface (upper surface) and a second surface (lower surface) opposite to each other, the first surface having exposed and spaced apart first interconnection electrodes 110 and external electrodes 111. And at the edge of the first surface, the first interconnection electrode 110 and the external connection electrode 111 are exposed. The first surface and the front surface of the wafer are the same surface, and the first interconnection electrode 110 and the external electrode 111 are both interconnection lead pads (Pad) of the first chip 101, and are used for electrically connecting the first chip 101 with other chips or circuit structures. In this embodiment, the first interconnection electrode 110 and the external connection electrode 111 are electrically connected to different circuit structures in the first chip 101.

In this embodiment, an interconnection conductive bump is formed on the first interconnection electrode of the first chip 101, an external conductive bump is formed on the external electrode, and the interconnection conductive bump is isolated from the external conductive bump, so as to electrically isolate the interconnection conductive bump from the external conductive bump. Therefore, the minimum pitch between the first interconnection electrode 110 and the external connection electrode 111 is not excessively small. If the minimum distance between the first interconnection electrode 110 and the external connection electrode 111 is too small, the interconnection conductive bump and the external connection conductive bump are easily bridged (bridge) or merged (merge), thereby adversely affecting the reliability of the package. For this reason, in the present embodiment, the minimum pitch of the first interconnection electrode 110 and the external connection electrode 111 is 3 micrometers. It should be noted that, in other embodiments, the first interconnection electrode may also be electrically connected to the external electrode according to the circuit design.

In this embodiment, a second chip is bonded on the first chip 101, and the first interconnection electrode 110 is used to realize an electrical connection with the second chip. The external electrode 111 is used to electrically lead out a chip module formed by the first chip 101 and the corresponding second chip, so as to electrically connect the chip module with other substrates having circuit structures.

In this embodiment, a dielectric layer 12 is formed on the upper surface of the device wafer, the exposed positions of the first interconnection electrode 110 and the external electrode 111 are protected by the dielectric layer 12 to prevent short circuit, and in the manufacturing process of the device wafer 10, the dielectric layer 12 is etched to expose the first interconnection electrode 110 and the external electrode 111, so that the surfaces of the first interconnection electrode 110 and the external electrode 111 are lower than the first surface of the device wafer 10, that is, grooves respectively exposing the first interconnection electrode 110 and the external electrode 111 are formed on the first surface of the device wafer 10. In addition, the dielectric layer 12 has a thickness that provides space for subsequent steps of forming the interconnect conductive bumps and the external conductive bumps.

Referring to fig. 2, a lithographically bondable material 40 is formed on the top surface of the device wafer 10, the lithographically bondable material 40 being used to bond the second chips and the interconnect chips to the top surface of the device wafer 10 in a later process. In this embodiment, the photo-lithographically bondable material 40 includes a dry film or a liquid dry film, but in other embodiments, other photo-sensitive adhesive materials may be selected. The film-shaped dry film is formed by coating a solvent-free photoresist on a polyester film base and then coating a polyethylene film; when in use, the polyethylene film is removed, the solvent-free photoresist is pressed on the base plate, and a pattern can be formed in the dry film through exposure and development treatment. The liquid dry film means that the components in the film-like dry film exist in a liquid state. The dry film is a permanent bonding film and has high bonding strength. The film-like dry film may be formed on the device wafer 10 by means of a film-attaching method, and the liquid dry film is coated on the device wafer 10 by a spin coating process, and then the liquid dry film is cured. The second chip/interconnect chip and the device wafer 10 are bonded by a dry film, which is a photo-lithographically-moldable material, and a desired pattern can be formed by a semiconductor process, which is simple and compatible with the semiconductor process, and can be mass-produced. And the elastic modulus of the dry film is relatively small, so that the dry film can be easily deformed and cannot be damaged when being subjected to thermal stress, and the bonding stress between the second chip/interconnection chip and the device wafer 10 is reduced.

In an alternative embodiment, after the forming the lithographically bondable material, the method further includes: and patterning the photoetching bonding material to form a fence structure at the periphery of the region where the external conductive bump and the interconnection conductive bump are preformed. The inner part enclosed by the fence structure is a region for forming the external connection conductive bump or the interconnection conductive bump, the fence structure is preferably a closed annular structure, and the enclosed space is cylindrical. When the photoetching bonding material is photoetched, the photoetching bonding material with a fence structure is reserved on the periphery of the area where the external connection conductive lug or the interconnection conductive lug is preformed, so that when the external connection conductive lug or the interconnection conductive lug is formed, the external connection conductive lug or the interconnection conductive lug with an expected shape can be formed due to the blocking of the fence, and the external connection conductive lug or the interconnection conductive lug is prevented from transversely overflowing.

In this embodiment, the lithographically bondable material 40 is formed on the surface of the device wafer 10, and in another embodiment, the lithographically bondable material 40 may also be formed on the surface of the second/interconnect die.

In this embodiment, the lithographically-bondable material 40 is formed to a thickness of 5-200 μm, such as 15 μm, 30 μm, 80 μm, 150 μm, and the like. When the second chip is bonded, the projection of the lithographically-enabled bonding material 40 in the surface direction of the device wafer 10 is centered at the center of the second chip 20 and covers at least 10% of the area of the second chip; and/or when the interconnection chip is bonded, the thickness of the formed photoetching bonding material is 5-200 μm, and the projection of the photoetching bonding material in the surface direction of the device wafer is centered at the center of the interconnection chip and covers at least 10% of the area of the interconnection chip. In particular, the thickness of the lithographically bondable material 40 is related to the height of the interconnect conductive bumps/circumscribed conductive bumps formed in later processes. The correlation between the two is described in detail later in the formation of the interconnection conductive bump/external conductive bump. In this embodiment, the lithographically bondable material 40 under the second chip covers at least 10% of the area of the second chip, and the lithographically bondable material 40 under the interconnect chip covers at least 10% of the area of the interconnect chip, with the lithographically bondable material covering a central location of the second chip/interconnect chip. Because the plastic package layer is not easily filled to the middle position of the second chip/the interconnection chip (because the plastic package layer is far away from the edge of the second chip/the interconnection chip) when the plastic package layer is formed in the subsequent process, the photoetching bonding material 40 not only plays a role in adhesion, but also plays a role in sealing in advance, and the photoetching bonding material 40 and the plastic package layer in the subsequent process play a role in sealing the second chip/the interconnection chip together. In an alternative, the photo-lithographically-bondable material 40 covers the entire lower surface (excluding the region where the electrode is located) of the second chip 20/the interconnection chip, so that when a plastic package layer is formed in a subsequent process, no gap is formed below the second chip/the interconnection chip, the bonding strength is improved, and the yield is improved.

With continued reference to fig. 2, an interconnection conductive bump 30 is formed on the first interconnection electrode 110, and an external connection conductive bump 31 is formed on the external connection electrode 111 by an electroplating process. In the present embodiment, the external connection conductive bump 31 and the interconnection conductive bump 30 are formed in the same electroplating process step, i.e., they are formed at the same time, and in another embodiment, the external connection conductive bump 30 and the interconnection conductive bump 31 are formed in different electroplating process steps, i.e., they are formed in steps. When the two are formed step by step, the same process parameters can be adopted, and different process parameters can be adopted. It can be understood that the formation of the interconnection conductive bump 30 and the external conductive bump 31 at the same time is beneficial to simplify the process steps and improve the packaging efficiency.

The material circumscribing the conductive bump 31 or interconnecting the conductive bump 30 includes: any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium. The height of the interconnection conductive bump 30 is formed in relation to the height of the dry film and the structure of the second chip, and when the second interconnection node electrode of the second chip is flush with the lower surface of the second chip, the height of the interconnection conductive bump 30 and the height of the dry film (including the height of the dielectric layer 12 in this embodiment) are substantially equal to each other, so that the second interconnection electrode 21 is in contact with the interconnection conductive bump 30 while the second chip is attached to the dry film. When the second interconnection electrode 21 is recessed downward with respect to the lower surface of the second chip 20, the height of the interconnection conductive bump 30 is equal to the depth of the recess + the dry film thickness + the thickness of the dielectric layer 12. In an alternative embodiment, the height of the interconnecting conductive bumps 30 is 5-200 μm. Such as 10 μm, 50 μm, 100 μm.

The electroplating process includes electroless palladium immersion gold (ENEPIG) or electroless nickel gold (ENIG), wherein the process parameters of ENEPIG or ENIG may be as described in table 1.

TABLE 1

The wafer-level system integration can be completed by utilizing the front-stage process, so that the process efficiency of the whole system integration is greatly improved, and the switching between the front-stage process and the packaging process is saved.

Before chemical plating, in order to better finish an electroplating process, the surfaces of electrodes (a first interconnection electrode, a second interconnection electrode and an external electrode) can be cleaned firstly to remove a natural oxidation layer on the surface of the electrodes and improve the surface wettability (wettabilities) of a welding pad; an activation process may then be performed to promote nucleation growth of the plating metal on the metal to be plated.

In order to better implement electroplating, a relatively perfect external connection conductive bump and interconnection conductive bump are formed, and the arrangement of the first interconnection electrode and the second interconnection electrode also needs to meet certain requirements, such as: the exposed area of the electrode is 5-200 square microns, and in the range, the conductive bump can be in sufficient contact with the electroplating solution, so that the contact between the conductive bump and the electrode is prevented from being influenced due to insufficient contact between the electrode and the electroplating solution, for example, the contact area is too small to influence the resistance, or the conductive bump cannot be contacted to cause poor electric contact; moreover, the electroplating efficiency can be ensured not to be reduced and the excessive surface can not be occupied because the contact area is not too large.

The cross section area of the formed conductive bump is larger than 10 square microns, so that the area occupied by the conductive bump is not too large, and the bonding strength between the conductive bump and the electrode can be ensured.

In the alternative, the material of the conductive bump is the same as the material of the electrode, which makes it easier to form the conductive bump. Of course, the material of the electrode may be different from that of the conductive bump, in order to make it easier to form the conductive bump later, a material layer may be formed on the electrode first, and the material of the material layer may be the same as that of the conductive bump, and the method of forming the material layer may be a deposition process. Referring to fig. 3, a plurality of second chips 20 and interconnection chips 50 are provided, the lower surfaces of the second chips 20 having second interconnection electrodes 21. An interconnection structure 51 is formed in the interconnection chip 50, and a portion of the interconnection structure 51 is exposed at a lower surface of the interconnection chip 50.

The second chip 20 is used as a chip to be integrated in a wafer level package, and the wafer level system packaging method of the embodiment can implement heterogeneous integration. Accordingly, the second chip 20 may be a chip made of a silicon wafer, or a chip made of another material. The second chip 20 is made by using an integrated circuit manufacturing technology, and may be a memory chip, a communication chip, a processor, or a logic chip. The second chip 20 typically includes NMOS devices or PMOS devices or the like formed on a semiconductor substrate. The second interconnection electrode 21 is located on the lower surface of the second chip 20, and is used for electrically connecting the second chip 200 with other devices. Specifically, the second interconnect electrode 21 may be a Pad (Pad). In this embodiment, the material of the second interconnection electrode 21 includes any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium, and preferably, the material combination of the second interconnection electrode 21 and the interconnection conductive bump 30 includes gold-gold, copper-copper, copper-tin, or gold-tin.

The plurality of second chips are same-function chips; the plurality of second chips at least comprise chips with two different functions; the first chip is a passive device or an active device.

The second chip may be a sensor module chip, a MEMS chip, a filter chip, a logic chip, a memory chip, a capacitor, an inductor, etc., and the capacitor may be an MLCC capacitor. The sensor module chip comprises a module chip for sensing at least one of a radio frequency signal, an infrared radiation signal, a visible light signal, a sound wave signal and an electromagnetic wave signal; the filter chip includes: at least one of the surface acoustic wave resonator and the bulk acoustic wave resonator. The second chip can be a packaged chip, and a plastic packaging process is not needed subsequently. The second chip may also be a through-die chip, or a chip with a shielding layer on its top surface.

The interconnection chip 50 is used for electrically leading out the external electrode 111, so that at least one surface of the interconnection chip 50 exposes a part of the interconnection structure 51, thereby enabling the interconnection structure 51 to be electrically connected with the external electrode 111. By interconnecting the chips 51, the terminals (e.g., I/O terminals) of the chip module formed by the first chip 101 and the second chip 20 can be led to the side of the device wafer 10 having the first interconnection electrode 110 and the external electrode 111, and compared with the scheme of leading the terminals to the side of the device wafer 10 facing away from the first interconnection electrode 110 and the external electrode 111, the embodiment can subsequently perform no processing (e.g., back thinning processing or through-silicon-via interconnection) on the device wafer 10, thereby reducing damage to the device wafer 10, facilitating improvement of package reliability, and making the packaging method suitable for system integration of various device wafers 10, and accordingly improving package compatibility.

In this embodiment, the interconnection chip 50 is prepared by a semiconductor process, so as to improve the process compatibility of the preparation process of the interconnection chip 50, facilitate the formation of the interconnection chip 50 by a wafer-level preparation method, and improve the preparation efficiency. Specifically, a semiconductor substrate is provided; forming a plurality of interconnect structures 51 in a semiconductor substrate; after the interconnect structure 51 is formed, the semiconductor substrate is diced to obtain a plurality of discrete interconnect chips 50. The semiconductor substrate may be a silicon substrate.

As an example, the interconnect structure 51 penetrates through the interconnect chip 50, and both ends of the interconnect structure 51 are exposed, wherein one end is used for electrical connection with the external conductive bump 31, and the other end is used for electrical connection with other interconnect structures (e.g., terminals). Specifically, the interconnect die 300 includes third and fourth opposite surfaces, and the interconnect structure 51 includes a plug 501, an interconnect line (not shown) connected to the plug 501, and a pad 502, the pad 502 being a portion of the interconnect die 50 exposed at the third surface. That is, the interconnect structure 51 includes an interconnect line and a pad 502 on the third surface, and a plug 501 embedded in the interconnect chip 50 from the fourth surface, the plug 501 being connected to the interconnect line. Wherein the third surface exposes a portion of the interconnect line, and a portion of the interconnect line exposed by the third surface serves as the pad 502.

The interconnect lines can function as redistribution layers (RDLs). For example, when the first chip 101 has a plurality of external connection electrodes 111, the plurality of external connection electrodes 111 can be connected by interconnection lines, and the plurality of external connection electrodes 111 can be electrically led out by one plug 501. Plug 501 is used to make electrical connection with a subsequently formed outlet. Moreover, the plug 501 has a certain height, which is beneficial to reducing the difficulty of forming a subsequent outlet.

In this embodiment, the interconnect is made of aluminum. The aluminum process is simple, and the process cost is low, so that the aluminum interconnection layer is selected, and the process difficulty and the process cost of the packaging process are favorably reduced. In other embodiments, the interconnect lines may also be other applicable conductive materials. In this embodiment, the plug 501 is made of copper. The resistivity of copper is low, and the conductive performance of the plug 501 is improved by selecting a copper material; moreover, the plug 501 is formed in the interconnection hole, and the filling property of copper is better, so that the forming quality of the plug 501 in the interconnection hole is improved. In other embodiments, the plug may also be other applicable conductive materials.

In other embodiments, the interconnect structure may also include only plugs extending through the interconnect die, the plugs being correspondingly exposed portions of the third surface of the interconnect die. In other embodiments, the interconnect structure includes interconnect lines and pads, the pads being portions of the third surface of the interconnect die that are exposed.

In this embodiment, after the interconnect line is formed, the plug 501 is formed. Specifically, forming an interconnection line on the third surface; etching the interconnection chip 50 from the fourth surface with the surface of the interconnection line facing the fourth surface as an etching stop position to form an interconnection hole; the interconnect hole is filled to form plug 501. By forming the interconnect line first, it is easy to control the position of the etching stop during the formation of the interconnect hole. In other embodiments, the interconnect lines may also be formed after the plugs are formed.

In the present embodiment, the thickness of the interconnect chip 50 is greater than or equal to the thickness of the second chip 20. Subsequently, both the second chip 20 and the interconnect chip 50 are bonded to the first surface (upper surface) of the first chip 101, and an encapsulation layer covering the second chip 20 and the interconnect chip 50 is further formed on the device wafer 10, a fourth surface of the interconnect chip 50 is exposed from a surface of the encapsulation layer facing away from the device wafer 10, so that the second chip 20 is buried while the fourth surface is exposed by the encapsulation layer by making the thickness of the interconnect chip 50 greater than or equal to the thickness of the second chip 20. However, if the difference between the thicknesses of the interconnection chip 50 and the second chip 20 is too large, the thickness of the package structure formed subsequently is too large, which is not favorable for the development of miniaturization of the device. For this reason, in the present embodiment, the difference in thickness between the interconnect chip 50 and the second chip 20 is 0 to 100 micrometers.

Referring to fig. 4, the second chip 20 and the interconnection chip 50 are bonded on the upper surface of the device wafer 10, and the second interconnection electrode 21 is electrically connected to the interconnection conductive bump 30, and the interconnection structure 51 of the interconnection chip 50 is electrically connected to the external conductive bump 31.

In this embodiment, each of the second chips 20 or the interconnect chips 50 is bonded to the device wafer 10 one by one in a chip-level manner. In another embodiment, a plurality of second chips 20 and interconnect chips 50 may be simultaneously bonded on the device wafer 10. The surface of the second chip 20 having the second interconnection electrode 21 is a front surface (the surface of the interconnection chip 50 exposing the interconnection structure 51 is a front surface), the surface opposite to the front surface is a back surface, and before the second chip 20 and the interconnection chip 50 are bonded to the device wafer 10, the back surfaces of the second chip 20 and the interconnection chip 50 are temporarily bonded to a substrate; the second chips 20 and the interconnect chips 50 are bonded on the device wafer 10 through the substrate, and then the substrate is debonded. The substrate may be a carrier wafer, and is used for temporarily fixing the plurality of second chips 20 and the interconnection chips 50, and the substrate is further used for supporting the second chips 20 and the interconnection chips 20 during the bonding process of the second chips 20 and the interconnection chips 50 with the device wafer 10, so as to improve the reliability of the bonding. The second chip 20 and the interconnect chip 50 are temporarily bonded to the substrate by an adhesive layer or electrostatic bonding. Electrostatic bonding technology is a method of achieving bonding without any adhesive. In the bonding process, the second chip/interconnection chip to be bonded and the substrate are respectively connected with different electrodes, electric charges are formed on the surfaces of the second chip/interconnection chip and the substrate under the action of voltage, and the electric charges on the surfaces of the second chip/interconnection chip and the substrate are different, so that a larger electrostatic attraction is generated in the bonding process of the second chip/interconnection chip and the substrate, and the physical connection of the second chip/interconnection chip and the substrate is realized. Accordingly, during the debonding process, the substrate may be separated from the second chip/interconnect chip by chemical or mechanical peeling.

In this embodiment, the second interconnection electrode 21 and the interconnection conductive bump 30 are made of metal, and the second interconnection electrode 21 and the interconnection conductive bump 30 are electrically connected by a thermocompression bonding process; and/or the interconnection structure 51 and the external conductive bump 31 are made of metal, and the interconnection structure is electrically connected with the external conductive bump 31 through a hot-press bonding process. The second chips 20/the interconnection chips 50 are pre-aligned by first bonding the second chips 20/the interconnection chips 50 to the device wafer 10, so that the second chips 20 and the interconnection conductive bumps 30 and/or the interconnection chips 50 and the external conductive bumps 31 can be thermally and simultaneously bonded, thereby greatly improving the manufacturing efficiency compared with the single-point thermal bonding of each second chip 20 or interconnection chip 50. By bonding both the second chip 20 and the interconnect chip 50 to the first chip 101, system integration of the second chip 20 and the interconnect chip 50 with the device wafer 10 is achieved.

In this embodiment, the area of the interconnect structure 51 or the second interconnect electrode 21 is 5 to 200 μm; the area of the overlapping region of the second interconnection electrode 21 and the interconnection conductive bump 30 in the direction perpendicular to the surface of the device wafer 10 is greater than half of the cross-sectional area of the second interconnection electrode 21, so as to improve the bonding strength of the two, and similarly, the area of the overlapping region of the interconnection structure 51 and the external conductive bump 31 in the direction perpendicular to the surface of the device wafer 10 is greater than half of the cross-sectional area of the interconnection structure 51. In an alternative, the interconnecting conductive bump 30 and the second interconnecting electrode 21 are opposite to each other, i.e., in a direction perpendicular to the surface of the device wafer 10, and/or the circumscribing conductive bump 31 and the interconnecting structure 51 are opposite to each other, i.e., in a direction perpendicular to the surface of the device wafer 10, and are overlapped with each other to the greatest extent. In the alternative, the cross-sectional area of the interconnecting conductive bump 30 and/or the circumscribing conductive bump 31 is greater than 10 square microns to ensure structural strength.

Referring to fig. 5 and 6, in this embodiment, after the second chip 20 and the interconnect chip 50 are bonded, the packaging method further includes: forming a molding compound layer 60 to cover the upper surface of the device wafer 10 and to wrap the second chip 20 and the interconnection chip 50, wherein the molding compound layer 60 exposes the upper surface of the interconnection chip 50 and the interconnection structure 51; and forming a leading-out terminal electrically connected with the interconnection structure 51 on the top surface of the plastic package layer 60.

The encapsulation layer 60 covers the upper surface of the device wafer 10 and wraps the second chip 20 and the interconnection chip 50, that is, the encapsulation layer 60 fills the gap between the chips, and the encapsulation layer seals the second chip 20 and the interconnection chip 50, so that air and moisture are better isolated, and the encapsulation effect is further improved. The molding compound layer 60 is an insulating material, in this embodiment, the material of the molding compound layer 60 includes one or two of a dielectric material and a molding compound material, and the dielectric material may be silicon oxide, silicon nitride, or other dielectric materials. Specifically, the material of the molding layer 60 may be epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, low cost and the like, and is widely used as a packaging material for electronic devices and integrated circuits. As an example, the molding layer 60 may be formed using an injection molding (injection molding) process. The filling performance of the injection molding process is good, and the injection molding agent can be filled between the chips well, so that the second chip 20 and the interconnection chip 50 have good packaging effect. In other embodiments, other processes may be used to form the encapsulation layer 60.

In this embodiment, after the molding layer 60 is formed, the package layer 60 is planarized until the interconnect structures 51 on the top surface of the interconnect chip are exposed. The molding layer 60 is a flat surface to facilitate the formation of the subsequent terminals. In other embodiments, after forming the molding compound layer 60, the molding compound layer 60 above the interconnect die 50 may be etched to expose the interconnect structure 51 of the interconnect die 50.

The second chip 20 and the corresponding first chip 101 constitute a chip module, and the terminals are used as input/output terminals of the chip module, and the chip module can be subsequently bonded to other substrates (e.g., circuit boards) through the terminals.

In this embodiment, the process of forming the terminal includes a bump process, and compared with a wire bonding (wire) process, the wafer level package can be realized in this embodiment. Specifically, the lead-out terminal includes a rewiring layer 61 connected to the interconnect structure 51 and a solder ball 62 on the rewiring layer 61. Specifically, the step of forming the terminal includes: a rewiring layer 61 connected to the top end (i.e., the end exposed by the fourth surface) of the interconnect structure 51 is formed on the top surface of the molding layer 60. The redistribution layer 61 is used to redistribute the top of the interconnect structure 51. In this embodiment, the material of the redistribution layer 61 is aluminum. In other embodiments, the redistribution layer may also be other applicable conductive materials. As an example, the rewiring layer 61 may be formed by deposition and etching of a corresponding material. The second chip 20 is covered by the molding compound layer 60, so that the redistribution layer 61 is isolated from the second chip 20, and correspondingly, the redistribution layer 61 can extend to the molding compound layer 60 above the second chip 20, so that the interconnection structure 51 is redistributed according to actual packaging requirements. An insulating layer 70 is formed to cover the rewiring layer 61, and an opening of the rewiring layer 61 is formed in the insulating layer 70 to expose a portion. The openings are used to provide a spatial location for the formation of solder balls 62. The insulating layer 70 is used for insulating between the heavy wiring layers 61 and also for providing a process platform for the formation of solder balls, and in addition, the insulating layer 70 can also play roles of waterproofing, oxidation resistance, pollution prevention and the like. In this embodiment, the material of the insulating layer 70 is a photosensitive material. Accordingly, the insulating layer 70 may be patterned by a photolithography process, which is advantageous to simplify the process steps and reduce the process cost. Specifically, the material of the insulating layer 70 may be photosensitive Polyimide (PI), photosensitive benzocyclobutene (BCB), or photosensitive Polybenzoxazole (PBO). In this embodiment, an insulating layer 70 covering the redistribution layer 61 is formed on the molding layer 60 by coating. Accordingly, the insulating layer 70 is patterned using a photolithography process to expose a portion of the redistribution layer 61.

Referring to fig. 6, solder balls 62 are formed in the openings, and the solder balls 62 and the rewiring layer 61 constitute terminals. In the present embodiment, the solder balls 62 are formed by a Bumping process. The bump process is favorable for reducing the thickness of the conductive bumps 62, thereby reducing the thickness of the package structure. In this embodiment, the solder balls 62 are made of copper. It should be noted that, in other embodiments, the ball-planting process may also be used to form the terminals.

It should be further noted that, in other embodiments, when the interconnect structure only includes the interconnect line and the pad, after the molding compound layer is formed and the interconnect chip is exposed, and before the lead is formed, the wafer level system packaging method further includes: and forming a plug embedded in the interconnection chip from the upper surface of the interconnection chip, wherein the plug is connected with the interconnection line.

Referring to fig. 7 and 8, in one embodiment, after bonding the second chip and the interconnect chip on the device wafer (after fig. 4), the method further comprises: providing a cover substrate 80, wherein the first surface of the cover substrate 80 includes a receiving cavity 81, bonding the first surface of the cover substrate 80 and the device wafer 10, and making the receiving cavity 81 cover at least a portion of the second chip 20. The material of the capping substrate 80 may be: the material may be a semiconductor material such as silicon, germanium, silicon carbide, gallium arsenide, or indium gallium, or may be a dielectric material. The cover substrate 80 has a receiving cavity 81 formed therein, the receiving cavity 81 may be relatively large, one receiving cavity 81 may simultaneously receive a plurality of second chips 20, and the cover substrate 80 may also include a plurality of sub-receiving cavities, each sub-receiving cavity receiving one or more second chips 20. In an alternative embodiment, the receiving cavity 81 may cover only a portion of one second chip 20, such as only a main portion of the second chip 20. For example, for a bulk acoustic wave resonator or a surface acoustic wave resonator or an infrared thermopile sensor, the chip needs to be formed with a cavity structure, and the cavity structure corresponds to a functional region of the chip structure, and the entire chip is not included in the cavity. For example, for a bulk acoustic wave resonator (BAW), a surface acoustic wave resonator (SAW) and a firmly-arranged bulk acoustic wave resonator (SMR), an upper cavity is arranged above a main body resonance area, the cavity in the present embodiment can be used as the upper cavity, for an infrared thermopile sensor, a heat insulation cavity for heat insulation is arranged below a functional area of the infrared thermopile sensor, the cavity formed in the present embodiment can be used as the heat insulation cavity, for an ultrasonic sensor, a film-shaped vibration portion is arranged in a suspended manner, the upper surface is used for receiving ultrasonic waves, and the lower surface covers the cavity, and the cavity in the present embodiment can be used as a lower cavity of the ultrasonic sensor.

In an alternative embodiment, after the cover substrate 80 is bonded to the device wafer 10, the formed cavity is a sealed cavity, which can prevent the device in the cavity from being contaminated by the external environment (moisture, dust, grease, etc.). In one embodiment, the upper surface of the interconnect die exposes a portion of the interconnect structure, the method further comprising: and forming an electrical lead-out structure 82 penetrating through the cover substrate 80, wherein one end of the electrical lead-out structure 82 is connected to the interconnection structure exposed from the upper surface of the interconnection chip, and the other end of the electrical lead-out structure is located on the upper surface of the cover substrate 80.

Example 2

Referring to fig. 9, the present embodiment is different from embodiment 1 in that a cavity is required below the second chip 20, and after the lithographically printable bonding material 40 is formed, the method further includes: the lithographically bondable material 40 is patterned to form openings 41 in the lithographically bondable material 40, the openings 41 having a depth equal to or less than the thickness of the lithographically bondable material 40. The area where the opening 41 is formed corresponds to the working area of the second chip 20, and after the second chip is bonded by the post-process, a cavity is formed, and the cavity is used as a working cavity (e.g., a thermal insulation cavity) of the second chip. By forming the opening in the lithographically bonding layer, process steps may be saved when a cavity needs to be formed underneath the second chip 20 (which would otherwise need to be formed when manufacturing the second chip). In this embodiment, the opening 41 is used for thermal insulation, and therefore, the depth of the opening 41 is not limited, and the opening 41 may penetrate through the lithographically-printable bonding material 40 (the opening depth is the same as the thickness of the lithographically-printable bonding material 40) or may penetrate through only a part of the thickness of the lithographically-printable bonding material 40 (the opening depth is smaller than the thickness of the lithographically-printable bonding material 40). In other embodiments, if the depth of the opening needs to be defined, a suitable thickness is formed when forming the lithographically-bondable material. For the cavity type bulk acoustic resonator (fbar) and the surface acoustic resonator (SAW), a lower cavity is arranged below the main body resonance area, a sealing cover is formed above the main body resonance area, and an upper cavity is formed between the sealing cover and the main body resonance area. For firmly installed bulk acoustic wave resonators (SMRs), an upper cavity is also formed between the covers above the bulk acoustic wave resonators, and the cavity in this embodiment may be used as the upper cavity. For the infrared thermopile sensor, a heat insulation cavity for heat insulation is arranged below the functional region of the infrared thermopile sensor, and the cavity formed in the embodiment can be used as the heat insulation cavity. For the ultrasonic sensor, the membrane-shaped vibrating part is arranged in a suspended manner, the upper surface is used for receiving ultrasonic waves, the lower surface covers the cavity, and the cavity of the embodiment can be used as the lower cavity of the ultrasonic sensor.

The invention forms the external conductive lug and the interconnection conductive lug through the electroplating process, and then carries out the welding process to finish the wafer-level system integration, the electroplating process can simultaneously form a plurality of external conductive lugs and interconnection conductive lugs on the whole wafer, the efficiency can be improved, and the invention is compatible with the front-stage process of the semiconductor, thereby the front-stage process can be utilized to finish the wafer-level system integration, the process efficiency of the whole system integration is greatly improved, and the switching between the front-stage process and the packaging process is saved.

Further, the second chip and the first chip and the interconnection chip and the first chip are bonded through the dry film, on one hand, the dry film is a photoetching material, a required pattern can be formed through a semiconductor process, the process is simple, the semiconductor process is compatible, and batch production can be realized. And the elastic modulus of the dry film is smaller, so that the dry film can be easily deformed and cannot be damaged when being subjected to thermal stress, and the bonding stress of the second chip/interconnection chip and the first chip is reduced. When the dry film is photoetched, the dry film of the fence structure can be reserved on the periphery of the area where the external conductive lug and the interconnection conductive lug are preformed, so that when the external conductive lug and the interconnection conductive lug are formed, the external conductive lug and the interconnection conductive lug in expected shapes can be formed due to blocking of the dry film, and the external conductive lug and the interconnection conductive lug are prevented from transversely overflowing. Each second chip and each interconnection chip are individually bonded on the device wafer in a chip-level manner, so that each second chip or each interconnection chip can be precisely bonded to a preset position, and the packaging reliability is improved.

Furthermore, when the adhesive layer is formed, the projection of the adhesive layer is centered on the center of the second chip/interconnection chip, the coverage area is larger than 10% of the area of the second chip/interconnection chip, and preferably covers the whole lower surface (the area where the electrode is removed) of the second chip/interconnection chip, so that when the plastic package layer is formed in the subsequent process, no gap is formed below the second chip/interconnection chip, the bonding strength is improved, and the yield is improved.

It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.

The above description is only for the purpose of describing the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are intended to fall within the scope of the appended claims.

Claims

1. A wafer level system packaging method, comprising:

providing a device wafer, wherein the device wafer comprises a plurality of first chips, and the first chips are provided with first interconnection electrodes and external connection electrodes which are exposed out of the upper surface of the device wafer and are spaced;

2. The wafer-level system packaging method of claim 1, wherein the electroplating process comprises: chemical plating palladium and gold leaching, wherein the chemical nickel time is 30-50 minutes, the chemical gold time is 4-40 minutes, and the chemical palladium time is 7-32 minutes; or the like, or, alternatively,

the electroplating process comprises chemical nickel and gold, wherein the chemical nickel time is 30-50 minutes, and the chemical gold time is 4-40 minutes.

3. The wafer-level system packaging method as claimed in claim 1, wherein the external conductive bumps and the interconnection conductive bumps are formed in the same electroplating process step; or the circumscribed conductive bump and the interconnecting conductive bump are formed in different electroplating process steps.

4. The wafer level system packaging method as claimed in claim 1, wherein the interconnect structure includes a plug, the plug being a portion of the lower surface of the interconnect die exposed;

alternatively, the first and second electrodes may be,

the interconnection structure includes a plug, an interconnection line connected to the plug, and a pad, which is a portion of the lower surface of the interconnection chip exposed.

5. The wafer-level system packaging method as claimed in claim 1, wherein the interconnection structure comprises an interconnection line and a pad, the pad being a portion of the lower surface of the interconnection chip exposed;

after bonding the interconnect die to the upper surface of the first die, the method further comprises: forming a plug from an upper surface side of the interconnection chip, the plug being connected to the interconnection line.

6. The wafer-level system packaging method of claim 1, wherein each of the second chips and each of the interconnect chips are individually bonded on the wafer in a chip-level manner;

alternatively, the first and second electrodes may be,

temporarily bonding the second chip and the interconnect chip to a substrate before bonding the second chip and the interconnect chip to the device wafer;

removing the substrate after bonding the second chip and the interconnect chip to the device wafer.

7. The wafer-level system packaging method of claim 1, wherein the method of bonding the second chip on the device wafer comprises:

forming a photoetching bonding material on the lower surface of the second chip or the upper surface of the device wafer, wherein the photoetching bonding material avoids the areas where the first interconnection electrode and the second interconnection electrode are located, and bonding the second chip on the device wafer through the photoetching bonding material; and/or, the method for bonding the interconnection chip on the device wafer comprises the following steps:

and forming a photoetching bonding material on the lower surface of the interconnection chip or the upper surface of the device wafer, wherein the photoetching bonding material avoids the external electrode and the area where the interconnection structure is located, and the interconnection chip is bonded on the device wafer through the photoetching bonding material.

8. The wafer level system packaging method of claim 7, wherein the lithographically bondable material comprises: film-like dry film or liquid dry film.

9. The wafer level system packaging method as claimed in claim 7, wherein the thickness of the photo-etching-able bonding material formed when bonding the second chip is 5-200 μm, and the projection of the photo-etching-able bonding material in the surface direction of the device wafer is centered at the center of the second chip and covers at least 10% of the area of the second chip; and/or when the interconnection chip is bonded, the thickness of the formed photoetching bonding material is 5-200 μm, and the projection of the photoetching bonding material in the surface direction of the device wafer is centered at the center of the interconnection chip and covers at least 10% of the area of the interconnection chip.

10. The wafer-level system packaging method of claim 7, wherein after forming the lithographically bondable material, the method further comprises:

and patterning the photoetching bonding material to form a fence structure at the periphery of the region where the external connection conductive bump and the interconnection conductive bump are preformed.

11. The wafer level system packaging method as claimed in claim 1, wherein the second interconnection electrode and the interconnection conductive bump are made of metal, and are electrically connected through a thermocompression bonding process; and/or the interconnection structure and the external conductive bump are made of metal and are electrically connected through a hot-pressing bonding process.

12. The wafer-level system packaging method according to claim 11, wherein a plurality of thermocompression bonding points or a single thermocompression bonding point by point are simultaneously performed between the second interconnection electrode and the interconnection conductive bump or between the interconnection structure and the external conductive bump.

13. The wafer-level system packaging method as claimed in claim 1, wherein the area of the overlapping region of the second interconnection electrode and the interconnection conductive bump in the direction perpendicular to the surface of the device wafer is greater than half of the cross-sectional area of the second interconnection electrode; and/or the area of the overlapped region of the interconnection structure and the external conductive bump in the direction vertical to the surface of the device wafer is larger than half of the cross-sectional area of the interconnection structure.

14. The wafer level system packaging method of claim 1, wherein bonding the second chip and the interconnect chip further comprises: forming a plastic packaging layer, covering the upper surface of the device wafer, and wrapping the second chip and the interconnection chip, wherein the plastic packaging layer exposes the interconnection structure on the upper surface of the interconnection chip;

and forming a leading-out terminal electrically connected with the interconnection structure on the top surface of the plastic packaging layer.

15. The wafer level system in package method of claim 14, wherein forming the pigtail comprises: and forming a rewiring layer on the top surface of the plastic packaging layer, wherein the rewiring layer is electrically connected with the interconnection structure, an insulating layer is formed on the rewiring layer and the plastic packaging layer, and a solder ball which is electrically connected with the rewiring layer and protrudes out of the surface of the insulating layer is formed.

16. The wafer level system packaging method of claim 1, wherein the step of providing a plurality of interconnected chips comprises: providing a semiconductor substrate;

forming a plurality of the interconnect structures in the semiconductor substrate;

and after the interconnection structure is formed, cutting the semiconductor substrate to obtain a plurality of discrete interconnection chips.

17. The wafer level system packaging method of claim 1, wherein the area of the interconnection structure exposed by the first interconnection electrode or the second interconnection electrode or the external electrode or the interconnection chip is 5-200 square micrometers.

18. The wafer-level system packaging method of claim 1, wherein the cross-sectional area of the interconnecting conductive bumps or the external conductive bumps is greater than 10 square microns.

19. The wafer-level system packaging method of claim 1, wherein after bonding the second chip and the interconnect chip on the device wafer, the method further comprises: and providing a cover substrate, wherein the first surface of the cover substrate comprises a containing cavity, and bonding the first surface of the cover substrate and the device wafer to enable the containing cavity to cover at least one part of the second chip.

20. The wafer level system in package method of claim 19, wherein the top surface of the interconnect die exposes a portion of the interconnect structure, the method further comprising: and forming an electrical lead-out structure penetrating through the cover substrate, wherein one end of the electrical lead-out structure is connected to the interconnection structure exposed from the upper surface of the interconnection chip, and the other end of the electrical lead-out structure is positioned on the upper surface of the cover substrate.