CN113539857A

CN113539857A - System-level packaging method and packaging structure

Info

Publication number: CN113539857A
Application number: CN202110808971.9A
Authority: CN
Inventors: 蔺光磊
Original assignee: Xinzhiwei Shanghai Electronic Technology Co ltd
Current assignee: Xinzhiwei Shanghai Electronic Technology Co ltd
Priority date: 2021-07-16
Filing date: 2021-07-16
Publication date: 2021-10-22

Abstract

The invention provides a system-level packaging method and a packaging structure, comprising the following steps: providing a PCB board, wherein the PCB board is provided with a front surface and a back surface which are opposite, the front surface is provided with a plurality of exposed first welding pads, the back surface is provided with a plurality of exposed third welding pads, a first cavity is formed on the front surface, and at least part of the first welding pads are positioned below the first cavity; providing a first chip, wherein the surface of the first chip is provided with a plurality of exposed second welding pads and is bonded to the bottom of the first cavity through a connecting layer, and the first welding pads are opposite to the second welding pads to form a gap; providing a second chip, wherein the surface of the second chip is provided with a plurality of exposed fourth welding pads and is bonded to the back surface of the PCB through a connecting layer, and the third welding pads are opposite to the fourth welding pads to form a gap; and forming a conductive bump in the gap by electroplating process to electrically connect the first and second bonding pads and the third and fourth bonding pads, respectively. The front surface and the back surface of the PCB are both bonded with the chips, and the traditional step of bonding the chips on the wafer is omitted, so that the process is simplified, the process difficulty is reduced, and the integration level is improved.

Description

System-level packaging method and packaging structure

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a system-level packaging method and a system-level packaging structure.

Background

The system-in-package is formed by integrally assembling a plurality of active elements/devices, passive elements/devices, MEMS devices, discrete kgd (known Good die) such as optoelectronic chips, biochips, etc., which have different functions and are prepared by different processes, into a single standard package having a multi-layered device structure in three dimensions (X-direction, Y-direction, and Z-direction) in any combination, and can provide multiple functions, forming one system or subsystem.

Flip-Chip (FC) bonding is a common system-level packaging method. The system-in-package method comprises the following steps: providing a PCB (printed circuit board), wherein solder balls (formed by a ball-planting process) arranged according to a certain requirement are formed on the PCB; dipping the circuit board with the soldering flux, and then inversely mounting the chip on the circuit board; soldering pads (pad) on the chip and solder balls on the circuit board by using a reflow soldering process and then electrically connecting the pads and the solder balls; filling glue between the bottom of the chip and the circuit board to increase the mechanical strength of the whole structure; however, the conventional system-in-package method has the following disadvantages: 1. the process is complex, so that the packaging efficiency is low; 2. all chips need to be welded on the solder balls in sequence, and the packaging efficiency is low; 3. the packaging height is higher, and the integration level is low.

Therefore, a new system-in-package method and a new package structure are desired, which can solve the technical problems of high difficulty in process control, large package size, low integration level, poor package effect, and the like.

Disclosure of Invention

The invention aims to provide a system-level packaging method and a system-level packaging structure, which can solve the technical problems of high difficulty of process control, large packaging size, low integration level, poor packaging effect and the like.

In order to achieve the above object, the present invention provides a system in package method, comprising: providing a PCB, wherein the PCB comprises a front surface and a back surface which are opposite, the surface of the front surface of the PCB is provided with a plurality of exposed first welding pads, the surface of the back surface of the PCB is provided with a plurality of exposed third welding pads, a first cavity is formed on the surface of the front surface of the PCB, and at least part of the first welding pads are positioned below the first cavity;

providing a first chip, wherein the surface of the first chip is provided with a plurality of exposed second welding pads;

bonding the first chip to the bottom of the first cavity through a connecting layer, wherein the first welding pad is opposite to the second welding pad so as to form a gap;

providing a second chip, wherein the surface of the second chip is provided with a plurality of exposed fourth welding pads, the second chip is bonded to the back surface of the PCB through a connecting layer, and the third welding pads are opposite to the fourth welding pads to form gaps;

and forming a conductive bump in the gap by an electroplating process, wherein the first welding pad and the second welding pad are electrically connected, and the third welding pad and the fourth welding pad are electrically connected through the conductive bump.

The present invention also provides a system-in-package structure, comprising: the PCB comprises a front surface and a back surface which are opposite, the front surface of the PCB is provided with a plurality of exposed first welding pads and a first cavity, and at least part of the first welding pads are positioned below the first cavity; the back surface of the PCB is provided with a plurality of exposed third welding pads;

the surface of the first chip is provided with a plurality of exposed second welding pads, the first chip is bonded at the bottom of the first cavity through a connecting layer, and the first welding pads and the second welding pads are oppositely arranged;

the surface of the second chip is provided with a plurality of exposed fourth welding pads, the second chip is bonded on the back surface of the PCB through a connecting layer, and the third welding pads and the fourth welding pads are oppositely arranged;

and the conductive bumps are formed between the first welding pad and the second welding pad and between the third welding pad and the fourth welding pad through an electroplating process so as to electrically connect the first welding pad and the second welding pad and the third welding pad and the fourth welding pad.

The invention has the beneficial effects that:

according to the invention, the first cavity is formed on the front surface of the PCB, and the first chip is bonded at the bottom of the first cavity through the connecting layer by a bonding process, so that the first chip is connected with the front surface of the PCB; providing a second chip, and bonding the second chip on the back of the PCB through a connecting layer by a bonding process, so that the integration height of the device is reduced, the space utilization rate is improved, and the integration level of the device is improved; in addition, the traditional packaging process for realizing the electrical connection between the chip and the PCB by welding is completely avoided, the conductive bumps are formed by the electroplating process so as to realize the electrical connection between the first chip and the second chip and the PCB, and firstly, the process flow is simplified, and the packaging efficiency is improved; and secondly, the conductive bump is formed between the chip and the PCB through an electroplating process, so that the traditional step of bonding the chip on the wafer is omitted, the process is simplified, the process difficulty is reduced, the integration level is improved, and the conductivity of the packaging structure is improved.

Furthermore, after all the chips are bonded on the PCB, the electric connection between each chip and the PCB is formed through an electroplating process, and compared with the traditional method that each chip is independently welded and electrically connected with the PCB, the packaging efficiency is greatly improved.

Furthermore, the first chip, the second chip and the PCB are physically connected through the photoetching bonding material and cover the peripheral area of the conductive bump, so that the filling and glue pouring process in the prior art can be omitted. When the subsequent plastic packaging process is carried out, the plastic packaging material does not need to fill gaps among the first chip, the second chip and the PCB, so that the time of the plastic packaging process is saved. In addition, the photoetching bonding material has a smaller elastic modulus, so that the photoetching bonding material can be easily deformed and cannot be damaged when being subjected to thermal stress, and the bonding stress of the first chip, the second chip and the PCB is reduced.

Furthermore, the photoetching bonding material can define the position of the conductive bump, so that the conductive bump is prevented from laterally overflowing in the electroplating process.

Further, by bonding a third chip on the first chip and/or the second chip, space utilization is improved and versatility of the device is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 to fig. 7 are schematic structural diagrams corresponding to different steps in a system-in-package method provided in embodiment 1 of the present invention;

fig. 8 to 9 are schematic structural diagrams corresponding to different steps in the system-in-package method according to embodiment 2 of the present invention;

fig. 10 is a schematic diagram of a system in package structure provided in embodiment 5 of the present invention;

fig. 11 is a schematic diagram of a system in package structure provided in embodiment 6 of the present invention.

Reference numerals: reference numerals: 10. a first cavity; 11. a second cavity; 21. a substrate; 22. a dielectric layer; 31. a first connection block; 32. a conductive plug; 40. a first pad; 41. a third pad; 42. a fourth pad; 50. a lithographically bondable material; 51. a third cavity; 60. a second pad; 61. a fifth pad; 62. a sixth pad; 70. a conductive bump; 70a, a void; 100. a first chip; 200. a second chip; 300. a third chip; 400. and (7) plastic packaging layer.

Detailed Description

The system-in-package method and the package structure of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.

The terms "first," "second," and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.

Example 1

The embodiment 2 provides a system-level packaging method, which includes the following steps:

s01: providing a PCB, wherein the PCB comprises a front surface and a back surface which are opposite, the surface of the front surface of the PCB is provided with a plurality of exposed first welding pads 40, the surface of the back surface of the PCB is provided with a plurality of exposed third welding pads 41, the surface of the front surface of the PCB forms a first cavity 10, and at least part of the first welding pads 40 are positioned below the first cavity 10;

s02: providing a first chip 100, wherein the surface of the first chip 100 is provided with a plurality of exposed second bonding pads 41;

s03: bonding the first chip 100 to the bottom of the first cavity 10 through a connection layer, wherein the first pad 40 is opposite to the second pad 60 to form a gap 70 a;

s04: providing a second chip 200, wherein the surface of the second chip 200 is provided with a plurality of exposed fourth bonding pads 42, the second chip 200 is bonded to the back surface of the PCB through a connecting layer, and the third bonding pads 41 are opposite to the fourth bonding pads 42 to form a gap;

s05: a conductive bump 70 is formed in the gap by an electroplating process, and the first pad 40 and the second pad 60 and the third pad 41 and the fourth pad 42 are electrically connected through the conductive bump 70.

It should be noted that step S0N does not represent a sequential order.

Fig. 1 to fig. 6 are schematic structural diagrams corresponding to steps of the system-in-package method according to the embodiment. The system-in-package method will be described in detail with reference to fig. 1 to 6.

Referring to fig. 1, a PCB is provided, the PCB includes opposite front and back surfaces, the front surface of the PCB has a plurality of exposed first pads 40, the back surface of the PCB has a plurality of exposed third pads 41, the front surface of the PCB forms a first cavity 10, and at least a portion of the first pads 40 is located below the first cavity 10.

The PCB comprises at least one layer of plates, each layer of plates at least comprises a substrate 21 and an interconnection structure positioned in the substrate 21, and the first welding pads 40 are positioned on the top layer of substrate 21 and electrically connected with the interconnection structure; forming a dielectric layer 22 on the top substrate 21, etching the dielectric layer 22 to form a first cavity 10 and expose a part of the first pad 40; the surface of the back surface of the PCB board has a plurality of exposed third pads 41.

There are many methods for forming the PCB, and an embodiment will be described below.

With continued reference to fig. 1, a substrate 21 is provided, the material of the substrate 21 comprising a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, among others.

The PCB board includes: at least one substrate 21, a conductive plug 32 located in the substrate 21, wherein the first bonding pad 40 is located on the top substrate 21 and electrically connected to the conductive plug 32. The substrate 21 may be a single-layer board, a double-layer board, a three-layer board, a four-layer board, etc., and specifically, the number of layers of the substrate 21 may be determined according to actual requirements. In this embodiment, the substrate 21 is a double-layer board, the PCB board includes the substrate 21, the first pad 40 located on the surface of the substrate 21, and an interconnection structure electrically connected to the first pad 40, the interconnection structure includes a conductive plug 32 and a first connection block 31 formed on a surface opposite to the first pad 40, and the first connection block 31 is electrically connected to the conductive plug 32. In the present invention, the substrate 21 may be a ceramic substrate.

The PCB board still includes: a dielectric layer 22 formed on the top substrate 21; in other embodiments, a dielectric layer 22 is also formed on the underlying substrate 21.

The method of forming the first cavity 10 includes: the dielectric layer 22 is etched to form a first cavity 10, where the first cavity 10 may penetrate through the dielectric layer 22 or may penetrate through a part of the dielectric layer 22, and the first cavity 10 in this embodiment penetrates through the dielectric layer 22.

In the prior art, the top layer of the PCB board is a solder resist layer and a solder-assist layer, and the solder resist layer covers the top surface of the PCB board and exposes the solder pads. In the invention, the top layer of the PCB can be the same as the top layer of the PCB in the prior art, and the top surface is provided with a solder mask layer and a solder mask; in the invention, the electric connection between the first chip and the PCB is not required to be realized by welding, so that the top surface of the PCB can be not provided with a solder mask (green oil) or a soldering assistant layer. The top layer and the bottom layer can be dielectric layers 22 with photoetching bonding characteristics, and the first welding pads 40 are embedded in the substrate 21 and partially exposed. When the top layer and the bottom layer are the dielectric layers 22 with the photoetching bonding characteristics, the dielectric layers 22 with certain thicknesses can be selected according to requirements, the first chip and the second chip can be conveniently bonded to the PCB in the follow-up process, and no bonding layer needs to be additionally formed, so that the process can be saved, and the forming efficiency of the PCB is improved.

The first bonding pad 40 is used for subsequent electrical connection with the first chip, the third bonding pad 41 is used for subsequent electrical connection with the second chip, and the material of the first bonding pad 40 and the third bonding pad 41 is a conductive material, and may be any one of copper, titanium, aluminum, gold, zinc, or chromium, or any combination thereof.

The dielectric layer 22 material includes silicon oxide, silicon nitride, etc., and may be formed by a deposition process.

Referring to fig. 2, after the PCB is formed, connection layers are formed on the front and rear surfaces of the PCB, the connection layers covering regions around the conductive bumps to be subsequently formed.

It should be noted that the connection layer is at least partially located on the substrate 21 below the first cavity 10.

The connecting layer comprises one or a combination of a lithographically bondable material, a die attach film, a metal, a dielectric layer, or a polymeric material.

In this embodiment, the connection layer is a lithographically bondable material 50, the lithographically bondable material 50 has a thickness of 60-160 μm, and the lithographically bondable material 50 covers at least 10% of the area of the subsequent first chip and the second chip. When the first chip, the second chip and the PCB are bonded subsequently, the photoetching bonding material 50 with a larger area is formed, and particularly, the photoetching bonding material 50 layer is formed at a position where the plastic packaging layer is not easy to fill in a later process, so that when the plastic packaging layer is formed subsequently, the first chip and the second chip can be ensured to be sealed together by the plastic packaging layer and the photoetching bonding material 50 layer, no gap exists at the peripheries of the first chip and the second chip, the structural strength of a device can be improved, and the yield is improved.

The material of the lithographically bondable material 50 may be a liquid dry film or a film-like dry film, the liquid dry film may be spin-coated on the surface of the PCB, and the film-like dry film may be attached to the surface of the PCB. Because the elastic modulus is smaller, the chip can be easily deformed and cannot be damaged when being subjected to thermal stress, and therefore the subsequent combination stress of the first chip, the second chip and the PCB is reduced. The photo-lithographically bondable material 50 covers the area around the subsequently formed conductive bump, directly enhancing the mechanical strength of the whole structure and eliminating the filling and glue-pouring process in the prior art.

In other embodiments, the connection layer has a first opening, and the first opening is surrounded by the subsequent first chip and/or the PCB board to form a third cavity (not shown in the figure), and the third cavity is used as a working cavity of the subsequent first chip.

The forming method of the third cavity comprises the following steps:

forming a photoetching-capable bonding material 50 on the surface of the subsequent first chip, and etching the photoetching-capable bonding material to form the third cavity, or forming a photoetching-capable bonding material 50 at the bottom of at least the first cavity 10 of the PCB board, and etching the photoetching-capable bonding material 50 to form the third cavity.

The third cavity provides a working cavity environment for the first chip, and no additional sealing cover is needed, so that the process is simplified.

Referring to fig. 3, a first chip 100 is provided, and a surface of the first chip 100 has a plurality of exposed second bonding pads 60.

The first chip 100 contains a cavity (not shown) or no cavity.

The number of the first chips 100 is plural, and the plural first chips 100 may be chips having the same function; the plurality of first chips 100 may also include at least two chips with different functions, and the chips with different functions are integrated together to realize a certain function. The first chip 100 may be a passive device including a capacitor, an inductor, and a connection chip (an electrical connection block for electrical connection), or an active device including a sensor module chip, a MEMS chip, a filter chip, a logic chip, and a memory chip.

The sensor module chip comprises a module chip which at least senses one of radio frequency signals, infrared radiation signals, visible light signals, sound wave signals and electromagnetic wave signals. The module chip for sensing the radio frequency signal may be a radio frequency module chip applied in a 5G device, but is not limited to a 5G radio frequency sensor module chip, and may also be other types of radio frequency module chips. The module chip for receiving the infrared radiation signal may be an infrared sensor module chip using the infrared radiation signal for temperature measurement or imaging in thermal imagers, forehead temperature guns, other types, and the like. The sensor module chip can also be a camera module chip, such as a module chip including a photosensitive chip and an optical filter, which can receive visible light for imaging. The sensor module chip can also be a microphone module chip which can receive sound waves for transmitting sound signals. The sensor module chip in the present invention is not limited to the type listed herein, and may be various types of sensor module chips that can perform a certain function in the art.

In this embodiment, each of the first chips 100 is provided with two second bonding pads 60, in other embodiments, the number of the second bonding pads 60 of the first chip 100 may be multiple, the material of the second bonding pads 60 is the same as that of the first bonding pads 40, which is not described herein again, and the second bonding pads 60 are used for subsequent electrical connection with the first bonding pads 40.

Referring to fig. 4, the first chip 100 is bonded to the bottom of the first cavity 10 through a connection layer, and the first pad 40 is opposite to the second pad 60 to form a gap 70 a.

The height of the first voids 70a is 60-160 μm, such as 60 μm, 80 μm, 120 μm. When the height of the first gap 70a is 60-160 μm, the distance between the two sides of the first chip 100 and the side wall of the first cavity 10 is 40-100 μm, which not only meets the requirement that the subsequent electroplating solution easily enters the first gap 70a for electroplating, but also avoids the problem that the electroplating time is long due to the too high height of the first gap 70a, thereby taking the electroplating efficiency and the electroplating yield into consideration.

Referring to fig. 5, a second chip 200 is provided, wherein a surface of the second chip 200 has a plurality of exposed fourth pads 42; and bonding the second chip 200 to the back surface of the PCB through a connection layer, wherein the third pad 41 is opposite to the fourth pad 42 to form a gap.

The second chip 200 may or may not be of the same type as the first chip 100. The material of the fourth bonding pad 42 is the same as that of the first bonding pad 40, and will not be described in detail herein.

It should be noted that the time for bonding the second chip 200 to the PCB may be before, after, or simultaneously with the bonding of the first chip 100 to the PCB, and the order is not limited.

Referring to fig. 6, a conductive bump 70 is formed in the gap 70a through an electroplating process, and the first pad 40 and the second pad 60 and the third pad 41 and the fourth pad 42 are electrically connected through the conductive bump 70.

In the invention, the electroplating process comprises chemical plating. The plating solution used in the electroless plating is determined according to the material of the conductive bump 70 and the materials of the first pad 40, the second pad 60, the third pad 41, and the fourth pad 42, which are actually required to be formed. The material of the first bonding pad 40, the second bonding pad 60, the third bonding pad and the fourth bonding pad is selected from any one of copper, titanium, aluminum, gold, zinc or chromium or any combination thereof. The cross-sectional area of the conductive bump 70 is greater than 10 square microns; the material of the conductive bump 70 includes: any one or any combination of copper, titanium, aluminum, gold, zinc, or chromium.

Optionally, electroless palladium plating and immersion gold, wherein the time of electroless nickel is 30-50 minutes, the time of electroless gold is 4-40 minutes, and the time of electroless palladium is 7-32 minutes; or, chemical nickel and gold, wherein the chemical nickel time is 30-50 minutes, and the chemical gold time is 4-40 minutes.

When the electroplating process selects electroless palladium immersion gold (ENEPIG) or electroless nickel gold (ENIG), the process parameters can be referred to table 1 below.

TABLE 1

Before chemical plating, in order to better finish an electroplating process, the surface of the welding pad can be cleaned firstly to remove a natural oxidation layer on the surface of the welding pad and improve the surface wettability (wettabilities) of the welding pad; an activation process may then be performed to promote nucleation growth of the plating metal on the metal to be plated.

Referring to fig. 7, after forming the conductive bump 70, the method further includes: a molding layer 400 is formed to cover the PCB and the first and

second chips

100 and 200.

The molding layer 400 may be formed using a compression molding process, a transfer molding process, a liquid seal molding process, a vacuum lamination process, or a spin coating process. The plastic package layer 400 comprises the following materials: polyimide, silicone, epoxy, curable polymer-based materials, or curable resin-based materials.

In the embodiment, the gaps between the first chip 100 and the second chip 200 and the PCB are completely filled with the lithographically bondable material 50, so that the molding compound layer 400 does not need to be filled between the first chip 100, the second chip 200 and the PCB, and the time of the molding process can be saved. Of course, in the present invention, if there is a gap between the first chip 100, the second chip 200 and the PCB that is not completely occupied by the lithographically bondable material 50, the molding compound 400 may enter the gap, and perform better insulation, sealing and protection functions on the first chip 100 and the second chip 200.

According to the invention, the first cavity is formed on the front surface of the PCB, and the first chip is bonded at the bottom of the first cavity through the connecting layer by a bonding process, so that the first chip is connected with the front surface of the PCB; providing a second chip, and bonding the second chip on the back of the PCB through a connecting layer by a bonding process, so that the integration height of the device is reduced, the space utilization rate is improved, and the integration level of the device is improved; in addition, the traditional packaging process for realizing the electrical connection between the chip and the PCB by welding is completely avoided, the conductive bumps are formed by the electroplating process so as to realize the electrical connection between the first chip and the second chip and the PCB, and firstly, the process flow is simplified, and the packaging efficiency is improved; and secondly, the conductive bump is formed between the chip and the PCB through an electroplating process, so that the traditional step of bonding the chip on the wafer is omitted, the process is simplified, the process difficulty is reduced, the integration level is improved, and the conductivity of the packaging structure is improved. Furthermore, after all the chips are bonded on the PCB, the electric connection between each chip and the PCB is formed through an electroplating process, and compared with the traditional method that each chip is independently welded and electrically connected with the PCB, the packaging efficiency is greatly improved.

Example 2

Referring to fig. 8 and fig. 9, the present embodiment 2 provides a schematic structural diagram corresponding to each step of another system-in-package method. The system-in-package method will be described in detail with reference to fig. 8 to 9.

The present embodiment 2 is different from the present embodiment 1 in that:

a second cavity 11 is formed on the surface of the back surface of the PCB, at least a portion of the third pad 41 is exposed from the second cavity 11, and the second chip 200 is bonded to the bottom of the second cavity 11 through a connection layer.

Referring to fig. 8, a second cavity 11 is formed on the surface of the back surface of the PCB, and at least a portion of the third pad 41 is exposed from the second cavity 11.

The method for forming the second cavity 11 comprises the following steps: the dielectric layer 22 is etched to form a second cavity 11, where the second cavity 11 may penetrate through the dielectric layer 22 or may penetrate through a part of the dielectric layer 22, and the second cavity 11 in this embodiment penetrates through the dielectric layer 22.

Referring to fig. 9, a second chip 200 is provided, said second chip 200 being bonded to the bottom of said second cavity 11 by means of a connection layer.

The material of the connection layer is referred to in example 2, and will not be described in detail here.

The rest of the process is the same as example 1, with specific reference to example 1.

Example 3

Referring to fig. 6 and 7, the present embodiment provides a system in package structure, and fig. 6 shows a schematic diagram of the system in package structure of embodiment 3, and referring to fig. 6, the system in package structure includes:

the PCB comprises a front surface and a back surface which are opposite, the front surface of the PCB is provided with a plurality of exposed first welding pads 40 and a first cavity 10, and at least part of the first welding pads 40 are positioned below the first cavity 10; the back surface of the PCB is provided with a plurality of exposed third welding pads 41;

a first chip 100, wherein the surface of the first chip 100 has a plurality of exposed second bonding pads 40, the first chip 100 is bonded at the bottom of the first cavity 10 through a connection layer, and the first bonding pads 40 are arranged opposite to the second bonding pads 60;

a second chip 200, wherein the surface of the second chip 200 has a plurality of exposed fourth pads 42, the second chip 200 is bonded to the back surface of the PCB through a connection layer, and the third pads 41 are disposed opposite to the fourth pads 42;

and conductive bumps 70 formed between the first and

second pads

40 and 60 and between the third and

fourth pads

41 and 42 by an electroplating process to electrically connect the first and

second pads

40 and 60 and the third and

fourth pads

41 and 42.

In this embodiment, the PCB board includes: at least one substrate 21, a conductive plug 32 located in the substrate 21, wherein the first bonding pad 40 is located on the top substrate 21 and electrically connected to the conductive plug 32. The substrate can be a single-layer board, a double-layer board, a three-layer board, a four-layer board and the like, and specifically, the number of layers of the substrate 21 can be determined according to actual requirements. In this embodiment, the substrate 21 is a double-layer board, the PCB board includes the substrate 21, the first pad 40 located on the surface of the substrate 21, and an interconnection structure electrically connected to the first pad 40, the interconnection structure includes a conductive plug 32 and a first connection block 31 formed on a surface opposite to the first pad 40, and the first connection block 31 is electrically connected to the conductive plug 32. In the present invention, the substrate 21 may be a ceramic substrate.

The PCB board still includes: and the dielectric layer 22 is positioned on the top substrate 21, the dielectric layer 22 is provided with a first cavity 10, and the first welding pad 40 is positioned below the first cavity 10 and at least partially exposed in the first cavity 10. A plurality of exposed third pads 41 are formed on the rear surface of the PCB.

Please refer to embodiment 1 for a method for forming the first cavity 10, which is not described herein again.

The first chip 100 contains a cavity (not shown) or no cavity.

The number of the first chips 100 is plural, and the plural first chips 100 may be chips having the same function; the plurality of first chips 100 may also include at least two chips with different functions, and the chips with different functions are integrated together to realize a certain function. The first chip 100 may be a passive device including a capacitor, an inductor, and a connection chip (an electrical connection block for electrical connection), or an active device including a sensor module chip, a MEMS chip, a filter chip, a logic chip, and a memory chip. The second chip 200 may be the same as or different from the first chip 100, and is not limited.

Specifically, the first chip 100, the second chip 200 and the PCB are physically connected by the lithographically bondable material 50, and the lithographically bondable material 50 avoids the pad arrangement and covers the peripheral region of the conductive bump 70.

The first chip 100, the second chip 200 and the PCB are physically connected by the photo-etching bonding material 50, and the photo-etching bonding material 50 covers the peripheral area of the conductive bump 70, on one hand, the mechanical strength of the whole structure is directly enhanced, and the filling and glue filling process in the prior art can be omitted, on the other hand, the photo-etching bonding material 50 can be easily deformed and not damaged when being subjected to thermal stress due to the small elastic modulus, so that the bonding stress between the first chip 100, the second chip 200 and the PCB is reduced.

Referring to fig. 7, further includes: and a plastic sealing layer 400, wherein the plastic sealing layer 400 covers the PCB and the first chip 100 and the second chip 200.

The material and function of the molding layer 400 are described in example 1 and will not be described here.

Example 4

Referring to fig. 9, the present embodiment provides another system in package structure, and the difference between the present embodiment 4 and the embodiment 3 is: a second cavity 11 is formed on the surface of the back surface of the PCB, at least a portion of the third pad 41 is exposed from the second cavity 11, and the second chip 200 is bonded to the bottom of the second cavity 11 through a connection layer.

The method for forming the second cavity 11 includes: a dielectric layer 22 is formed on the bottom substrate 21, the dielectric layer 22 is etched to form a second cavity 11, the second cavity 11 may penetrate through the dielectric layer 22, or may penetrate through a part of the dielectric layer 22, and the second cavity 11 in this embodiment penetrates through the dielectric layer 22.

Bonding the first chip at the bottom of the first cavity through a connecting layer by a bonding process to realize the connection of the first chip and the front surface of the PCB; and the second chip is bonded at the bottom of the second cavity through a connecting layer by a bonding process, so that the integration height of the device is reduced, the space utilization rate is improved, and the integration level of the device is improved.

The other structure is the same as that of embodiment 3, and please refer to embodiment 3 specifically.

Example 5

Referring to fig. 10, the present embodiment 5 provides a system-in-package structure, which is different from the embodiment 3 in that: a third chip 300 is bonded to the first chip 100.

Specifically, a sixth bonding pad 62 is formed on the third chip 300, a plurality of exposed fifth bonding pads 61 are formed on a surface of the first chip 100 opposite to the second bonding pad 60, the third chip 300 is connected to the first chip 100 through the lithographically bondable material 50, and the fifth bonding pad 41 is electrically connected to the sixth bonding pad 42 through the conductive bump, so that the first chip 100 is electrically connected to the third chip 300.

By bonding the third chip 200 on the first chip 100, space utilization can be improved and versatility of the device can be improved.

In other embodiments, the third chip 300 is bonded to the second chip 200 or both the first chip 100 and the second chip 200, further improving space utilization and device versatility.

Example 6

Referring to fig. 11, the present embodiment 6 provides another system in package structure, and the present embodiment 6 is different from the present embodiment 3 in that the lithographically bondable material 50 of the present embodiment 3 has a first opening, and the first opening is surrounded by the first chip 100 and the PCB board to form a third cavity 51.

In this embodiment, the cavity is required to be disposed below the first chip 100, and in other embodiments, the cavity may not be required to be disposed below a portion of the first chip 100. The third cavity 51 provides a working cavity environment for the first chip 100, and no additional capping is required, thereby simplifying the process.

In other embodiments, the lithographically bondable material 50 has a first opening that is surrounded by the second chip 200 and the PCB board backside to form a fourth cavity (not shown).

The other parts are the same as those in embodiment 1, and are not described herein.

It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A system-in-package method, comprising:

providing a PCB, wherein the PCB comprises a front surface and a back surface which are opposite, the surface of the front surface of the PCB is provided with a plurality of exposed first welding pads, the surface of the back surface of the PCB is provided with a plurality of exposed third welding pads, a first cavity is formed on the surface of the front surface of the PCB, and at least part of the first welding pads are positioned below the first cavity;

2. The system-in-package method according to claim 1, wherein a second cavity is formed on the surface of the back surface of the PCB board, at least a portion of the third bonding pad is exposed from the second cavity, and the second chip is bonded to the bottom of the second cavity through a connection layer.

3. The system-in-package method according to claim 1, wherein the PCB board comprises:

the first welding pad is positioned on the top layer substrate and is electrically connected with the interconnection structure;

and forming a dielectric layer on the top substrate, etching the dielectric layer to form a first cavity and expose part of the first welding pad.

4. The system-in-package method according to claim 1, comprising:

the distance between the two sides of the first chip and the side wall of the first cavity is 40-100 μm.

5. The system-in-package method of claim 1, wherein the connection layer comprises one or a combination of a lithographically bondable material, a die attach film, a metal, a dielectric layer, or a polymer material.

6. The system-in-package method according to claim 5, wherein the lithographically bondable material has a thickness of 60-160 μm.

7. The system-in-package method according to claim 5, wherein the lithographically bondable material covers an area at the periphery of the conductive bumps.

8. The system-in-package method according to claim 1, wherein the connection layer has a first opening, and the first opening is surrounded by the first chip and/or the front side of the PCB board to form a third cavity, and the third cavity is used as a working cavity of the first chip; and/or the first opening is surrounded by the second chip and/or the back surface of the PCB board to form a fourth cavity, and the fourth cavity is used as a working cavity of the second chip.

9. The system-in-package method according to claim 6, wherein the third cavity and/or the fourth cavity extends through the connection layer or through a portion of the connection layer.

10. The system-in-package method according to claim 1, wherein the cross-sectional area of the conductive bump is greater than 10 square microns.

11. The system-in package method according to claim 5, wherein the lithographically bondable material comprises a dry film in the form of a film or a dry film in the form of a liquid.

12. The system-in-package method according to claim 5, wherein the lithographically bondable material covers at least 10% of the area of the first and second chips.

13. The system-in-package method according to claim 1, further comprising forming a molding compound layer after forming the conductive bumps, the molding compound layer covering the first chip, the second chip and the PCB board.

14. A system in a package structure, comprising:

the PCB comprises a front surface and a back surface which are opposite, the front surface of the PCB is provided with a plurality of exposed first welding pads and a first cavity, and at least part of the first welding pads are positioned below the first cavity; the back surface of the PCB is provided with a plurality of exposed third welding pads;

15. The system-in-package structure of claim 14, wherein a second cavity is formed on the surface of the back surface of the PCB, at least a portion of the third pad is exposed by the second cavity, and the second chip is bonded to the bottom of the second cavity through a connection layer.

16. The system-in package structure according to claim 14, wherein the connection layer comprises a lithographically bondable material having a thickness of 60-160 μ ι η, the lithographically bondable material covering regions at the periphery of the conductive bumps.

17. The system-in-package structure according to claim 14, wherein the connection layer has a first opening, the first opening is surrounded by the first chip and/or the PCB board to form a third cavity, and the third cavity is a working cavity of the first chip; and/or the first opening is surrounded by the second chip and/or the back surface of the PCB board to form a fourth cavity, and the fourth cavity is used as a working cavity of the second chip.

18. The system-in-package structure according to claim 17, wherein the third and/or fourth cavity extends through the connection layer or through a portion of the connection layer.

19. The system-in-package structure of claim 14, wherein the PCB board comprises:

the dielectric layer is positioned on the top substrate and provided with a first cavity, and the first welding pad is positioned below the first cavity and at least partially exposed in the first cavity.

20. The system-in-package structure of claim 14,

and bonding a third chip on the first chip and/or the second chip, wherein the third chip is electrically connected with the first chip and/or the second chip through a conductive bump or a solder ball formed by an electroplating process.